| :lib:`sky130_fd_pr_base` - Primitive Device library |
| ============================ |
| |
| All devices for the SKY130 technology reside in the design library s8phirs_10r for customer usage and legacy libraries tech and technology_library for compatibility with the IP. Categories are included in s8phirs_10r to simplify device selection. |
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| Units |
| ----- |
| |
| All values in the pcells are specified in microns (e.g. a width of 0.5 implies a width of 0.5μm). |
| |
| |
| FETs |
| ---- |
| |
| The SKY130 FET models with fixed W and L are carefully characterized to ensure optimal hardware correlation. The pcell does allow a user defined geometry ("Model name" = userDefined), but this model has not been carefully scrutinized across all configurations. This custom geometry model should only be used for evaluation purposes. All layouts and final simulations should be based on fixed geometry FET models. |
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| The FETs are available for Layout XL in V1.3.0. |
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| Layout XL |
| ~~~~~~~~~ |
| |
| The supported nfet options are nhv, nhvesd, nhvnative, nhvnativeesd, nlowvt, nshort, and ntvnative. For additional layout options without LayoutXL compatibility, the designer may use the symbolic layout nfet_symbolic in s8phirs_10r. |
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| The supported pfet options are phighvt, pshort, phv, plowvt, and phvesd. For additional layout options without LayoutXL compatibility, the designer may use the symbolic layout pfet_symbolic in s8phirs_10r. |
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| The Layout XL FET pcell options include: |
| |
| * Model Name: dropdown options of supported devices followed by unsupported devices in LayoutXL |
| * Length: dropdown options for device length |
| * Width Per Finger: dropdown options for device width |
| * Source Voltage: dropdown options for supply voltage limit\* |
| * Drain Voltage: dropdown options for drain voltage limit\* |
| * Number of Fingers (m) |
| * Multiplicity (mult) |
| * Body Contact: none or leftDetached\* |
| |
| \*This option is only available for the PFET. |
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| Simulation |
| ~~~~~~~~~~ |
| |
| There are additional features in the schematic, indicated below: |
| |
| * Area source [μm2]: calculated automatically |
| * Perimeter source [μm]: calculated automatically |
| * Area drain [μm2]: calculated automatically |
| * Perimeter drain [μm]: calculated automatically |
| * Source Num Squares (nrs): calculated automatically |
| * Drain Num Squares (nrd): calculated automatically |
| * No Noise?: option to remove noise from model if enabled |
| * Dist. Diff Edge A (sa) [μm] |
| * Dist. Diff Edge B (sb) [μm] |
| * Dist. Btwn. Fingers (sd) [μm] |
| * Zero bias thresh. V shift |
| * Enable gate resistor?: option to define gate resistance using one of two presets or a custom value |
| |
| The user can modify sa, sb, and sd (in microns). The schematic below was used to simulate the effect of sweeping sa (set to psa) on current Id. |
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| |process1| |
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| The nfet and pfet were both in deep saturation, with the nfet’s Vgs and Vds set to VDD, and the pfet’s Vgs and Vds set to –VDD. Parameter psa was swept from 0 to 2, and generated the waveforms illustrated in Figure 2, with the nfet in purple and the pfet in white. Note that the impact of sa/sb/sd will be geometry dependent, and the plot is specific for one geometry. |
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| |process2| |
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| The default value of sa, sb, and sd is 0. Note that at sa equal to 0, the current is approximately equivalent to that at sa equal to 1.083. In the valid region, the nfet varies by roughly ±3% and the pfet ranges by ±6%. |
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| Resistors |
| --------- |
| |
| S8PHIRS_10R supports a variety of resistors listed in Table 2: |
| |
| .. table:: Resistor models |
| |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | **Device** | **Cell** | **Type** | **Model** | **Description** | **Sheet Resistance (Ω/□)** | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | **Resistor** | res | poly | mrp1 | poly | 48.2 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | li1 | mrl1 | li1 | 12.8 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | res3 | poly | xhrpoly_0p35 | Fixed width poly resistor | | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | | xhrpoly_0p69 | | | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | | xhrpoly_1p41 | | 319.8 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | | xhrpoly_2p85 | | | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | | xhrpoly_5p73 | | | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | respw | pwell | xpwres | Fixed width P well resistor (in DNW) | 4400 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | resn | diff | mrdn | N diffusion resistor | 120 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | resp | diff | mrdp | P diffusion resistor | 197 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | **Parasitic resistance + capacitance** | rescap\* | poly | mrp1 | parasitic poly | 48.2 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | li1 | mrl1 | parasitic li1 | 12.8 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | met1 | mrm1 | parasitic metal1 | 0.125 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | met2 | mrm2 | parasitic metal2 | 0.125 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | met3 | mrm3 | parasitic metal3 | 0.047 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | met4 | mrm4 | parasitic metal4 | 0.047 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| | | | met5 | mrm5 | parasitic metal5 | 0.0285 | |
| +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+ |
| |
| Bent resistor symbolic layout pcells are available for res of type poly (PYbentRes), resn (nDFbentRes) and resp (pDFbentRes) resistors. Bent resistors are neither modeled nor supported in LVS. |
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| resn, resp, res type poly and li1, and respw are all supported in LayoutXL. |
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| res3 is not currently supported in LayoutXL. |
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| respw is a p well resistor placed in deep NW with a fixed 2.65μm width and a variable length. The minimum length is 26.5μm. |
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| \*rescap is a parasitic resistor/capacitor that can be used for simulation only. All of the cap models are available except the following: mcm5m4m3, mrcdlm3p1, mcm5l1p1, mcm5m3m2, mcm5m2m1. |
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| Capacitors |
| ---------- |
| |
| This PDK includes 26 vertical parallel plate (VPP) capacitors that can be simulated using 3-terminal cap_int3 and 4-terminal vppcap. The various options detailed in Table 3 are all supported in LayoutXL. Twelve of these VPPs have shields on their top layer. |
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| .. table:: VPP Capacitors |
| |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | **Cell** | **Model** | **Size X** | **Size Y** | **Bottom Layer** | **Top Layer** | **Shield** | **Cap [fF]** | **C0 par [fF]** | **C1 par [fF]** | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp5 | 2.42 | 4.59 | M1 | M2 | none | 4.37 | 0.84 | 0.29 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp4p4x4p6_m1m2 | 4.38 | 4.59 | M1 | M2 | none | 7.81 | 1.24 | 0.39 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp4 | 4.38 | 4.59 | M1 | M2 | none | 9.48 | 0.81 | 0.82 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp4p4x4p6_m3_lim5shield | 4.38 | 4.59 | LI1 | M5 | top | 10.80 | 1.90 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp_hd5_atlas_fingercap_l5 | 2.70 | 6.10 | M1 | M4 | none | 12.13 | 1.00 | 0.70 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp_hd5_atlas_fingercap2_l5 | 2.85 | 6.10 | M1 | M4 | none | 12.65 | 1.23 | 0.71 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp_hd5_atlas_fingercap_l10 | 2.70 | 11.10 | M1 | M4 | none | 23.35 | 1.51 | 1.08 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp6p8x6p1_lim4shield | 6.80 | 6.09 | LI1 | M4 | top | 26.60 | 3.00 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp_hd5_atlas_wafflecap2 | 5.90 | 5.90 | M1 | M4 | none | 27.78 | 2.11 | 0.50 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp6p8x6p1_polym4shield | 6.84 | 6.13 | POLY | M4 | top | 33.80 | 6.50 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp3 | 8.58 | 7.84 | M1 | M2 | none | 35.00 | 1.84 | 1.84 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp8p6x7p9_m3_lim5shield | 8.58 | 7.84 | LI1 | M5 | top | 42.50 | 4.30 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp_hd5_atlas_fingercap_l20 | 2.70 | 21.10 | M1 | M4 | none | 45.83 | 2.49 | 1.82 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp11p5x11p7_m1m2 | 11.41 | 11.69 | M1 | M2 | none | 74.60 | 4.11 | 2.01 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp_hd5_atlas_fingercap_l40 | 2.70 | 41.10 | M1 | M4 | none | 91.27 | 5.99 | 2.62 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp11p5x11p7_m3_lim5shield | 11.41 | 11.69 | LI1 | M5 | top | 97.30 | 7.40 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp11p5x11p7_m1m4 | 11.41 | 11.69 | M1 | M5 | none | 110.19 | 4.87 | 1.87 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp_hd5_atlas_wafflecap1 | 11.33 | 11.33 | M1 | M4 | none | 110.41 | 1.76 | 1.45 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp11p5x11p7_lim5shield | 11.41 | 11.69 | LI1 | M5 | top | 116.80 | 7.40 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp11p5x11p7_m4shield | 11.41 | 11.69 | LI1 | M4 | top | 118.50 | 5.00 | 2.40 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp11p5x11p7_polym4shield | 11.45 | 11.73 | POLY | M4 | top | 121.90 | 17.70 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp11p5x11p7_m5shield | 11.41 | 11.69 | LI1 | M5 | top | 137.40 | 5.40 | 2.30 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp11p5x11p7_polym5shield | 11.45 | 11.73 | POLY | M5 | top | 141.20 | 18.10 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvpp11p5x11p7_polym50p4shield | 11.45 | 11.73 | POLY | M5 | top | 141.20 | 18.10 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | vppcap | xcmvppx4_2xnhvnative10x4 | 11.34 | 11.69 | DIFF | M5 | top | 340.90 | ~0 | ~0 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| | cap_int3 | xcmvpp_hd5_4x2 | 44.69 | 23.09 | POLY | M5 | none | 1470.00 | 51.70 | 48.60 | |
| +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+ |
| |
| Two scalable Metal-insulator-Metal (MiM) capacitors are available and supported in LayoutXL, as specified in Table 4. One is on metals 3 and 4, the other is on metals 4 and 5. These devices are defined in section tt_rc of the design_wrapper.lib.scs, which is discussed in Section 8.7.1.2. The MiM can also be made into an array by increasing the number of rows and columns from 1; currently this generates a layout pcell with the top plates connected, but the bottom plates will need to be connected as well. |
| |
| .. table:: MiM Capacitor Models |
| |
| +----------+-----------+----------------------+---------------------+--------------------+ |
| | **Cell** | **Model** | **Description** | **Cap** | **Nominal Corner** | |
| +----------+-----------+----------------------+---------------------+--------------------+ |
| | cmimc | xcmimc1 | MiM Capacitor, M3-M4 | 2.2 fF/μm\ :sup:`2` | tt_rc | |
| +----------+-----------+----------------------+---------------------+--------------------+ |
| | | xcmimc2 | MiM Capacitor, M4-M5 | 2.2 fF/μm\ :sup:`2` | tt_rc | |
| +----------+-----------+----------------------+---------------------+--------------------+ |
| |
| Two varactors are available as well, and described in Table 5. These varactors are supported in LayoutXL. The bulk must always be tied to ground. |
| |
| .. table:: Varactor Models |
| |
| +----------+-----------+-----------------------+------------------------+--------------------+ |
| | **Cell** | **Model** | **Description** | **Cap@V(c0,c1)>400mV** | **Nominal Corner** | |
| +----------+-----------+-----------------------+------------------------+--------------------+ |
| | capbn_b | xcnwvc | Varactor | >8.096fF/μm\ :sup:`2` | tt_fet & tt_parRC | |
| +----------+-----------+-----------------------+------------------------+--------------------+ |
| | | xcnwvc2 | Varactor with high Vt | >8.1297/μm\ :sup:`2` | | |
| +----------+-----------+-----------------------+------------------------+--------------------+ |
| |
| BJTs |
| ---- |
| |
| S8 supports two fixed size PNPs and three fixed size NPNs intended for use in bandgap reference circuits. All of the BJTs listed in Table 6 are supported in LayoutXL. The NPNs and PNPs are defined in sections npn_t and tt_fet, respectively, of design_wrapper.lib.scs. For more information, refer to Section 8.7.1.2. |
| |
| .. table:: BJT Models |
| |
| +------------+----------+----------------+-----------------+--------------------+ |
| | **Device** | **Cell** | **Model** | **Description** | **Nominal Corner** | |
| +------------+----------+----------------+-----------------+--------------------+ |
| | **NPN** | npn4 | npnpar1x1 | NPN BJT | npn_t | |
| +------------+----------+----------------+-----------------+--------------------+ |
| | | | npnpar1x2 | | | |
| +------------+----------+----------------+-----------------+--------------------+ |
| | | | npn_1x1_2p0_hv | | | |
| +------------+----------+----------------+-----------------+--------------------+ |
| | **PNP** | pnp4 | pnppar | PNP BJT | tt_fet | |
| +------------+----------+----------------+-----------------+--------------------+ |
| | | | pnppar5x | | | |
| +------------+----------+----------------+-----------------+--------------------+ |
| |
| Diodes |
| ------ |
| |
| The diodes (diode, lvsdiode) in SKY130 represent parasitic diodes and are not intended for forward biased usage. |
| |
| Inductors |
| --------- |
| |
| The schematic elements ind4 and inductor are available for simulation. Fixed geometry inductors are not included in this PDK. Contact SkyWater for information on generating custom inductor models using EM modeling tools. |
| |
| Other |
| ----- |
| |
| Additional devices in the Misc category include the seal ring, various shorts, a metal 4 fuse, pad cells, and the connectivity diode. |
| |
| Seal Ring |
| ~~~~~~~~~ |
| |
| The pcell advSeal_6um is the chip seal ring. |
| |
| Fuse |
| ~~~~ |
| |
| A fuse on metal 4 is available. |
| |
| Connectivity Diode |
| ~~~~~~~~~~~~~~~~~~ |
| |
| The connectivity diode (condiode_grid) is used to check the connectivity of the isolated pwell and the dnwell. This is done to ensure proper biasing of the isolated pwell by extracting the condiode. In the layout, a text label “condiode” is drawn over the isolated pwell using the text.dg layer inside the isolated pwell, which is formed using the dnwell and the nwell ring. The latchup ruledeck checks for the condiode label in the dnwell that is connected to a non-power terminal. |
| |
| 1. Make sure the text label inside the isolated pwell (not over the nwell drawing). Make sure to turn on the lower level hierarchy to ensure the label is not over nwell. |
| 2. Make sure to use the text label at the level of hierarchy intended. |
| 3. Make sure the schematic contains the condiode element. |
| 4. Make sure the diode is connected properly in the schematic. The anode is connected to the isolated pwell term and the cathode is connected to the dnwell term. |
| |
| The newly placed Condiode will have the area and perimeter set to -1 along with the text “WILL NOT EXTRACT” as in the figure. |
| |
| |process3| |
| |
| The element will not extract if the value is set to -1 or both area and perimeter set to 0. The user must update these parameters to the proper value. If the user tried to extract the schematic without updating the Condiode symbol, the extract will fail. |
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| When the element is properly updated with the best estimate area and perimeter of the dnwell the symbol will show: |
| |
| |process4| |
