| Section B: Design Rule Criteria & Assumptions,,,,, |
| ,,,,, |
| "Note: all numbers below are final (S8, on wafer) unless explicitly specified otherwise",,,,, |
| 1. General,,,,, |
| Parameter,,Units,Value,,Variable name |
| Space to Draw,, ,S8,, |
| Grid Size - Drawn,,um,0.005,,GSF |
| Approximate Scale Factor for R32 data,,,0.3,,sfr32 |
| ,,,,, |
| "2. Minimum CDs in Design or on Wafer, Required by Technology (Core or Periphery)",,,,, |
| Layer Name,,,S8,,Variable name |
| ,,, feature,space, |
| Field Oxide,,,0.14,0.27,FOMCD/FOMCDSP |
| Deep N-Well,,,3,6.3,DNMCD/DNMCDSP |
| P-Well Block Mask,,,0.84,1.27,PWBMCD/PWBMCDSP |
| P-Well Drain Extended ,,,0.84,1.27,PWDEMCD/PWDEMCDSP |
| N-Well,,,0.84,1.27,NWMCD/NWMCDSP |
| High Vt PCh,,,0.38,0.38,HVTPMCD/HVTPMCDSP |
| Low Vt Nch,,,0.38,0.38,LVTNMCD/LVTNMCDSP |
| HLow VT PCh Radio,,,0.38,0.38,HVTRMCD/HVTRMCDSP |
| N-Core Implant,,,0.38,0.38,NCMCD/NCMCDSP |
| Tunnel Mask,,,0.41,0.5,TUNMCD/TUNMCDSP |
| ONO Mask,,,0.41,0.5,ONOMCD/ONOMCDSP |
| Low Voltage Oxide,,,0.6,0.7,LVOMCD/LVOMCDSPCSMC |
| Resistor Protect,,,1.27,0.84,RPMCD/RPMCDSP |
| Poly 1,Endcap/Gap,,0.15,0.21,P1G |
| Poly 1,,,N/A,0.14,P1MCD/P1MCDSP |
| N-tip Implant,,,0.84,0.7,NTMCD/NTMCDSP |
| High Volt. N-tip,,,0.7,0.7,HVNTMCD/HVNTMCDSP |
| Lightly Doped N-tip,,,0.7,0.7,LDNTMCD/LDNTMCDSP |
| Nitride Poly Cut,,,0.27,0.27,NPCMCD/NPCMCDSP |
| P+ Implant,,,0.38,0.38,PSDMCD/PSDMCDSP |
| N+ Implant,,,0.38,0.38,NSDMCD/NSDMCDSP |
| Local Intr Cont.1,Slotted,,0.17,0.17,LICM1SLCD/LICM1SLCDSP |
| Local Intr Cont.1,Core,,0.19,0.35,LICM1CD/LICM1CDSP |
| Local Intrcnct 1,Core,,0.14,0.14,LI1MCD/LI1MCDSP |
| Local Intrcnct 1,,,0.17,0.17,LI1MCD/LI1MCDSP |
| Contact,,,0.17,0.19,CTM1CD/CTM1CDSP |
| Open Frame Mask,,,N/A,N/A,OFMCD/OFMCDSP |
| Metal 1,,,0.14,0.14,MM1CD/MM1CDSP |
| Metal 1 - Cu,,,0.14,0.14,MM1_CuCD/MM1_CuCDSP |
| Via,,,0.15,0.17,VIMCD/VIMCDSP |
| Via - Cu,,,0.18,0.13,VIM_CuCD/VIM_CuCDSP |
| Capacitor MiM,,,2,0.84,CAPMCD/CAPMCDSP |
| Metal 2,,,0.14,0.14,MM2CD/MM2CDSP |
| Metal 2 - Cu,,,0.14,0.14,MM2_CuCD/MM2_CuCDSP |
| Via 2-TNV,,,0.28,0.28,VIM2CD/VIM2CDSP |
| Via 2-S8TM,,,0.8,0.8,VIM2CD/VIM2CDSP |
| Via 2-PLM, ,,0.2,0.2,VIM2CD/VIM2CDSP |
| Via 2-Cu, ,,0.21,0.18,VIM2_CuCD/VIM2_CuCDSP |
| Metal 3-TLM,,,0.36,0.36,MM3CD/MM3CDSP |
| Metal 3-S8TM,,,0.8,0.8,MM3CD/MM3CDSP |
| Metal 3-PLM,,,0.3,0.3,MM3CD/MM3CDSP |
| Metal 3-Cu, ,,0.3,0.3,MM3_CuCD/MM3_CuCDSP |
| Pad Via,,,1.2,1.27,VIPDMCD/VIPDMCDSP |
| Via3-PLM,,,0.2,0.2,VIM3CD/VIM3CDSP |
| Via3-Cu, ,,0.21,0.18,VIM3_CuCD/VIM3_CuCDSP |
| Inductor-TLM,,,2.5,2.5,INDMCD/INDMCDSP |
| Metal 4,,,0.3,0.3,MM4CD/MM4CDSP |
| Metal 4-Cu, ,,0.3,0.3,MM4_CuCD/MM4_CuCDSP |
| Via4,,,0.8,0.8,VIM4CD/VIM4CDSP |
| Metal 5,All flows except S8PF*/S8PIR*,,0.8,0.8,MM5CD/MM5CDSP |
| Metal 5,S8PF*/S8PIR*,,1.6,1.6,MM5CD/MM5CDSP |
| Nitride Seal Mask,,,3,4,NSMCD/NSMCDSP |
| Pad (scribe protect),,,2,1.27,PDMCD/PDMCDSP |
| Polyimide,,,5,15,PMMCD/PMMCDSP |
| Polyimide_ExtFab,,,5,15,PMM[E]CD/PMM[E]CDSP |
| DECA PBO, ,,10,10,PBOCD/PBOCDSP |
| Cu Inductor/Redist.,,,20,20,CU1MCD/CU1MCDSP |
| Serifs,,,0.1,0.1,SERCD/SERCDSP |
| ,,,,, |
| 3. Semiconductor Criteria,,,,, |
| Basic Parameters,,Units,Value,,Variable name |
| n-well peak concentration,,cm-3,6E+017,,NWPCONC |
| background concentration,,cm-3,800000000000000,,NWBCONC |
| y.char,,um,0.43,,NWYCHAR |
| desired Nmin/Ns ratio,,,0.9,,NMINNSRATIO |
| min n-well width to guarantee 90 % peak concentr.,,um,0.55,,MINNWWID |
| p-well peak concentration,,cm-3,4E+017,,PWPCONC |
| p-well peak coordinate,,um,0.42,,PWPCOORD |
| y.char,,um,0.13,,PWYCHAR |
| min. p-well width to guarantee 90 % peak concentr.,,um,0.33,,MINPWWID |
| Junction Depths,, ,Vertical,,Variable name |
| Baseline: N-Well,,um,1.1, ,NWVDIM |
| P-Well,,um,0.75, ,PWVDIM |
| N-w/P-w junction (from drawn edge),,um,*,0.034,WELLJCT |
| N+ or P+ S/D (XJ),,um,0.1,0.06,JCTD / LD |
| Max (N+ or P+ S/D outdiff.) next to isol. edge,,um, ,0.007,LDST |
| Max (N+ or P+ S/D outdiff.) next to isol. edge for 6 V reg. devices,,,,0.05,LDST5 |
| N Tip (As),,um, ,0.01,LDNTIP |
| Other Width Criteria,, ,Value (um),,Variable name |
| Min. diff/tap width for reproducible resistivity,,,0.12,,MINFWR |
| Min. width to open a strip of tap between two diffs,,,0.34,,SDM3 |
| "Max s/d diff width without contact, consistent w/Ram4,5,6",,,5.7,,XMAXCON |
| Minimum Spacing for 3.3 V Punchthrough (1.8V devices),,,Value (um),,Variable name |
| n-well - n-well ,,,0.835,,NWPTS |
| n+ - n+ or p+-p+,,,0.23,,DPTS |
| p+ in nwell to pwell,,,0.05,,PPTS |
| n+ in pwell to nwell,,,0.15,,PNPTS |
| Latch-up/ESD Criteria,,,Value (um),,Variable name |
| Minimum n+ or p+ - nwell spacing to prevent latch-up ,,,0.23,,NPNWLU |
| Min n-well enclos. of tap to ensure bkdwn N-w/P-w before N+/P-w (ESD),,,0.04,,XNWESD |
| Max. overlap of n-well by p+ tap,,,0.06,,XNWPTS |
| Implant angles,,,Angle (deg),,Variable name |
| High current,,,0,0,HCIMPA |
| Angle for tip implant ,,,7,,TipAng |
| Angle for HV tip implant ,,,40,,HvTipAngle |
| Twist angle for HV Tip ,,,23,,HvTipTwist |
| ,,,,, |
| 4. Physical Criteria,,,,, |
| Material Thicknesses,,,Value (um),,Variable name |
| field oxide (above silicon surface) ... underneath poly,,,0.07,,FOXSTEP |
| "min. etch and fill capability for isolation, licon, and met1",,,0.15,,DEFC |
| min. etch and fill capability for mcon,,,0.14,,CEFC |
| min. etch and fill capability for via,,,0.18,,VEFC |
| poly cap after SPE,,,0.2,,OVGTTH |
| poly thickness,,,0.18,,POLYTH |
| oxide spacer ,,,0.05,,SpThickn |
| Pre-LI ILD thickness,,,0.5,,ILDTHICKN |
| Licon1 etch angle (deg),,,10,,LICETANG |
| Standard Licon bottom CD,,,0.08,,LBCD |
| Mcon enclosure by Li,,,0,,mconLiEnclosure |
| Via1 slope,,,0.02,,Via1Slope |
| Oxide Bias for MM1,,,0.6,,BiasMM1 |
| Oxide Bias for MM2,,,0.6,,BiasMM2 |
| Oxide Bias for MM3,,,1.15,,BiasMM3 |
| Oxide Bias for MM4,,,1.15,,BiasMM4 |
| LI1 thickness for antenna ratio calculations,,,0.1,,LiThick |
| Metal 1 thickness for antenna ratio calculations (S8D*),,,0.35,,Met1Thick |
| Metal 2 thickness for antenna ratio calculations (S8D*),,,0.35,,Met2Thick |
| Inductor thickness for antenna ratio calculation (S8D*),,,4,,IndmThick |
| Metal 3 thickness for antenna ratio calculation (S8Q/SP8Q),,,0.8,,Met3thick_q |
| Metal4 thickness for antenna ratio calculation (S8Q*/SP8Q),,,2,,Met4Thick_q |
| Metal 3 thickness for antenna ratio calculation (S8P*/SP8P*),,,0.8,,Met3thick_p |
| Metal4 thickness for antenna ratio calculation (S8P*/SP8P*),,,0.8,,Met4Thick_p |
| Metal5 thickness for antenna ratio calculation (S8P*/SP8P* with 2um thick metal),,,2,,Met5Thick_p |
| Metal5 thickness for antenna ratio calculation (S8P*/SP8P* with 1.2um thick metal),,,1.2,,Met5Thickp_12 |
| Metal 2 thickness for antenna ratio calculations (SP8T/S8T*),,,0.35,,Met2_Qthick |
| Metal 3 thickness for antenna ratio calculations (S8T* other than S8TM*),,,0.85,,Met3_Qthick |
| Metal 3 thickness for antenna ratio calculations (S8TM* flow),,,2,,Met3_TMthick |
| Metal 3 thickness for antenna ratio calculations (SP8T flow),,,0.8,,Met3_SP8Tthick |
| Photoresist thickness,,,1.14,,PRTHICKN |
| Photoresist thickness for HV Tip Implants,,,0.3,,PrThickImplant |
| Min width of tip implant opening,,,0.1,,minTip_impW |
| NTM shadowing,,,0.16,,ntmShadowing |
| HVNTM shadowing,,,0.232,,hvntmShadowing |
| HVPTM shadowing,,,0.089,,hvptmShadowing |
| pseudo-shadowing,,,0.045,,pseudoShadowing |
| Channel length for low Vt PMOS,,,0.35,,lvtpmos_poly |
| Width of the Low Leakage gate on each side of LowVt Pmos connected to power rails (requirement based on exp data),,,0.28,,LvtEnc_forPowerRail |
| CD tolerance for PDM (3s),,,1,,PdmCD_tol |
| Min process bias 3s tolerance,,,0.032,,PHTOL |
| Min process bias 3s tolerance for poly,,,0.02,,PHP1TOL |
| Minimum Space and Overlap,,,Value (um),,Variable name |
| Minimum mcon overlap onto LI for reproducible contact resistance,,,0.12,,TCONOVLP |
| Dogbone PR decay length (SRS 8/4/99),,,0.2,,DBPRDEC |
| Bowing of rectangular contact (per edge) -- seal ring sizing,,,0.015,,TBOWINGSEAL |
| Waffling / Pattern Density,,,Value,,Variable name |
| S8 average FOM PD (extractions from logic device),,,0.45,,FOMPDAVG |
| Size of small PD extraction box for rough tolerance (um),,,700,,SMALLPDBOX |
| Size of large PD extraction box for rough tolerance (um),,,2000,,LARGEPDBOX |
| Min pattern density for oxide,,,0.75,,OxideMinPD |
| Min MM* PD range,,,0.3,,MMPDrange |
| FOM 700um box PD tolerance for CMP (SOI8 PCR2) for all technologies,,,0.15,,FOM700TOL |
| Stepping box shift as a percent of box size,,,0.5,,BOXSHIFT |
| Maximum metal waffle drop pattern density in the frame,,,0.55,,PD_FrameWP |
| Window size for frame waffle drop PD check,,,100,,WP_PDWINDOW |
| Step size for frame waffle drop PD check,,,10,,WP_PDSTEP |
| Other,,,Value,,Variable name |
| Poly resistor width and spacing to reduce CD variation (um),,,0.33,,POLYRCD |
| Poly resistor width and spacing to reduce CD variation (um),,,0.48,,POLYRSPC |
| Spacing between slotted_licons (Not applicable when the two edges L= 0.19um),,,0.51,,LICM1SLSP1 |
| Precision resistor width to accommodate 6 contacts across,,,2.03,,PRECRESW |
| Li resistor width (to drop one Licon w/o dogbones),,,0.29,,LIRESCD |
| Correction factor for spacing to a wide metal line,,,2,,BIGMF |
| Min spacing for created dnwell to pnp.dg (more restrictive than dnwell.4 rule),,,5,,cdnwPnpSpc |
| "Min spacing between nwell and deep nwell on separate nets (Taken from dnwell.3 from S4* TDR *N plus rounded up, IGK request.)",,,6,,nwellDnwellSpc |
| Min space between deep nwells used as photo diode (um),,,5,,PDDnwSpc |
| Min space between dnwell (used for photo diode and other deep nwell (um),,,5.3,,PDDnwSpc1 |
| Min/Max width of nwell inside deep nwell (for photo diodes),,,0.84,,PDNwmCD |
| Min/Max enclosure of nwell by deep nwell (for photo diode),,,1.08,,PDNwmDnwEnc |
| Min/Max width of tap inside deep nwell (for photo diode),,,0.41,,PDTapCD |
| Min/Max enclosure of tap by nwell inside deep nwell (for photo diode),,,0.215,,PDTapNwmEnc |
| ,,,,, |
| 5. Laser Fuse Criteria,,,,, |
| Min. spac. of laser spot to diffused junction to ensure jct integrity,,,0.6,,XLASJUN |
| Max. width of a metal fuse line that can be removed reliably,,,0.8,,FSW |
| Min. L of met. fuse at which damage doesn't extend beyond ends,,,6.605,,FSLE |
| Max. extension of met2 beyond fuse boundary,,,0.005,,FEXT |
| Min. distance between laser spot and active junction,,,0.545,,LASJCT |
| Standard contact bottom CD,,,0.09,, |
| Positioning tolerance of laser spot (3 s),,,0.3,,LASMA |
| Nominal effective laser spot diameter,,,3.5,,LASSPT |
| Max. increase in spot diameter at max. distance from focus (3 s),,,0.9,,LASCDTOL |
| Fuse melting radius,,,3.6,,MELTRAD |
| Melting related crack size in ILD,,,0.36,,FUSECRACK |
| Min space between fuse and any feature not connected to it,,,0.2,,MinFuseSpace |
| Space between fuse and any unrelated layer,,,0.5,,SP_fuse_to_unrelated |
| DC offset in some fuse rules,,,0.87,,LASDC1 |
| ,,,,, |
| Parameter,Name in SR spec,,Value (um) (final),, |
| FOM offset,D7+D10+D14,,9.18,,SRFOMOFFS |
| FOM width,D4,,3,,SRFOMWIDTH |
| Licon1 size for seal ring,D2,,0.23,,licon1srsize |
| FOM-licon1 enc,D3,,1.39,,SRFOMLICON1ENC |
| LI1-licon1 encl,D1,,2.42,,SRLILICON1ENC |
| LI1-licon1 encl far side,D16,,1.25,,SRLILICON1ENCFS |
| licon1/mcon/via spaces,D8,,1.17,,SRCTSPACES |
| li1-mconenc,D5,,1.17,,SRLI1MCONENC |
| met1 width,D11,,5.99,,SRMET1WIDTH |
| Via size for seal ring,D12,,0.28,,viasrsize |
| met2-via enc,D9,,5.71,,SRMET2VIAENC |
| met2-via far side enc,D13,,2,,SRMET2VIAF |
| met2-met1 offset,D14,,1,,M2M1OFF |
| Moat (passivation opening) width,D15,,2,,MOATW |
| Pad to Scribe (areaid:seal) min space,per spec 01-70001,,20,,PADSEALSP |
| Passivation enclosure,D7,,5,,SRPASSENC |
| 7. Other criteria and parameters,,,,, |
| Layer / Design rule,CD,,space,,Comment |
| MOSFET width,0.135,,,,FOMSE |
| MOSFET width in standard cells,0.075,,,,FOMSESC |
| Spacing of poly on field to diff,,,0.065,,PFDSE |
| Spacing of poly on field to tap,,,0.005,,PFTSE |
| Enclosure of tap by nwell for pwell res,,,0.22,,PTAP_NWL_SP |
| Grid conversion rounding factor,,,0.005,,GRCF |
| Licon enclosure rounding,,,0.02,,LICENCLR |
| LI1CD add/drop,0.01,,0.04,, |
| Huge metal X min. W and L,3,,,,HugeM |
| Min Nsdm area ,0.265,,,,MinNsdmArea |
| Min Psdm area,0.255,,,,MinPsdmArea |
| Min N/Psdm hole area ,0.265,,,,MinNPsdmHole |
| Large waffle size must be divisible by 4,7.2,,,,waffle_large |
| P1M additional CD control,0.011,,,,P1MCDcontrol |
| Li1 proximity correction,,,0.25,,LI1PROXSpace |
| "Serif added to nwell convex corner (SXX-572, 573)",0.22,,,,NwellCvxSerif |
| "Serif added to nwell concave corner (SXX-572, 573)",0.12,,,,NwellCveSerif |
| NWM extension beyond nwell edge straddling de_nFet_source (for GSMC; QZM-133),0.075,,,,NvhvNwellExt |
| Min enclosure of pad by pmm for Cu inductor (JNET-80) ,0,,,,padPMMEncInd |
| Min enclosure of pmm by cu1m for Cu inductor (JNET-80) ,10.75,,,,pmmCu1mEncInd |
| Min enclosure of pbo by cu1m per DECA 000348 Rev S,10,,,,pboCu1mEnc |
| Min enclosure of pmm by pmm2 for radio flow in the die (JNET-80) ,13,,,,pmmPmm2EncInd |
| Min enclosure of pmm by pmm2 inside frame,7.5,,,,pmmPmm2EncIndFrame |
| Min space between pmm2 and Inductor.dg ,,,7.5,,pmm2IndSpc |
| Min cu1m PD across full chip,0.35,,,,MinCU1Mpd |
| Max cu1m PD across full chip,0.45,,,,MaxCU1Mpd |
| Spacing between RDL and outer edge of seal ring,15,,,,RdlSealSpc |
| Spacing between RDL and pmm2,6.16,,,,RdlPmm2Spc |
| Enclosure of etest module in die by cpmm2,0,,,,EtestCpmm2Enc |
| "Keepout of active, poly, li and metal to NSM (TCS-2253)",,,1,,NSMKeepout |
| "3 um keepout of active, poly, li and metal to areaid.dt/areaid.ft (TCS-2253)",,,3,,NSMKeepout_3um |
| pnp_emitter sizing (S8P GSMC flow),,,0.05,,PnpEmitterSzGSMC |
| pnp_emitter sizing (other flows),,,0.03,,PnpEmitterSz |
| MiM Capacitor aspect ration,20,,,,MiM_AR |
| Min NCM space to be used to preserve NCM CL algorithm (avoid LVL error),,,1.27,,NCM_0LVL |
| Min space of NCM between core and periphery due to existing layout restriction,,,0.96,,NcmCorePeriSP |
| Multiplication factor,,,0.01,,S8LVconv |
| Minimum scribe width,50,,,,scribew |
| spacing of p-well outside deep n-well to deep n-well mask edge,,,0.12,,NWDNWENCL |
| p-well in deep n-well to p-sub,,,1.2,,NWDNWOL |
| Field oxide etchback after P1ME before implants,,,0.04,,WFDEL |
| ,,,,, |
| 8. Criteria for High Voltage FET,,,,, |
| Layer / Design rule,CD,,space,,Comment |
| Min HVNwell to any nwell space,,,2,,HVNwell_Nwell_SP |
| Min HVDiff width,0.29,,,,HVDiff_CD |
| Min HVDiff space,,,0.3,,HVDiff_SP |
| Min HV Pmos gate width,0.5,,,,HVP_gate_CD |
| Min space between HV poly,,,0.28,,HVPoly_SP |
| Min HV Nmos gate width,0.37,,,,HVPoly_CD |
| HV P+ Diff enclosure by Nwell,0.33,,,,HVPdiff_nwell_enc |
| HV N+ diff space to Nwell,,,0.43,,HVNdiff_nwell_SP |
| HV N+ tap enclosure by Nwell,0.33,,,,HVNtap_nwell_enc |
| HV P+tap space to Nwell,,,0.43,,HVPtap_nwell_SP |
| Photoresist tilted implant penetration,0.02,,,,HVPrPenetration |
| Photoresist tilted implant blocking distance,0.013,,,,HVPrBlocking |
| Min size of HVTip,0.1,,,,HVTipMinSize |
| Extra CD tol for HVNTM to match Ram7 process,0.015,,,,HVNTMExtraCdTol |
| Min HVDiff resistor width,0.29,,,,HVDiff_Res_CD |
| High voltage n+-n+ or p+-p+,,,0.3,,HVDPTS15 |
| HV MOSFET channel length,0.5,,,,HVPCD |
| ,,,,, |
| 9. Criteria for polyimide manufacturability,,,,, |
| Layer / Design rule,CD,,space,,Comment |
| Enclosure of fuses by polyimide,12,,,,PimFuseEnc |
| Enclosure of bondpad by polyimide (YUY-165),0.5,,,,PimPadEnc |
| "Enclosure of pad:dg by PBO inside inductor capture pad, with DECA online monitoring",4.5,,,,PBOPadEnc |
| Enclosure of pad:dg by PBO per standard DECA rules,7.5,,,,PBOPadEncDECA |
| DECA PBO drawn-to-final process bias per side,0.5,,,,PBOProcBiasPerSide |
| Polyimide CD tolerance,1,,,,PimCD_tol |
| Min Pim width over pad openings,87,,,,PimOverPad_CD |
| Polyimide slope (001-87400),,5.3,,,I_polyimide_slope |
| Enclosure of polyimide by polymer tolerance,,7.7,,,Po_po_tol |
| Min/Max enclosure of pad.dg inside M5RDL by pmm,0,,,,pmmM5RDLpadEnc |
| Min spacing of pmm to (rdl NOT (pad.dg sized by 0.5)),,,19.16,,pmmRDLspc |
| Enclosure of laser targets in the die by polyimide,30,,,,PimLaserEnc |
| ,,,,, |
| 10. Criteria for VPP capacitor,,,,, |
| Layer / Design rule,CD,,space,,Comment |
| Min width of capacitor:dg,4.38,,,,VppWidth |
| Max width of unit capacitor:dg,8.58,,,,VppMaxWidth |
| Min spacing between two capacitor:dg ,1.5,,,,VppSpc |
| Min spacing of capacitor:dg to li1 or met1 or met2 or nwell,1.5,,,,VppOtherSPc |
| Min enclosure of capacitor by nwell,1.5,,,,VppNwmEnc |
| Min spacing of pmm to (rdl NOT (pad.dg sized by 0.5)),,,19.16,,pmmRDLspc |
