blob: 844e8758cf50a524ccccf46f780f2f7568f716a6 [file] [log] [blame] [edit]
import argparse
from pathlib import Path
if __name__ == '__main__':
parser = argparse.ArgumentParser()
parser.add_argument(
"input_dir",
help="The path to the directory containing diagrams and schematics",
type=Path)
args = parser.parse_args()
# fix output/skywater-pdk/libraries/openfpga/Skywater_130/SRC/routing/routing.v.full
routingsimplepath = args.input_dir / 'output/skywater-pdk/libraries/openfpga/Skywater_130/SRC/routing/routing.v.full'
tmpfile = Path('./routing.full.v.tmp')
with open(routingsimplepath, 'r') as routingsimple:
with open(tmpfile, 'w') as finfile:
for line in routingsimple:
newline = line.replace('.v', '.simple.v')
finfile.write(newline)
tmpfile.rename(routingsimplepath)