blob: 8e514d77cd7c33248e91225f9a355fd27ff0eb0d [file] [log] [blame]
import argparse
from pathlib import Path
if __name__ == '__main__':
parser = argparse.ArgumentParser()
parser.add_argument(
"input_dir",
help="The path to the directory containing diagrams and schematics",
type=Path)
args = parser.parse_args()
# fix output/skywater-pdk/libraries/openfpga/Skywater_130/SRC/routing/routing.simple.v
routingsimplepath = args.input_dir / 'output/skywater-pdk/libraries/openfpga/Skywater_130/SRC/routing/routing.simple.v'
tmpfile = Path('./routing.simple.v.tmp')
with open(routingsimplepath, 'r') as routingsimple:
with open(tmpfile, 'w') as finfile:
for line in routingsimple:
newline = line.replace('.v', '.simple.v')
finfile.write(newline)
tmpfile.rename(routingsimplepath)