run/run-verilog.inc.sh

# Convert the verilog files
msg "Splitting Verilog files."
$SCRIPT_DIR/verilog_split.py $INPUT_DIRECTORY $OUTPUT_DIRECTORY $TEMP_DIR ; RETCODE=$?
if [ "$RETCODE" -ne 0 ]; then
	msg "Error: Failed to split Verilog files!?"
	exit 1
else
	msg "Successfully split Verilog files."
fi

# Generate the blackbox verilog files
msg "Generating blackbox Verilog model files."
$SCRIPT_DIR/generate_verilog_blackbox.py $OUTPUT_DIRECTORY/skywater-pdk/libraries/*/*/models/* ; RETCODE=$?
if [ "$RETCODE" -ne 0 ]; then
	msg "Error: Failed to generate blackbox Verilog model files!?"
	exit 1
else
	msg "Successfully generated blackbox Verilog model files."
fi
msg "Generating blackbox Verilog cell files."
$SCRIPT_DIR/generate_verilog_blackbox.py $OUTPUT_DIRECTORY/skywater-pdk/libraries/*/*/cells/* ; RETCODE=$?
if [ "$RETCODE" -ne 0 ]; then
	msg "Error: Failed to generate blackbox Verilog cell files!?"
	exit 1
else
	msg "Successfully generated blackbox Verilog cell files."
fi

# Generate the .svg symbol images
$SCRIPT_DIR/symbols.sh $OUTPUT_DIRECTORY || exit 1

# Generate the .svg schematic images
$SCRIPT_DIR/schematics.sh $OUTPUT_DIRECTORY || exit 1