add SOFA GDS, lef, spef and post-pnr verilog files
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..39f529a
--- /dev/null
+++ b/README.md
@@ -0,0 +1,26 @@
+# OpenFPGA ready-to-use Macros
+
+This repository provide the following GDS-ready eFPGA IPs using OpenFPGA prototyping tool.
+
+
+## Available FPGA Macros
+
+- `SOFA_CHD`: Skywater Opensource FPGA (SOFA) - Custom High-Density Design
+    - Open-source 12x12 FPGA with adapted QuickLogic' soft-adder CLB architecture ([documentation](https://skywater-openfpga.readthedocs.io/en/latest/datasheet/sofa_chd/), [github](https://github.com/lnis-uofu/SOFA))
+    - Designed with Skywater130nm PDK with HD standard cell library + Custom Transmission Gate Cells
+    - Base K4 architecture from VPR with 60 vertical and horizontal channels
+    - Fabricated with eFabless Open MPW shuttle program ([slot-039](https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-one/slot-039))
+
+- `SOFA_HD`: Skywater Opensource FPGA (SOFA) - High-Density Design
+    - Open-source 12x12 FPGA ([documentation](https://skywater-openfpga.readthedocs.io/en/latest/datasheet/sofa_hd/), [github](https://github.com/lnis-uofu/SOFA))
+    - Designed with Skywater130nm PDK with HD standard cell library
+    - Base K4 architecture from VPR with 40 vertical and horizontal channels
+    - No adders (carry-chain) or flipflop reset pins
+    - Fabricated with eFabless Open MPW shuttle program ([slot-017](https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-one/slot-017))
+
+- `SOFA_QLHD`: Skywater Opensource FPGA (SOFA) - QuickLogic' soft-adder High-Density Design
+    - Opensource 12x12 FPGA with adapted QuickLogic' soft-adder CLB architecture ([documentation](https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/), [github](https://github.com/lnis-uofu/SOFA))
+    - Designed with Skywater130nm PDK with HD standard cell library
+    - Base K4 architecture from VPR with 60 vertical and horizontal channels
+    - Fabricated with eFabless Open MPW shuttle program ([slot-036](https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-one/slot-036))
+
diff --git a/SOFA_CHD/README.md b/SOFA_CHD/README.md
new file mode 100644
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--- /dev/null
+++ b/SOFA_CHD/README.md
@@ -0,0 +1,3 @@
+## FPGA1212_SOFA_CHD_PNR
+
+https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.gds.gz b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.gds.gz
new file mode 100644
index 0000000..645fa25
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.gds.gz
Binary files differ
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.lef b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.lef
new file mode 100644
index 0000000..bc1a90d
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.lef
@@ -0,0 +1,352 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.34 ;
+  WIDTH 0.14 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.46 ;
+  WIDTH 0.14 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.68 ;
+  WIDTH 0.3 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.92 ;
+  WIDTH 0.3 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.4 ;
+  WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+  TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+  TYPE MASTERSLICE ;
+END pwell
+
+VIA L1M1_PR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+  LAYER li1 ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER mcon ;
+    RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+    RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+  LAYER met1 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+  LAYER met1 ;
+    RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+  LAYER met1 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER via ;
+    RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met2 ;
+    RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+  LAYER met2 ;
+    RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+  LAYER met2 ;
+    RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+  LAYER met2 ;
+    RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER via2 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+  LAYER met3 ;
+    RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+  LAYER met3 ;
+    RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+  LAYER met3 ;
+    RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER via3 ;
+    RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met4 ;
+    RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+  LAYER met4 ;
+    RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER via4 ;
+    RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met5 ;
+    RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+  CLASS CORE ;
+  SYMMETRY Y ;
+  SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+  CLASS CORE ;
+  SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+END LIBRARY
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz
new file mode 100644
index 0000000..3e4a4c4
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz
Binary files differ
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.pt.v b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.pt.v
new file mode 100644
index 0000000..db99259
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.pt.v
@@ -0,0 +1,147071 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , 
+    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_117 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_118 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_117 ) , 
+    .X ( copt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( copt_net_115 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_118 ) ) ;
+endmodule
+
+
+module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_513_ ) , 
+    .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
+    .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_32 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ;
+cby_2__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_57 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( aps_rename_512_ ) , 
+    .Y ( BUF_net_100 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_31 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) ) ;
+cby_2__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_54 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , 
+    .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) ) ;
+cby_2__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_51 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , 
+    .Y ( BUF_net_96 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_48 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_45 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ;
+cby_2__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_42 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_509_ ) , 
+    .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_92 ) ) ;
+cby_2__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_39 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( net_net_92 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_36 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_108 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_108 ) , 
+    .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_111 ) , 
+    .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( copt_net_109 ) , 
+    .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_110 ) , 
+    .X ( copt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_112 ) , 
+    .X ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( copt_net_113 ) , 
+    .X ( ropt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_121 ) , 
+    .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1376 ( .A ( ropt_net_122 ) , 
+    .X ( ropt_net_123 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ;
+cby_2__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_508_ ) , 
+    .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ;
+cby_2__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_507_ ) , 
+    .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) ) ;
+cby_2__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+cby_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) ) ;
+cby_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cby_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , 
+    left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , 
+    left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , 
+    left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , 
+    left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , 
+    left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , 
+    left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , 
+    prog_clk_0_S_out , prog_clk_0_N_out ) ;
+input  [0:0] pReset ;
+input  [0:29] chany_bottom_in ;
+input  [0:29] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input  pReset_S_in ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size10_0_sram ;
+wire [0:3] mux_2level_size10_1_sram ;
+wire [0:3] mux_2level_size10_2_sram ;
+wire [0:3] mux_2level_size10_3_sram ;
+wire [0:3] mux_2level_size10_4_sram ;
+wire [0:3] mux_2level_size10_5_sram ;
+wire [0:3] mux_2level_size10_6_sram ;
+wire [0:3] mux_2level_size10_7_sram ;
+wire [0:0] mux_2level_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_6_ccff_tail ;
+wire [0:3] mux_2level_size12_0_sram ;
+wire [0:3] mux_2level_size12_1_sram ;
+wire [0:3] mux_2level_size12_2_sram ;
+wire [0:3] mux_2level_size12_3_sram ;
+wire [0:3] mux_2level_size12_4_sram ;
+wire [0:3] mux_2level_size12_5_sram ;
+wire [0:3] mux_2level_size12_6_sram ;
+wire [0:3] mux_2level_size12_7_sram ;
+wire [0:3] mux_2level_size12_8_sram ;
+wire [0:0] mux_2level_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_8_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_2level_size12_0 mux_left_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+    .sram ( mux_2level_size12_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_103 ) ) ;
+cby_2__1__mux_2level_size12_1 mux_right_ipin_0 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+    .sram ( mux_2level_size12_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( { aps_rename_514_ } ) ,
+    .p0 ( optlc_net_103 ) ) ;
+cby_2__1__mux_2level_size12_2 mux_right_ipin_2 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , 
+        chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+    .sram ( mux_2level_size12_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_2__1__mux_2level_size12_3 mux_right_ipin_4 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , 
+        chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) ,
+    .sram ( mux_2level_size12_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_101 ) ) ;
+cby_2__1__mux_2level_size12_4 mux_right_ipin_6 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+    .sram ( mux_2level_size12_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( { aps_rename_516_ } ) ,
+    .p0 ( optlc_net_105 ) ) ;
+cby_2__1__mux_2level_size12_5 mux_right_ipin_8 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , 
+        chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+    .sram ( mux_2level_size12_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size12_6 mux_right_ipin_10 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , 
+        chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) ,
+    .sram ( mux_2level_size12_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_101 ) ) ;
+cby_2__1__mux_2level_size12_7 mux_right_ipin_12 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+    .sram ( mux_2level_size12_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( { aps_rename_517_ } ) ,
+    .p0 ( optlc_net_103 ) ) ;
+cby_2__1__mux_2level_size12 mux_right_ipin_14 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , 
+        chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+    .sram ( mux_2level_size12_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_0_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_1_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_2_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_3_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_4_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_5_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_6 mem_right_ipin_10 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_6_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_7 mem_right_ipin_12 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_7_sram ) ) ;
+cby_2__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_8_sram ) ) ;
+cby_2__1__mux_2level_size10_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , 
+        chany_bottom_out[26] } ) ,
+    .sram ( mux_2level_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( { aps_rename_515_ } ) ,
+    .p0 ( optlc_net_102 ) ) ;
+cby_2__1__mux_2level_size10_1 mux_right_ipin_3 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , 
+        chany_bottom_out[28] } ) ,
+    .sram ( mux_2level_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size10_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , 
+        chany_bottom_out[21] } ) ,
+    .sram ( mux_2level_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_2__1__mux_2level_size10_3 mux_right_ipin_7 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , 
+        chany_bottom_out[23] } ) ,
+    .sram ( mux_2level_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( { ZBUF_6_f_0 } ) ,
+    .p0 ( optlc_net_105 ) ) ;
+cby_2__1__mux_2level_size10_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , 
+        chany_bottom_out[25] } ) ,
+    .sram ( mux_2level_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( { ZBUF_6_f_1 } ) ,
+    .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size10_5 mux_right_ipin_11 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , 
+        chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , 
+        chany_bottom_out[27] } ) ,
+    .sram ( mux_2level_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_2__1__mux_2level_size10_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , 
+        chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , 
+        chany_bottom_out[29] } ) ,
+    .sram ( mux_2level_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ;
+cby_2__1__mux_2level_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , 
+        chany_bottom_out[22] } ) ,
+    .sram ( mux_2level_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_0_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_1_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_2_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_3_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_4_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_5 mem_right_ipin_11 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_5_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_6 mem_right_ipin_13 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_6_sram ) ) ;
+cby_2__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_8_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_2level_size10_7_sram ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( left_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_1106 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_2107 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , 
+    .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , 
+    .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , 
+    .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , 
+    .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , 
+    .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , 
+    .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , 
+    .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , 
+    .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , 
+    .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , 
+    .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , 
+    .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , 
+    .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , 
+    .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , 
+    .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , 
+    .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , 
+    .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , 
+    .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , 
+    .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , 
+    .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , 
+    .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 ( 
+    .A ( left_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , 
+    .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_112 ( .A ( aps_rename_517_ ) , 
+    .X ( left_grid_pin_28_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_113 ( .A ( aps_rename_514_ ) , 
+    .X ( left_grid_pin_16_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_114 ( .A ( aps_rename_516_ ) , 
+    .X ( left_grid_pin_22_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_115 ( .A ( aps_rename_515_ ) , 
+    .X ( left_grid_pin_17_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1359 ( .A ( ZBUF_6_f_0 ) , 
+    .X ( left_grid_pin_23_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3711261 ( .A ( ctsbuf_net_1106 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3761266 ( .A ( ctsbuf_net_2107 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1360 ( .A ( ZBUF_6_f_1 ) , 
+    .X ( left_grid_pin_25_[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) , 
+    .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_53 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_54 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_50 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_51 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_52 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_83 ) ) ;
+cby_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_47 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_48 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_49 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( net_net_83 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_44 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_45 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_46 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_41 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_42 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_43 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_38 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_39 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_40 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_35 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_36 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_37 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_82 ) ) ;
+cby_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_34 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_124 ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1360 ( .A ( copt_net_105 ) , 
+    .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_106 ) , 
+    .X ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_107 ) , 
+    .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_109 ) , 
+    .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1375 ( .A ( copt_net_110 ) , 
+    .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1386 ( .A ( ropt_net_123 ) , 
+    .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1387 ( .A ( copt_net_111 ) , 
+    .X ( ropt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1388 ( .A ( ropt_net_122 ) , 
+    .X ( ropt_net_124 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_81 ) ) ;
+cby_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( net_net_81 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_80 ) ) ;
+cby_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+cby_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_79 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cby_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_77 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , 
+    left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , 
+    left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , 
+    left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , 
+    left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , 
+    left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , 
+    Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , 
+    Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in , 
+    Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in , 
+    prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in , 
+    prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , 
+    prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , 
+    clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , 
+    clk_3_S_out ) ;
+input  [0:0] pReset ;
+input  [0:29] chany_bottom_in ;
+input  [0:29] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+input  Test_en_E_in ;
+input  Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input  pReset_S_in ;
+output pReset_N_out ;
+input  Reset_S_in ;
+input  Reset_E_in ;
+input  Reset_W_in ;
+output Reset_N_out ;
+output Reset_W_out ;
+output Reset_E_out ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_2_N_in ;
+input  clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size10_0_sram ;
+wire [0:3] mux_2level_size10_1_sram ;
+wire [0:3] mux_2level_size10_2_sram ;
+wire [0:3] mux_2level_size10_3_sram ;
+wire [0:3] mux_2level_size10_4_sram ;
+wire [0:3] mux_2level_size10_5_sram ;
+wire [0:3] mux_2level_size10_6_sram ;
+wire [0:3] mux_2level_size10_7_sram ;
+wire [0:0] mux_2level_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_6_ccff_tail ;
+wire [0:3] mux_2level_size12_0_sram ;
+wire [0:3] mux_2level_size12_1_sram ;
+wire [0:3] mux_2level_size12_2_sram ;
+wire [0:3] mux_2level_size12_3_sram ;
+wire [0:3] mux_2level_size12_4_sram ;
+wire [0:3] mux_2level_size12_5_sram ;
+wire [0:3] mux_2level_size12_6_sram ;
+wire [0:3] mux_2level_size12_7_sram ;
+wire [0:0] mux_2level_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+
+assign Test_en_E_in = Test_en_S_in ;
+assign Test_en_E_in = Test_en_W_in ;
+assign Reset_E_in = Reset_S_in ;
+assign Reset_E_in = Reset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
+
+cby_1__1__mux_2level_size12_0 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+    .sram ( mux_2level_size12_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_101 ) ) ;
+cby_1__1__mux_2level_size12_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , 
+        chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+    .sram ( mux_2level_size12_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_98 ) ) ;
+cby_1__1__mux_2level_size12_2 mux_right_ipin_4 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , 
+        chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) ,
+    .sram ( mux_2level_size12_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_96 ) ) ;
+cby_1__1__mux_2level_size12_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+    .sram ( mux_2level_size12_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_98 ) ) ;
+cby_1__1__mux_2level_size12_4 mux_right_ipin_8 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , 
+        chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+    .sram ( mux_2level_size12_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_99 ) ) ;
+cby_1__1__mux_2level_size12_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , 
+        chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) ,
+    .sram ( mux_2level_size12_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_96 ) ) ;
+cby_1__1__mux_2level_size12_6 mux_right_ipin_12 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+    .sram ( mux_2level_size12_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ;
+cby_1__1__mux_2level_size12 mux_right_ipin_14 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , 
+        chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+    .sram ( mux_2level_size12_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_98 ) ) ;
+cby_1__1__mux_2level_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_0_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_1_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_2_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_3_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_4_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_5 mem_right_ipin_10 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_5_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_6 mem_right_ipin_12 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_6_sram ) ) ;
+cby_1__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_7_sram ) ) ;
+cby_1__1__mux_2level_size10_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , 
+        chany_bottom_out[25] } ) ,
+    .sram ( mux_2level_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_96 ) ) ;
+cby_1__1__mux_2level_size10_1 mux_right_ipin_3 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , 
+        chany_bottom_out[27] } ) ,
+    .sram ( mux_2level_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_1__1__mux_2level_size10_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , 
+        chany_bottom_out[29] } ) ,
+    .sram ( mux_2level_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_100 ) ) ;
+cby_1__1__mux_2level_size10_3 mux_right_ipin_7 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] , 
+        chany_bottom_out[22] } ) ,
+    .sram ( mux_2level_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_96 ) ) ;
+cby_1__1__mux_2level_size10_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] , 
+        chany_bottom_out[24] } ) ,
+    .sram ( mux_2level_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_1__1__mux_2level_size10_5 mux_right_ipin_11 (
+    .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
+        chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , 
+        chany_bottom_out[26] } ) ,
+    .sram ( mux_2level_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_97 ) ) ;
+cby_1__1__mux_2level_size10_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
+        chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , 
+        chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , 
+        chany_bottom_out[28] } ) ,
+    .sram ( mux_2level_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_97 ) ) ;
+cby_1__1__mux_2level_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , 
+        chany_bottom_out[21] } ) ,
+    .sram ( mux_2level_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ;
+cby_1__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_0_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_1_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_2_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_3_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_4_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_5 mem_right_ipin_11 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_5_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_6 mem_right_ipin_13 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_6_sram ) ) ;
+cby_1__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) ,
+    .ccff_tail ( { copt_net_119 } ) ,
+    .mem_out ( mux_2level_size10_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , 
+    .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_E_in ) , 
+    .X ( Reset_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_E_in ) , 
+    .X ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_1103 ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_2104 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( aps_rename_512_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( aps_rename_513_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( prog_clk_3_S_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , 
+    .X ( aps_rename_514_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , 
+    .X ( aps_rename_515_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( aps_rename_516_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( clk_3_S_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , 
+    .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , 
+    .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , 
+    .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , 
+    .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , 
+    .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , 
+    .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , 
+    .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , 
+    .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , 
+    .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , 
+    .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , 
+    .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , 
+    .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , 
+    .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , 
+    .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , 
+    .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , 
+    .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , 
+    .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , 
+    .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , 
+    .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , 
+    .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_507_ ) , 
+    .Y ( BUF_net_85 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_508_ ) , 
+    .Y ( BUF_net_87 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( pReset_S_in ) , .Y ( BUF_net_89 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( Reset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_509_ ) , 
+    .Y ( BUF_net_91 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_E_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_510_ ) , 
+    .Y ( BUF_net_93 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , 
+    .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_513_ ) , 
+    .Y ( BUF_net_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , 
+    .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_111 ( .A ( aps_rename_516_ ) , 
+    .X ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_112 ( .A ( aps_rename_511_ ) , 
+    .X ( prog_clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_113 ( .A ( aps_rename_514_ ) , 
+    .X ( clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_512_ ) , 
+    .X ( prog_clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_515_ ) , 
+    .X ( clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3711261 ( .A ( ctsbuf_net_1103 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3761266 ( .A ( ctsbuf_net_2104 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_119 ) , 
+    .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1383 ( .A ( copt_net_120 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_116 ) , 
+    .X ( copt_net_120 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , 
+    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_80 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_79 ) , 
+    .X ( copt_net_75 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_78 ) , 
+    .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_76 ) , 
+    .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_75 ) , 
+    .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_77 ) , 
+    .X ( copt_net_80 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_63 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
+    .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_73 ) , 
+    .X ( copt_net_69 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( copt_net_72 ) , 
+    .X ( copt_net_70 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_69 ) , 
+    .X ( copt_net_71 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( copt_net_74 ) , 
+    .X ( copt_net_72 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_70 ) , 
+    .X ( copt_net_73 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_74 ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_0__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_0__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cby_0__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_0__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_0__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_0__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_0__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_0__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ;
+input  [0:0] pReset ;
+input  [0:29] chany_bottom_in ;
+input  [0:29] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  pReset_N_in ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_139 ;
+wire ropt_net_131 ;
+wire ropt_net_140 ;
+wire ropt_net_142 ;
+wire ropt_net_127 ;
+wire ropt_net_152 ;
+wire ropt_net_133 ;
+wire ropt_net_141 ;
+wire ropt_net_143 ;
+wire ropt_net_135 ;
+wire ropt_net_154 ;
+wire ropt_net_156 ;
+wire ropt_net_153 ;
+wire ropt_net_130 ;
+wire ropt_net_132 ;
+wire ropt_net_147 ;
+wire ropt_net_138 ;
+wire ropt_net_151 ;
+wire ropt_net_128 ;
+wire ropt_net_149 ;
+wire ropt_net_150 ;
+wire ropt_net_129 ;
+wire ropt_net_146 ;
+wire ropt_net_136 ;
+wire ropt_net_148 ;
+wire ropt_net_134 ;
+wire ropt_net_137 ;
+wire ropt_net_144 ;
+wire ropt_net_145 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size12_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_2level_size12 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+    .sram ( mux_2level_size12_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_68 ) ) ;
+cby_0__1__mux_2level_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_2level_size12_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( ropt_net_139 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( ropt_net_131 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( ropt_net_140 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( ropt_net_142 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( ropt_net_127 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( ropt_net_152 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( ropt_net_133 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( ropt_net_141 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( ropt_net_143 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( ropt_net_135 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( ropt_net_154 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , 
+    .X ( ropt_net_156 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , 
+    .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , 
+    .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , 
+    .X ( ropt_net_153 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , 
+    .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , 
+    .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) , 
+    .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , 
+    .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_bottom_in[28] ) , 
+    .X ( ropt_net_130 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , 
+    .X ( ropt_net_132 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , 
+    .X ( ropt_net_147 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[5] ) , 
+    .X ( ropt_net_138 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , 
+    .X ( ropt_net_151 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[9] ) , 
+    .X ( ropt_net_128 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , 
+    .X ( ropt_net_149 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , 
+    .X ( ropt_net_150 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , 
+    .X ( ropt_net_129 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , 
+    .X ( ropt_net_146 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chany_top_in[15] ) , 
+    .X ( ropt_net_136 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , 
+    .X ( ropt_net_148 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , 
+    .X ( ropt_net_134 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , 
+    .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[22] ) , 
+    .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chany_top_in[23] ) , 
+    .X ( ropt_net_137 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , 
+    .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , 
+    .X ( ropt_net_144 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , 
+    .X ( ropt_net_145 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , 
+    .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[28] ) , 
+    .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , 
+    .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_68 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_127 ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_128 ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_129 ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1286 ( .A ( ropt_net_130 ) , 
+    .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_131 ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_132 ) , 
+    .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_133 ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_134 ) , 
+    .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1291 ( .A ( ropt_net_135 ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1292 ( .A ( ropt_net_136 ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_137 ) , 
+    .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_138 ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_139 ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_140 ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_141 ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_142 ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_143 ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_144 ) , 
+    .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_145 ) , 
+    .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1302 ( .A ( ropt_net_146 ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_147 ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_148 ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_149 ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1306 ( .A ( ropt_net_150 ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_151 ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1308 ( .A ( ropt_net_152 ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1309 ( .A ( ropt_net_153 ) , 
+    .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1310 ( .A ( ropt_net_154 ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1312 ( .A ( ropt_net_156 ) , 
+    .X ( chany_top_out[20] ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , 
+    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_113 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_113 ) , 
+    .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_112 ) , 
+    .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_110 ) , 
+    .X ( copt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_111 ) , 
+    .X ( mem_out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , 
+    .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , 
+    prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
+    .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_32 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ;
+cbx_1__2__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_57 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_508_ ) , 
+    .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_31 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_93 ) ) ;
+cbx_1__2__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_54 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( net_net_93 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_51 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_507_ ) ) ;
+cbx_1__2__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_48 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , 
+    .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_45 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_90 ) ) ;
+cbx_1__2__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_42 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_39 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_89 ) ) ;
+cbx_1__2__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_36 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_121 ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_107 ) , 
+    .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_105 ) , 
+    .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( ropt_net_123 ) , 
+    .X ( copt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_106 ) , 
+    .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( copt_net_116 ) , 
+    .X ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1369 ( .A ( ropt_net_122 ) , 
+    .X ( ropt_net_121 ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_h_inst_1370 ( .A ( copt_net_115 ) , 
+    .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_117 ) , 
+    .X ( ropt_net_123 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_17 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_88 ) ) ;
+cbx_1__2__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+cbx_1__2__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) ) ;
+cbx_1__2__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:11] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cbx_1__2__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , 
+    bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , 
+    SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , 
+    pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+input  [0:0] pReset ;
+input  [0:29] chanx_left_in ;
+input  [0:29] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:29] chanx_left_out ;
+output [0:29] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  pReset_E_in ;
+input  pReset_W_in ;
+output pReset_W_out ;
+output pReset_S_out ;
+output pReset_E_out ;
+input  prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size10_0_sram ;
+wire [0:3] mux_2level_size10_1_sram ;
+wire [0:3] mux_2level_size10_2_sram ;
+wire [0:3] mux_2level_size10_3_sram ;
+wire [0:3] mux_2level_size10_4_sram ;
+wire [0:3] mux_2level_size10_5_sram ;
+wire [0:3] mux_2level_size10_6_sram ;
+wire [0:3] mux_2level_size10_7_sram ;
+wire [0:0] mux_2level_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_6_ccff_tail ;
+wire [0:3] mux_2level_size12_0_sram ;
+wire [0:3] mux_2level_size12_1_sram ;
+wire [0:3] mux_2level_size12_2_sram ;
+wire [0:3] mux_2level_size12_3_sram ;
+wire [0:3] mux_2level_size12_4_sram ;
+wire [0:3] mux_2level_size12_5_sram ;
+wire [0:3] mux_2level_size12_6_sram ;
+wire [0:3] mux_2level_size12_7_sram ;
+wire [0:3] mux_2level_size12_8_sram ;
+wire [0:0] mux_2level_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_8_ccff_tail ;
+
+assign pReset_W_in = pReset_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_2level_size12_0 mux_bottom_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+    .sram ( mux_2level_size12_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
+        chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+    .sram ( mux_2level_size12_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ;
+cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , 
+        chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+    .sram ( mux_2level_size12_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 (
+    .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
+        chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , 
+        chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
+    .sram ( mux_2level_size12_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_98 ) ) ;
+cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
+        chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+    .sram ( mux_2level_size12_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( { aps_rename_510_ } ) ,
+    .p0 ( optlc_net_98 ) ) ;
+cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , 
+        chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+    .sram ( mux_2level_size12_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_99 ) ) ;
+cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 (
+    .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
+        chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , 
+        chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
+    .sram ( mux_2level_size12_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( { ropt_net_119 } ) ,
+    .p0 ( optlc_net_99 ) ) ;
+cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
+        chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+    .sram ( mux_2level_size12_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_2level_size12 mux_top_ipin_14 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , 
+        chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+    .sram ( mux_2level_size12_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( { aps_rename_513_ } ) ,
+    .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_2level_size12_mem_0 mem_bottom_ipin_0 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_0_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_1_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_2_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_3_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_4_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_5_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_6_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_7_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) , 
+    .mem_out ( mux_2level_size12_8_sram ) ) ;
+cbx_1__2__mux_2level_size10_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
+        chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , 
+        chanx_left_out[26] } ) ,
+    .sram ( mux_2level_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_100 ) ) ;
+cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
+        chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , 
+        chanx_left_out[28] } ) ,
+    .sram ( mux_2level_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_100 ) ) ;
+cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] , 
+        chanx_left_out[21] } ) ,
+    .sram ( mux_2level_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_102 ) ) ;
+cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 (
+    .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
+        chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] , 
+        chanx_left_out[23] } ) ,
+    .sram ( mux_2level_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( { aps_rename_511_ } ) ,
+    .p0 ( optlc_net_99 ) ) ;
+cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
+        chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , 
+        chanx_left_out[25] } ) ,
+    .sram ( mux_2level_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_98 ) ) ;
+cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , 
+        chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , 
+        chanx_left_out[27] } ) ,
+    .sram ( mux_2level_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( { aps_rename_512_ } ) ,
+    .p0 ( optlc_net_99 ) ) ;
+cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
+        chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , 
+        chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , 
+        chanx_left_out[29] } ) ,
+    .sram ( mux_2level_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_102 ) ) ;
+cbx_1__2__mux_2level_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
+        chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , 
+        chanx_left_out[22] } ) ,
+    .sram ( mux_2level_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_100 ) ) ;
+cbx_1__2__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_0_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_1_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_2_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_3_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_4_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_5_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_2level_size10_6_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_2level_size12_mem_8_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_2level_size10_7_sram ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_W_in ) , 
+    .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_S_FTB01 ( .A ( pReset_W_in ) , 
+    .X ( aps_rename_514_ ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , 
+    .X ( aps_rename_515_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , 
+    .X ( ctsbuf_net_1104 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , 
+    .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , 
+    .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , 
+    .X ( chanx_right_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , 
+    .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , 
+    .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , 
+    .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , 
+    .X ( chanx_right_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , 
+    .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , 
+    .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , 
+    .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , 
+    .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , 
+    .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , 
+    .X ( chanx_left_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , 
+    .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , 
+    .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , 
+    .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , 
+    .X ( chanx_left_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , 
+    .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , 
+    .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , 
+    .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 ( 
+    .A ( bottom_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , 
+    .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , 
+    .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_111 ( .A ( aps_rename_513_ ) , 
+    .X ( bottom_grid_pin_14_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_35_inst_112 ( .A ( aps_rename_510_ ) , 
+    .X ( bottom_grid_pin_6_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_35_inst_113 ( .A ( aps_rename_511_ ) , 
+    .X ( bottom_grid_pin_7_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_35_inst_114 ( .A ( aps_rename_512_ ) , 
+    .X ( bottom_grid_pin_11_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_115 ( .A ( aps_rename_515_ ) , 
+    .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_116 ( .A ( aps_rename_514_ ) , 
+    .X ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_119 ) , 
+    .X ( bottom_grid_pin_10_[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3711262 ( .A ( ctsbuf_net_1104 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+wire copt_net_109 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_111 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_109 ) , 
+    .X ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( mem_out[3] ) , 
+    .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_112 ) , 
+    .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_110 ) , 
+    .X ( copt_net_112 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_53 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_54 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_50 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_51 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_52 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_47 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_48 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_49 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ;
+cbx_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_44 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_45 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_46 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_508_ ) , 
+    .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_41 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_42 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_43 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_38 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_39 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_40 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out , 
+    p0 ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ) ;
+input  [0:3] in ;
+input  [0:3] mem ;
+input  [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
+    .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
+    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input  [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
+    .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
+    .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
+    .data ( local_encoder2to4_0_data ) , 
+    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
+    .data ( local_encoder2to4_1_data ) , 
+    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_35 mux_l1_in_0_ ( .in ( in[0:3] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_36 mux_l1_in_1_ ( .in ( in[4:7] ) , 
+    .mem ( local_encoder2to4_0_data ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_37 mux_l2_in_0_ (
+    .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
+        mux_2level_basis_input4_mem4_1_out[0] , 
+        mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to4_1_data ) , 
+    .mem_inv ( local_encoder2to4_1_data_inv ) , 
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
+    .mem ( local_encoder2to4_0_data[0:1] ) , 
+    .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
+    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+input  [0:1] in ;
+input  [0:1] mem ;
+input  [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+