| //This design.inc.cal file contains calibre tool options which users are required to set, please refer to calibre user manual for detail explanation on each command |
| |
| /**********************************************************************************************************/ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /* | GLOBAL I/O DEFINITION SECTION | */ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /**********************************************************************************************************/ |
| //SOURCE CASE NO |
| //SOURCE SYSTEM SPICE |
| //SOURCE PATH __SOURCE_PATH__ |
| //SOURCE PRIMARY __SOURCE_PRIMARY__ |
| |
| //LAYOUT CASE NO |
| //LAYOUT SYSTEM GDSII |
| //LAYOUT PATH __LAYOUT_PATH__ |
| //LAYOUT PRIMARY __LAYOUT_PRIMARY__ |
| |
| //LVS REPORT lvs.rep |
| //LVS REPORT MAXIMUM ALL |
| //LVS REPORT OPTION S V |
| |
| //MASK RESULTS DATABASE mask.db |
| |
| //Please uncomment following line to run CCI Star-RCXT |
| //MASK SVDB DIRECTORY svdb CCI |
| |
| //Please uncomment following line to run XRC |
| //MASK SVDB DIRECTORY svdb QUERY XRC |
| |
| //DRC RESULTS DATABASE __LAYOUT_PRIMARY__.drc.db ASCII |
| //DRC SUMMARY REPORT __LAYOUT_PRIMARY__.drc.rep |
| |
| /**********************************************************************************************************/ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /* | DESCRIPTION SECTION | */ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /**********************************************************************************************************/ |
| |
| //PRECISION 1000 |
| //RESOLUTION 1 |
| // |
| //UNIT CAPACITANCE fF |
| //UNIT RESISTANCE OHM |
| //UNIT LENGTH u |
| // |
| //LAYOUT DEPTH ALL |
| //PORT DEPTH PRIMARY |
| |
| //LVS POWER NAME __USER_DEFINED_LVS_POWER_NAME__ |
| //LVS GROUND NAME __USER_DEFINED_LVS_GROUND_NAME__ |
| |
| // Modify the PWR, PWR1P8, PWR6 ang GND varables to the labels used in the design. |
| //VARIABLE PWR "VCC" "vcc" "vcc!" "VDD" "vdd" "vdd!" "DVDD" "6vdd" "VDD6" "vdd6" |
| //VARIABLE GND "GND" "gnd" "gnd!" "VSS" "vss" "vss!" "DVSS" |
| |
| //VARIABLE PWR3P3 "VDD3P3" "3p3vdd" "vdd3p3" "VCC3P3" "3p3vcc" "vcc3p3" |
| //VARIABLE PWR5 "VDD5" "5vdd" "vdd5" "VCC5" "5vcc" "vcc5" |
| //VARIABLE PWR6 "VDD6" "6vdd" "vdd6" "VCC6" "6vcc" "vcc6" |
| //VARIABLE PWR10 "VDD10" "10vdd" "vdd10" "VCC10" "10vcc" "vcc10" |
| |
| //VIRTUAL CONNECT COLON YES |
| //VIRTUAL CONNECT NAME "?" |
| |
| //LVS WRITE SOURCE NETLIST src.rep |
| //LVS WRITE LAYOUT NETLIST lay.rep |
| |
| /**********************************************************************************************************/ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /* | LVS GLOBAL OPTION DEFINITION SECTION | */ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /**********************************************************************************************************/ |
| |
| //LVS ABORT ON SOFTCHK NO |
| //LVS ABORT ON SUPPLY ERROR YES |
| //LVS ALL CAPACITOR PINS SWAPPABLE NO |
| //LVS CHECK PORT NAMES YES |
| //LVS COMPARE CASE NO |
| //LVS COMPONENT TYPE PROPERTY element |
| //LVS COMPONENT SUBTYPE PROPERTY model |
| //LVS IGNORE PORTS NO |
| //LVS ISOLATE SHORTS YES |
| //LVS PIN NAME PROPERTY phy_pin |
| //LVS PRESERVE PARAMETERIZED CELLS NO |
| //LVS PROPERTY RESOLUTION MAXIMUM ALL |
| //LVS PUSH DEVICES NO |
| //LVS SPICE PREFER PINS NO |
| //LVS SOFT SUBSTRATE PINS NO |
| LVS BUILTIN DEVICE PIN SWAP NO |
| LVS RECOGNIZE GATES NONE |
| |
| LVS REDUCE SPLIT GATES NO |
| // please uncomment the following lines if wish to perform the LVS REDUCE SPLIT GATE and comment out the line above "LVS REDUCE SPLIT GATES". |
| // the following lines are template only and user please modify the lines based on the design. |
| // the nf is only apply for LOGIC MOSFET when MOS_NF_BY_COUNT is turn on and also apply for ESD SAB MOSFET. |
| //LVS REDUCE SPLIT GATES YES [ |
| //effective W, L, M, nf |
| //M = 1 |
| //nf = 1 |
| //P = sum(W*L) |
| //Q = sum(W/L) |
| //W = sqrt(P*Q) |
| //L = sqrt(P/Q) |
| //] |
| |
| /**********************************************************************************************************/ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /* | PEX GLOBAL OPTION DEFINITION SECTION | */ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /**********************************************************************************************************/ |
| |
| //#IFDEF PEX_RUN |
| //PEX NETLIST net.dspf DSPF LAYOUTNAMES LOCATION |
| //PEX REPORT __LAYOUT_PRIMARY__.report LAYOUTNAMES |
| //#ENDIF // PEX_RUN |
| |
| |
| /**********************************************************************************************************/ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /* | SET LVS FILTER OPTIONS | */ |
| /* +----------------------------------------------------------------------------------------------------+ */ |
| /**********************************************************************************************************/ |
| |
| //LVS FILTER UNUSED OPTION AC AD AF AG C F G RC RE ZC YB RG ZD SOURCE LAYOUT |
| |
| // AC - Filters MOS devices with floating gate pin, and source and drain pins connected to a single power net. |
| // AD - Filters MOS devices with floating gate pin, and source and drain pins connected to a single ground net. |
| // AF - Filters MOS devices with source and drain pins tied together. |
| // AG - Filters MOS devices with all pins tied together, including bulk and optional pins. |
| // C - Filters MOS devices with gate tied to power or ground and either the source or drain floating. |
| // F - Filters MN and LDDN devices with the gate tied to ground. |
| // G - Filters MP and LDDP devices with the gate tied to power. |
| |
| // RC - Filters Resistors with POS and NEG pins tied together. |
| |
| // RE - Filters Capacitors with POS and NEG pins tied together. |
| // ZC - Filters Capacitors with both POS and NEG pins floating. |
| |
| // YB - Filters Bipolar transistors with base and emitter tied together. |
| |
| // RG - Filters Diodes with POS and NEG pins tied together. |
| // ZD - Filters Diodes with both POS and NEG pins floating. |
| |
| |
| |
| |
| //In Rev1F release, some of the devices name had been changed to align to Design Rule's devices name. |
| //So, In order to enable this LVS runset for the old design, following step might be needed for the |
| //corresponding devices name mapping. |
| //Example of LVS DEVICE Mapping: |
| |
| //LVS MAP DEVICE MN(nmos_1p8_dw) MN(nmos_1p8) LAYOUT |
| //LVS MAP DEVICE MP(pmos_1p8_dw) MP(pmos_1p8) LAYOUT |
| //LVS MAP DEVICE D(np_1p8_dw) D(np_1p8) LAYOUT |
| //LVS MAP DEVICE D(pn_1p8_dw) D(pn_1p8) LAYOUT |
| //LVS MAP DEVICE R(nplus_u_dw) R(nplus_u) LAYOUT |
| //LVS MAP DEVICE R(pplus_u_dw) R(pplus_u) LAYOUT |
| //LVS MAP DEVICE R(nplus_s_dw) R(nplus_s) LAYOUT |
| //LVS MAP DEVICE R(pplus_s_dw) R(pplus_s) LAYOUT |
| //LVS MAP DEVICE R(npolyf_u_dw) R(npolyf_u) LAYOUT |
| //LVS MAP DEVICE R(ppolyf_u_dw) R(ppolyf_u) LAYOUT |
| //LVS MAP DEVICE R(npolyf_s_dw) R(npolyf_s) LAYOUT |
| //LVS MAP DEVICE R(ppolyf_s_dw) R(ppolyf_s) LAYOUT |
| //LVS MAP DEVICE R(ppolyf_u_1k_dw) R(ppolyf_u_1k) LAYOUT |
| //LVS MAP DEVICE R(ppolyf_u_2k_dw) R(ppolyf_u_2k) LAYOUT |
| //LVS MAP DEVICE R(ppolyf_u_fhr_16p0_lv_dw) R(ppolyf_u_fhr_16p0_lv) LAYOUT |
| //LVS MAP DEVICE C(nmoscap_1p8_dw) C(nmoscap_1p8) LAYOUT |
| //LVS MAP DEVICE C(pmoscap_1p8_dw) C(pmoscap_1p8) LAYOUT |
| //LVS MAP DEVICE C(pis_1p8_dw) C(pis_1p8) LAYOUT |
| //LVS MAP DEVICE C(pis_6p0_dw) C(pis_6p0) LAYOUT |
| //LVS MAP DEVICE C(pn_varactor_1p8_dw) C(pn_varactor_1p8) LAYOUT |
| //LVS MAP DEVICE C(pn_varactor_6p0_dw) C(pn_varactor_6p0) LAYOUT |
| |
