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foss-eda-tools / openflow-drc-tests / 9d0a760502e7abbea2c8d37bfb3c4866dbe9dbf3 / . / pdk / skywater / s8 / V2.0.1 / DRC / Calibre / s8_latchupRules
blob: 67785e8d260cfa12d9ac6ea3fc4e67abc1e30a1a [file] [log] [blame]
/// -*- c++ -*-
/// latchup: by vun on Oct 11 10:06:00 2017
/// Copyright (c) 2017 by Cypress Semiconductor
/// Cypress Confidential Information
/// s8phirs-10rmisc. (latchup) TDR:001-69087 REV AB
/// metopNumber: none metopLayer: "met3"
/// Switches = ("local_sub")
/// vccNets: ("vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2")
/// vssNets: ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
/// ioNets: ("io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad")
/// intVccNets: ("vpwr2")
/// mainGroundNet : ("vgnd")
/// mainPowerNet : ("vpwr")
/// powerNets_1p8v : none
/// powerNets_3p3or5v : none
/// vppPadNets : ("vpp_pad")
/// powerGroundPairs : (("vpwr" "vgnd"))
/// VCSEL_pairs : none
/// esd7_6Nets : none
/// esd8_4Nets : none
/// $Id: s8_latchupRules 2 2018/06/18 18:10:16 GMT ssoares Exp $
/// Tolerance for round-off errors on skew edges
DRC TOLERANCE FACTOR 0.001
DRC INCREMENTAL CONNECT YES
// bmadden
// bug 1048
// 032618
INCLUDE "$PDK_HOME/DRC/Calibre/CALtvfRunTime.svrf"
LAYER nwell 1000
LAYER MAP 64 DATATYPE 20 1000 // nwell drawing
LAYER diff 1001
LAYER MAP 65 DATATYPE 20 1001 // diff drawing
LAYER tap 1002
LAYER MAP 65 DATATYPE 44 1002 // tap drawing
LAYER lvtn 1003
LAYER MAP 125 DATATYPE 44 1003 // lvtn drawing
LAYER hvi 1004
LAYER MAP 75 DATATYPE 20 1004 // hvi drawing
LAYER tunm 1005
LAYER MAP 80 DATATYPE 20 1005 // tunm drawing
LAYER npc 1006
LAYER MAP 95 DATATYPE 20 1006 // npc drawing
LAYER nsdm 1007
LAYER MAP 93 DATATYPE 44 1007 // nsdm drawing
LAYER psdm 1008
LAYER MAP 94 DATATYPE 20 1008 // psdm drawing
LAYER pmm 1009
LAYER MAP 85 DATATYPE 44 1009 // pmm drawing
LAYER ldntm 1010
LAYER MAP 11 DATATYPE 44 1010 // ldntm drawing
LAYER vhvi 1011
LAYER MAP 74 DATATYPE 21 1011 // vhvi drawing
LAYER target 1012
LAYER MAP 76 DATATYPE 44 1012 // target drawing
LAYER pnp 1013
LAYER MAP 82 DATATYPE 44 1013 // pnp drawing
LAYER metal1 1014
LAYER MAP 68 DATATYPE 20 1014 // met1 drawing
LAYER metal2 1015
LAYER MAP 69 DATATYPE 20 1015 // met2 drawing
LAYER metal3 1016
LAYER MAP 70 DATATYPE 20 1016 // met3 drawing
LAYER metal4 1017
LAYER MAP 71 DATATYPE 20 1017 // met4 drawing
LAYER metal5 1018
LAYER MAP 72 DATATYPE 20 1018 // met5 drawing
LAYER Via 1019
LAYER MAP 68 DATATYPE 44 1019 // via drawing
LAYER Via2 1020
LAYER MAP 69 DATATYPE 44 1020 // via2 drawing
LAYER Via3 1021
LAYER MAP 70 DATATYPE 44 1021 // via3 drawing
LAYER Via4 1022
LAYER MAP 71 DATATYPE 44 1022 // via4 drawing
LAYER rdl 1023
LAYER MAP 74 DATATYPE 20 1023 // rdl drawing
LAYER poly 1024
LAYER MAP 66 DATATYPE 20 1024 // poly drawing
LAYER Licon1 1025
LAYER MAP 66 DATATYPE 44 1025 // licon1 drawing
LAYER Li1 1026
LAYER MAP 67 DATATYPE 20 1026 // li1 drawing
LAYER Mcon 1027
LAYER MAP 67 DATATYPE 44 1027 // mcon drawing
LAYER diffTap 1001 1002
// 1001 -> diff drawing
// 1002 -> tap drawing
LAYER paddg 1028
LAYER MAP 76 DATATYPE 20 1028 // pad drawing
LAYER dnwelldg 1029
LAYER MAP 64 DATATYPE 18 1029 // dnwell drawing
LAYER li1tt 1030 1031 1032 1033
LAYER MAP 67 TEXTTYPE 20 1030 // li1 drawing
LAYER MAP 67 TEXTTYPE 5 1031 // li1 label
LAYER MAP 67 TEXTTYPE 23 1032 // li1 net
LAYER MAP 67 TEXTTYPE 16 1033 // li1 pin
LAYER met1tt 1034 1035 1036 1037
LAYER MAP 68 TEXTTYPE 20 1034 // met1 drawing
LAYER MAP 68 TEXTTYPE 5 1035 // met1 label
LAYER MAP 68 TEXTTYPE 23 1036 // met1 net
LAYER MAP 68 TEXTTYPE 16 1037 // met1 pin
LAYER met2tt 1038 1039 1040 1041
LAYER MAP 69 TEXTTYPE 20 1038 // met2 drawing
LAYER MAP 69 TEXTTYPE 5 1039 // met2 label
LAYER MAP 69 TEXTTYPE 23 1040 // met2 net
LAYER MAP 69 TEXTTYPE 16 1041 // met2 pin
LAYER met3tt 1042 1043 1044 1045
LAYER MAP 70 TEXTTYPE 20 1042 // met3 drawing
LAYER MAP 70 TEXTTYPE 5 1043 // met3 label
LAYER MAP 70 TEXTTYPE 23 1044 // met3 net
LAYER MAP 70 TEXTTYPE 16 1045 // met3 pin
LAYER met4tt 1046 1047 1048 1049
LAYER MAP 71 TEXTTYPE 20 1046 // met4 drawing
LAYER MAP 71 TEXTTYPE 5 1047 // met4 label
LAYER MAP 71 TEXTTYPE 23 1048 // met4 net
LAYER MAP 71 TEXTTYPE 16 1049 // met4 pin
LAYER met5tt 1050 1051 1052 1053
LAYER MAP 72 TEXTTYPE 20 1050 // met5 drawing
LAYER MAP 72 TEXTTYPE 5 1051 // met5 label
LAYER MAP 72 TEXTTYPE 23 1052 // met5 net
LAYER MAP 72 TEXTTYPE 16 1053 // met5 pin
LAYER polytt 1054 1055 1056 1057
LAYER MAP 66 TEXTTYPE 20 1054 // poly drawing
LAYER MAP 66 TEXTTYPE 5 1055 // poly label
LAYER MAP 66 TEXTTYPE 23 1056 // poly net
LAYER MAP 66 TEXTTYPE 16 1057 // poly pin
LAYER difftt 1058 1059 1060 1061
LAYER MAP 65 TEXTTYPE 20 1058 // diff drawing
LAYER MAP 65 TEXTTYPE 6 1059 // diff label
LAYER MAP 65 TEXTTYPE 23 1060 // diff net
LAYER MAP 65 TEXTTYPE 16 1061 // diff pin
LAYER rdltt 1062 1063 1064
LAYER MAP 74 TEXTTYPE 20 1062 // rdl drawing
LAYER MAP 74 TEXTTYPE 5 1063 // rdl label
LAYER MAP 74 TEXTTYPE 16 1064 // rdl pin
LAYER poly_pin 1065
LAYER MAP 66 DATATYPE 16 1065 // poly pin
LAYER li1_pin 1066
LAYER MAP 67 DATATYPE 16 1066 // li1 pin
LAYER met1_pin 1067
LAYER MAP 68 DATATYPE 16 1067 // met1 pin
LAYER met2_pin 1068
LAYER MAP 69 DATATYPE 16 1068 // met2 pin
LAYER met3_pin 1069
LAYER MAP 70 DATATYPE 16 1069 // met3 pin
LAYER met4_pin 1070
LAYER MAP 71 DATATYPE 16 1070 // met4 pin
LAYER met5_pin 1071
LAYER MAP 72 DATATYPE 16 1071 // met5 pin
LAYER rdl_pin 1072
LAYER MAP 74 DATATYPE 16 1072 // rdl pin
LAYER nwellpt 1073
LAYER MAP 64 TEXTTYPE 16 1073 // nwell pin
LAYER MAP 64 TEXTTYPE 0 1073 // nwell pin
LAYER diffpt 1074
LAYER MAP 65 TEXTTYPE 16 1074 // diff pin
LAYER MAP 65 TEXTTYPE 0 1074 // diff pin
LAYER polypt 1075
LAYER MAP 66 TEXTTYPE 16 1075 // poly pin
LAYER MAP 66 TEXTTYPE 0 1075 // poly pin
LAYER Li1pt 1076
LAYER MAP 67 TEXTTYPE 16 1076 // li1 pin
LAYER MAP 67 TEXTTYPE 0 1076 // li1 pin
LAYER Met1pt 1077
LAYER MAP 68 TEXTTYPE 16 1077 // met1 pin
LAYER MAP 68 TEXTTYPE 0 1077 // met1 pin
LAYER Met2pt 1078
LAYER MAP 69 TEXTTYPE 16 1078 // met2 pin
LAYER MAP 69 TEXTTYPE 0 1078 // met2 pin
LAYER Met3pt 1079
LAYER MAP 70 TEXTTYPE 16 1079 // met3 pin
LAYER MAP 70 TEXTTYPE 0 1079 // met3 pin
LAYER Met4pt 1080
LAYER MAP 71 TEXTTYPE 16 1080 // met4 pin
LAYER MAP 71 TEXTTYPE 0 1080 // met4 pin
LAYER Met5pt 1081
LAYER MAP 72 TEXTTYPE 16 1081 // met5 pin
LAYER MAP 72 TEXTTYPE 0 1081 // met5 pin
LAYER Rdlpt 1082
LAYER MAP 74 TEXTTYPE 16 1082 // rdl pin
LAYER MAP 74 TEXTTYPE 0 1082 // rdl pin
LAYER padtt 1083 1084
LAYER MAP 76 TEXTTYPE 20 1083 // pad drawing
LAYER MAP 76 TEXTTYPE 5 1084 // pad label
LAYER pad_pin 1085
LAYER MAP 76 DATATYPE 16 1085 // pad pin
LAYER padpt 1086
LAYER MAP 76 TEXTTYPE 16 1086 // pad pin
LAYER MAP 76 TEXTTYPE 0 1086 // pad pin
LAYER FRAMEID 1087
LAYER MAP 81 DATATYPE 3 1087 // areaid frame
LAYER localSub 1088
LAYER MAP 81 DATATYPE 53 1088 // areaid substrateCut
LAYER ESDID 1089
LAYER MAP 81 DATATYPE 19 1089 // areaid esd
LAYER DIODEID 1090
LAYER MAP 81 DATATYPE 23 1090 // areaid diode
LAYER COREID 1091
LAYER MAP 81 DATATYPE 2 1091 // areaid core
LAYER SEALID 1092
LAYER MAP 81 DATATYPE 1 1092 // areaid seal
LAYER STDCID 1093
LAYER MAP 81 DATATYPE 4 1093 // areaid standardc
LAYER ENID 1094
LAYER MAP 81 DATATYPE 57 1094 // areaid extendedDrain
LAYER LTDID 1095
LAYER MAP 81 DATATYPE 14 1095 // areaid lowTapDensity
LAYER INJID 1096
LAYER MAP 81 DATATYPE 17 1096 // areaid injection
LAYER HVNID 1097
LAYER MAP 81 DATATYPE 63 1097 // areaid hvnwell
LAYER pwellres 1098
LAYER MAP 64 DATATYPE 13 1098 // pwell res
LAYER polyres 1099
LAYER MAP 66 DATATYPE 13 1099 // poly res
LAYER met1res 1100
LAYER MAP 68 DATATYPE 13 1100 // met1 res
LAYER met2res 1101
LAYER MAP 69 DATATYPE 13 1101 // met2 res
LAYER met3res 1102
LAYER MAP 70 DATATYPE 13 1102 // met3 res
LAYER met4res 1103
LAYER MAP 71 DATATYPE 13 1103 // met4 res
LAYER met5res 1104
LAYER MAP 72 DATATYPE 13 1104 // met5 res
LAYER diffres 1105
LAYER MAP 65 DATATYPE 13 1105 // diff res
LAYER textlabel 1106
LAYER MAP 83 TEXTTYPE 44 1106 // text drawing
LAYOUT BASE LAYER diff
LAYOUT BASE LAYER tap
LAYOUT BASE LAYER poly
LAYOUT BASE LAYER DIODEID
LAYOUT BASE LAYER ESDID
LAYOUT BASE LAYER COREID
LAYOUT BASE LAYER diffres
LAYOUT BASE LAYER polyres
LAYOUT BASE LAYER met1res
LAYOUT BASE LAYER met2res
LAYOUT BASE LAYER met3res
LAYOUT BASE LAYER met4res
LAYOUT BASE LAYER met5res
PDIFF = diff AND nwell
NDIFF = diff NOT PDIFF
NTAP = tap AND nwell
PTAP = tap NOT NTAP
gate = poly AND diff
NSRCDRN = NDIFF NOT (gate OR diffres)
PSRCDRN = PDIFF NOT (gate OR diffres)
PolyNoRes = poly NOT polyres
ResPoly = poly AND polyres
nDiffRes = NDIFF AND diffres
pDiffRes = PDIFF AND diffres
Met1EsdRes = (metal1 AND met1res) AND ESDID
Met1 = metal1 NOT Met1EsdRes
Met2EsdRes = (metal2 AND met2res) AND ESDID
Met2 = metal2 NOT Met2EsdRes
Met3EsdRes = (metal3 AND met3res) AND ESDID
Met3 = metal3 NOT Met3EsdRes
Met4EsdRes = (metal4 AND met4res) AND ESDID
Met4 = metal4 NOT Met4EsdRes
Met5EsdRes = (metal5 AND met5res) AND ESDID
Met5 = metal5 NOT Met5EsdRes
Licon1ply = Licon1 OUTSIDE diffTap
Licon1fom = Licon1 NOT Licon1ply
Licon1Nfom = (Licon1fom AND NDIFF) OR (Licon1fom AND NTAP)
Licon1Pfom = (Licon1fom AND PDIFF) OR (Licon1fom AND PTAP)
Licon1diff = Licon1fom AND diff
LAYER SigPadDiff 1107
LAYER MAP 81 DATATYPE 6 1107 // areaid sigPadDiff
LAYER SigPadWell 1108
LAYER MAP 81 DATATYPE 7 1108 // areaid sigPadWell
LAYER SigPadMetNtr 1109
LAYER MAP 81 DATATYPE 8 1109 // areaid sigPadMetNtr
pad = paddg NOT (WITH TEXT paddg "probe-only" textlabel)
probe_pad = WITH TEXT paddg "probe-only" textlabel
switched_intPower_met1 = WITH TEXT met1 "switched_power" textlabel
dnwell = COPY dnwelldg
SubstrateAll = EXTENT
dnwANDnwell = dnwelldg AND nwell
SubstrateIso = SubstrateAll NOT ((dnwelldg NOT (SIZE dnwelldg BY -0.01)) OR dnwANDnwell)
localSubRing = localSub NOT (SIZE localSub BY -0.005)
SubstrateLocal = SubstrateIso NOT localSubRing
isolatedSubstrate = COPY SubstrateLocal
isolatedSubNoPWR = isolatedSubstrate NOT pwellres
isoSubPTap = PTAP AND isolatedSubNoPWR
/// CALconnectZone started - zoneName was nil
CONNECT nwell NTAP
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT Met3 met3tt
CONNECT Met2 met2tt
CONNECT Met1 met1tt
CONNECT Li1 li1tt
CONNECT NSRCDRN difftt
CONNECT PSRCDRN difftt
CONNECT Li1 li1_pin BY Li1pt
CONNECT Met1 met1_pin BY Met1pt
CONNECT Met2 met2_pin BY Met2pt
CONNECT Met3 met3_pin BY Met3pt
CONNECT switched_intPower_met1 Met1
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT PolyNoRes gate
CONNECT PolyNoRes polytt
CONNECT PolyNoRes poly_pin BY polypt
CONNECT pad Met5
CONNECT probe_pad Met5
CONNECT Met5 Met4 BY Via4
CONNECT Met5 met5tt
CONNECT Met5 met5_pin BY Met5pt
CONNECT Met4 Met3 BY Via3
CONNECT Met4 met4tt
CONNECT Met4 met4_pin BY Met4pt
CONNECT rdl pad BY pmm
CONNECT rdl probe_pad BY pmm
/// CALconnectZone done. zoneName is now zone_1
vccNetsNTAP = NET NTAP "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccSipNTAP = NET AREA RATIO NTAP switched_intPower_met1 > 0
vccNTAP = vccNetsNTAP OR vccSipNTAP
vssPTAP = NET PTAP "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vccPTAP = NET PTAP "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vssNSD = NET NSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssPSD = NET PSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vccNetsPSD = NET PSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccSipPSD = NET AREA RATIO PSRCDRN switched_intPower_met1 > 0
vccNetsNSD = NET NSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccSipNSD = NET AREA RATIO NSRCDRN switched_intPower_met1 > 0
vccPSD = vccNetsPSD OR vccSipPSD
vccNSD = vccNetsNSD OR vccSipNSD
vssNwell = NET nwell "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
lvvccNwell = COPY 4000
ioNSDnet = NET NSRCDRN "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
ioPSDnet = NET PSRCDRN "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
ioNTAPnet = NET NTAP "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
ioPTAPnet = NET PTAP "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
ioPads = NET pad "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
ioPadConnNSDnet = NET AREA RATIO NSRCDRN ioPads > 0
ioPadConnPSDnet = NET AREA RATIO PSRCDRN ioPads > 0
NSDsigPad = NSRCDRN INSIDE SigPadDiff
PSDsigPad = PSRCDRN INSIDE SigPadDiff
SigPadNtr = SigPadMetNtr INSIDE SigPadDiff
NSDsigPadNtr = NSRCDRN INSIDE SigPadNtr
PSDsigPadNtr = PSRCDRN INSIDE SigPadNtr
NTAPsigPad = NTAP INSIDE SigPadDiff
PTAPsigPad = PTAP INSIDE SigPadDiff
NTAPsigPadNtr = NTAP INSIDE SigPadNtr
PTAPsigPadNtr = PTAP INSIDE SigPadNtr
SigPadWellNtr = SigPadMetNtr INSIDE SigPadWell
nwellSigPadNtr = nwell INSIDE SigPadWellNtr
NSDsigPadConn = STAMP NSDSigPad BY NSRCDRN
PSDsigPadConn = STAMP PSDSigPad BY PSRCDRN
NTAPsigPadConn = STAMP NTAPSigPad BY NTAP
PTAPsigPadConn = STAMP PTAPSigPad BY PTAP
ioNSD = NSDsigPad OR ioNSDnet
ioPSD = PSDsigPad OR ioPSDnet
ioNTAP = NTAPsigPad OR ioNTAPnet
ioPTAP = PTAPsigPad OR ioPTAPnet
ioPadConnNSD = NSDsigPadNtr OR ioPadConnNSDnet
ioPadConnPSD = PSDsigPadNtr OR ioPadConnPSDnet
ioNSDntr = (NSDsigPad AND sigPadMetNtr) OR ioNSDnet
ioPSDntr = (PSDsigPad AND sigPadMetNtr) OR ioPSDnet
nwellHole = HOLES nwell
ntapRing = (DONUT NTAP) NOT SEALID
ptapRing = (DONUT PTAP) NOT SEALID
ptapRingFilled = HOLES ptapRing
pTaplicon = licon1 AND PTAP
nTaplicon = licon1 AND NTAP
pTapliconVss = licon1 AND vssPTAP
pTapliconNonVss = pTaplicon NOT pTapliconVss
nTapliconVcc = licon1 AND vccNTAP
POLYandNDIFF = poly AND NDIFF
POLYandPDIFF = poly AND PDIFF
diffCore = diff AND COREID
ndiffPeri = NDIFF NOT diffCore
pdiffPeri = PDIFF NOT diffCore
nwellArea = (SIZE PDIFF BY 1.5) AND nwell
pwellArea = (SIZE NDIFF BY 1.5) NOT nwell
nonVccNwell = nwell OUTSIDE vccNTAP
nonPnpNTap = NTAP NOT pnp
nonPnpPTap = PTAP NOT pnp
nDiffRing = DONUT NDIFF
nDiffHole = HOLES nDiffRing
nWellTap = nwell INSIDE NTAP
nWellTapInHole = nDiffHole INSIDE nWellTap
ESDnWellTapTmp = nWellTapInHole AND ESDID
ESDnWellTap = STAMP ESDnWellTapTmp BY NTAP
nwellDIOESD = nwell AND
(ESDID AND DIODEID)
ESD_diode = nwellDIOESD OUTSIDE (ESDnWellTap OR poly)
ESD_diff = diff AND ESDID
slatchAB = EXTENT CELL "slatchA*" "slatchB*" ORIGINAL
slatch_lvA = EXTENT CELL "slatch_lvA*" ORIGINAL
vssNwellNoXmtCells = vssNwell NOT (INSIDE CELL nwell "s8iom0s8_top_lvc_b2b_wopad" "s8iom0s8_top_lvclamp" "s8atlasana_esd_gnd2gnd_sub_dnwl" "s8fpafeg1_tk_lvc_b2b_wopad")
ptapRingFilledNotRing = ptapRingFilled NOT ptapRing
ptapRingWithVssNwell = INTERACT ptapRingFilledNotRing vssNwellNoXmtCells
ptapRingNoVssNwell = INTERACT ptapRing (NOT INTERACT ptapRingFilledNotRing vssNwellNoXmtCells)
vssNwellPtapRing = (ptapRing NOT ptapRingNoVssNwell) OUTSIDE ptapRingWithVssNwell
"r_0_lu.5.7a" {
@ lu.5.7a: vssNwellPtapRing must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET vssNwellPtapRing "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
"r_1_lu.5.7b" {
@ lu.5.7b: vssNwellNoXmtCells must overlap ptapRingFilled
vssNwellNoXmtCells OUTSIDE ptapRingFilled
}
sealHole = HOLES SEALID
lu1_2_xmt = ESD_diff OR COREID
IOregionN = SIZE ioPadConnNSD BY 50
IOregionP = SIZE ioPadConnPSD BY 50
IOregion = IOregionP OR IOregionN
isoPwell = (dnwell AND nwellHole) NOT nwell
isoPwellVccPdiff = INTERACT isoPwell (INTERACT nwell (nwell AND vccPSD))
isoPwellNoVccPdiff = isoPwell NOT isoPwellVccPdiff
ntapPsrcdrnMetConn = NET AREA RATIO NTAP PSRCDRN > 0 INSIDE OF LAYER NWELL
q0sealHole = COPY 4001
ndiffInSeal = TVF CALtvfLay1AndLay2 sealHole NDIFF q0sealHole
lu1_2_ndiff = ndiffInSeal NOT lu1_2_xmt
ndiffNonIsoPwell = lu1_2_ndiff NOT isoPwell
ndiffNonIsoIO = ndiffNonIsoPwell AND IOregion
ndiffIsoPwellPSDvccIO = (lu1_2_ndiff AND isoPwellVccPdiff) AND IOregion
ndiffIsoPwellNoPSDvccIO = (lu1_2_ndiff AND isoPwellNoVccPdiff) AND IOregion
ndiffNonIso = ndiffNonIsoPwell NOT IOregion
ndiffIsoPwellPSDvcc = (lu1_2_ndiff AND isoPwellVccPdiff) NOT IOregion
ndiffIsoPwellNoPSDvcc = (lu1_2_ndiff AND isoPwellNoVccPdiff) NOT IOregion
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q0pTaplicon = pTaplicon NOT nwell
q1pTaplicon = SIZE q0pTaplicon BY 6 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q1pTaplicon (pTaplicon sized around nwell) is now 6.0
q0ndiffNonIsoIO = ndiffNonIsoIO NOT nwell
q1ndiffNonIsoIO = q0ndiffNonIsoIO NOT q1pTaplicon
"r_2_lu1.2.1a" {
@ lu1.2.1a: 6.000 max. dist. of ndiffNonIsoIO from pTaplicon around nwell
COPY q1ndiffNonIsoIO
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q2pTaplicon = pTaplicon NOT nwell
q3pTaplicon = SIZE q2pTaplicon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q3pTaplicon (pTaplicon sized around nwell) is now 15.0
q0ndiffNonIso = ndiffNonIso NOT nwell
q1ndiffNonIso = q0ndiffNonIso NOT q3pTaplicon
"r_3_lu1.2.1b" {
@ lu1.2.1b: 15.000 max. dist. of ndiffNonIso from pTaplicon around nwell
COPY q1ndiffNonIso
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q4pTaplicon = pTaplicon NOT nwell
q5pTaplicon = SIZE q4pTaplicon BY 6 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q5pTaplicon (pTaplicon sized around nwell) is now 6.0
q0ndiffIsoPwellPSDvccIO = ndiffIsoPwellPSDvccIO NOT nwell
q1ndiffIsoPwellPSDvccIO = q0ndiffIsoPwellPSDvccIO NOT q5pTaplicon
"r_4_lu1.2.2a" {
@ lu1.2.2a: 6.000 max. dist. of ndiffIsoPwellPSDvccIO from pTaplicon around nwell inside dnwell
q1ndiffIsoPwellPSDvccIO AND dnwell
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q6pTaplicon = pTaplicon NOT nwell
q7pTaplicon = SIZE q6pTaplicon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q7pTaplicon (pTaplicon sized around nwell) is now 15.0
q0ndiffIsoPwellPSDvcc = ndiffIsoPwellPSDvcc NOT nwell
q1ndiffIsoPwellPSDvcc = q0ndiffIsoPwellPSDvcc NOT q7pTaplicon
"r_5_lu1.2.2b" {
@ lu1.2.2b: 15.000 max. dist. of ndiffIsoPwellPSDvcc from pTaplicon around nwell inside dnwell
q1ndiffIsoPwellPSDvcc AND dnwell
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q8pTaplicon = pTaplicon NOT nwell
q9pTaplicon = SIZE q8pTaplicon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q9pTaplicon (pTaplicon sized around nwell) is now 15.0
q0ndiffIsoPwellNoPSDvccIO = ndiffIsoPwellNoPSDvccIO NOT nwell
q1ndiffIsoPwellNoPSDvccIO = q0ndiffIsoPwellNoPSDvccIO NOT q9pTaplicon
"r_6_lu1.2.3a" {
@ lu1.2.3a: 15.000 max. dist. of ndiffIsoPwellNoPSDvccIO from pTaplicon around nwell inside dnwell
q1ndiffIsoPwellNoPSDvccIO AND dnwell
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q10pTaplicon = pTaplicon NOT nwell
q11pTaplicon = SIZE q10pTaplicon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q11pTaplicon (pTaplicon sized around nwell) is now 15.0
q0ndiffIsoPwellNoPSDvcc = ndiffIsoPwellNoPSDvcc NOT nwell
q1ndiffIsoPwellNoPSDvcc = q0ndiffIsoPwellNoPSDvcc NOT q11pTaplicon
"r_7_lu1.2.3b" {
@ lu1.2.3b: 15.000 max. dist. of ndiffIsoPwellNoPSDvcc from pTaplicon around nwell inside dnwell
q1ndiffIsoPwellNoPSDvcc AND dnwell
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
q1sealHole = COPY 4002
ndiffInExtent = TVF CALtvfLay2OrEmpty sealHole NDIFF q1sealHole
lu1_2_ndiffAll = ndiffInExtent NOT lu1_2_xmt
lu1_2_ndiff_tightTap = lu1_2_ndiffAll NOT LTDID
lu1_2_ndiff_looseTap = lu1_2_ndiffAll AND LTDID
ndiffNonIsoTTap = lu1_2_ndiff_tightTap NOT isoPwell
ndiffIsoPwellPSDvccTTap = lu1_2_ndiff_tightTap AND isoPwellVccPdiff
ndiffIsoPwellNoPSDvccTTap = lu1_2_ndiff_tightTap AND isoPwellNoVccPdiff
ndiffNonIsoLTap = lu1_2_ndiff_looseTap NOT isoPwell
ndiffIsoPwellPSDvccLTap = lu1_2_ndiff_looseTap AND isoPwellVccPdiff
ndiffIsoPwellNoPSDvccLTap = lu1_2_ndiff_looseTap AND isoPwellNoVccPdiff
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q12pTaplicon = pTaplicon NOT nwell
q13pTaplicon = SIZE q12pTaplicon BY 6 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q13pTaplicon (pTaplicon sized around nwell) is now 6.0
q0ndiffNonIsoTTap = ndiffNonIsoTTap NOT nwell
q1ndiffNonIsoTTap = q0ndiffNonIsoTTap NOT q13pTaplicon
"r_8_lu1.2.1a" {
@ lu1.2.1a: 6.000 max. dist. of ndiffNonIsoTTap from pTaplicon around nwell
COPY q1ndiffNonIsoTTap
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q14pTaplicon = pTaplicon NOT nwell
q15pTaplicon = SIZE q14pTaplicon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q15pTaplicon (pTaplicon sized around nwell) is now 15.0
q0ndiffNonIsoLTap = ndiffNonIsoLTap NOT nwell
q1ndiffNonIsoLTap = q0ndiffNonIsoLTap NOT q15pTaplicon
"r_9_lu1.2.1b" {
@ lu1.2.1b: 15.000 max. dist. of ndiffNonIsoLTap from pTaplicon around nwell
COPY q1ndiffNonIsoLTap
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q16pTaplicon = pTaplicon NOT nwell
q17pTaplicon = SIZE q16pTaplicon BY 6 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q17pTaplicon (pTaplicon sized around nwell) is now 6.0
q0ndiffIsoPwellPSDvccTTap = ndiffIsoPwellPSDvccTTap NOT nwell
q1ndiffIsoPwellPSDvccTTap = q0ndiffIsoPwellPSDvccTTap NOT q17pTaplicon
"r_10_lu1.2.2a" {
@ lu1.2.2a: 6.000 max. dist. of ndiffIsoPwellPSDvccTTap from pTaplicon around nwell inside dnwell
q1ndiffIsoPwellPSDvccTTap AND dnwell
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q18pTaplicon = pTaplicon NOT nwell
q19pTaplicon = SIZE q18pTaplicon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q19pTaplicon (pTaplicon sized around nwell) is now 15.0
q0ndiffIsoPwellPSDvccLtap = ndiffIsoPwellPSDvccLtap NOT nwell
q1ndiffIsoPwellPSDvccLtap = q0ndiffIsoPwellPSDvccLtap NOT q19pTaplicon
"r_11_lu1.2.2b" {
@ lu1.2.2b: 15.000 max. dist. of ndiffIsoPwellPSDvccLtap from pTaplicon around nwell inside dnwell
q1ndiffIsoPwellPSDvccLtap AND dnwell
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q20pTaplicon = pTaplicon NOT nwell
q21pTaplicon = SIZE q20pTaplicon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q21pTaplicon (pTaplicon sized around nwell) is now 15.0
q0ndiffIsoPwellNoPSDvccTTap = ndiffIsoPwellNoPSDvccTTap NOT nwell
q1ndiffIsoPwellNoPSDvccTTap = q0ndiffIsoPwellNoPSDvccTTap NOT q21pTaplicon
"r_12_lu1.2.3a" {
@ lu1.2.3a: 15.000 max. dist. of ndiffIsoPwellNoPSDvccTTap from pTaplicon around nwell inside dnwell
q1ndiffIsoPwellNoPSDvccTTap AND dnwell
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
/// CALmaxElectDistOutside: sizing from pTaplicon around nwell; min_width: 0.84 -> max_incr: 0.59
q22pTaplicon = pTaplicon NOT nwell
q23pTaplicon = SIZE q22pTaplicon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
/// Total sizing of q23pTaplicon (pTaplicon sized around nwell) is now 15.0
q0ndiffIsoPwellNoPSDvccLTap = ndiffIsoPwellNoPSDvccLTap NOT nwell
q1ndiffIsoPwellNoPSDvccLTap = q0ndiffIsoPwellNoPSDvccLTap NOT q23pTaplicon
"r_13_lu1.2.3b" {
@ lu1.2.3b: 15.000 max. dist. of ndiffIsoPwellNoPSDvccLTap from pTaplicon around nwell inside dnwell
q1ndiffIsoPwellNoPSDvccLTap AND dnwell
}
/// CALmaxElectDistOutside: Done sizing from pTaplicon around nwell
lu1_3_xmt = ESD_diff OR COREID
nwellWithPdiff = INTERACT nwell (nwell AND pdiff)
nwellNotDeepNW = NOT INTERACT nwellWithPdiff dnwell
deepNWisoPW = INTERACT dnwell (dnwell AND isoPwell)
nwellDeepNWisoPW = INTERACT nwellWithPdiff deepNWisoPW
nwellDeepNWnoIsoPW = (NOT INTERACT nwellWithPdiff deepNWisoPW) AND dnwell
q2sealHole = COPY 4003
pdiffInSeal = TVF CALtvfLay1AndLay2 sealHole PDIFF q2sealHole
lu1_3_pdiff = pdiffInSeal NOT lu1_3_xmt
pdiffNWnoDNWio = (lu1_3_pdiff AND nwellNotDeepNW) AND IOregion
pdiffNWisoPWio = (lu1_3_pdiff AND nwellDeepNWisoPW) AND IOregion
pdiffNWnonIsoPWio = (lu1_3_pdiff AND nwellDeepNWnoIsoPW) AND IOregion
pdiffNWnoDNW = (lu1_3_pdiff AND nwellNotDeepNW) NOT IOregion
pdiffNWisoPW = (lu1_3_pdiff AND nwellDeepNWisoPW) NOT IOregion
pdiffNWnonIsoPW = (lu1_3_pdiff AND nwellDeepNWnoIsoPW) NOT IOregion
"r_14_lu1.3.1a" {
@ lu1.3.1a: 6 max. distance of pdiffNWnoDNWio area to nTaplicon
q0nTaplicon = SIZE nTaplicon BY 6 INSIDE OF nwell STEP 1
pdiffNWnoDNWio NOT q0nTaplicon
}
"r_15_lu1.3.1b" {
@ lu1.3.1b: 15 max. distance of pdiffNWnoDNW area to nTaplicon
q1nTaplicon = SIZE nTaplicon BY 15 INSIDE OF nwell STEP 1
pdiffNWnoDNW NOT q1nTaplicon
}
"r_16_lu1.3.2a" {
@ lu1.3.2a: 6 max. distance of pdiffNWnonIsoPWio area to nTaplicon
q2nTaplicon = SIZE nTaplicon BY 6 INSIDE OF nwell STEP 1
pdiffNWnonIsoPWio NOT q2nTaplicon
}
"r_17_lu1.3.2b" {
@ lu1.3.2b: 15 max. distance of pdiffNWnonIsoPW area to nTaplicon
q3nTaplicon = SIZE nTaplicon BY 15 INSIDE OF nwell STEP 1
pdiffNWnonIsoPW NOT q3nTaplicon
}
"r_18_lu1.3.3a" {
@ lu1.3.3a: 6 max. distance of pdiffNWisoPWio area to nTaplicon
q4nTaplicon = SIZE nTaplicon BY 6 INSIDE OF nwell STEP 1
pdiffNWisoPWio NOT q4nTaplicon
}
"r_19_lu1.3.3b" {
@ lu1.3.3b: 15 max. distance of pdiffNWisoPW area to nTaplicon
q5nTaplicon = SIZE nTaplicon BY 15 INSIDE OF nwell STEP 1
pdiffNWisoPW NOT q5nTaplicon
}
q3sealHole = COPY 4004
pdiffInExtent = TVF CALtvfLay2OrEmpty sealHole PDIFF q3sealHole
lu1_3_pdiffAll = pdiffInExtent NOT lu1_3_xmt
lu1_3_pdiffTTap = lu1_3_pdiffAll NOT LTDID
lu1_3_pdiffLTap = lu1_3_pdiffAll AND LTDID
pdiffNWnoDNW_TTap = lu1_3_pdiffTTap AND nwellNotDeepNW
pdiffNWisoPW_TTap = lu1_3_pdiffTTap AND nwellDeepNWisoPW
pdiffNWnonIsoPW_TTap = lu1_3_pdiffTTap AND nwellDeepNWnoIsoPW
pdiffNWnoDNW_LTap = lu1_3_pdiffLTap AND nwellNotDeepNW
pdiffNWisoPW_LTap = lu1_3_pdiffLTap AND nwellDeepNWisoPW
pdiffNWnonIsoPW_LTap = lu1_3_pdiffLTap AND nwellDeepNWnoIsoPW
"r_20_lu1.3.1a" {
@ lu1.3.1a: 6 max. distance of pdiffNWnoDNW_TTap area to nTaplicon
q6nTaplicon = SIZE nTaplicon BY 6 INSIDE OF nwell STEP 1
pdiffNWnoDNW_TTap NOT q6nTaplicon
}
"r_21_lu1.3.1b" {
@ lu1.3.1b: 15 max. distance of pdiffNWnoDNW_LTap area to nTaplicon
q7nTaplicon = SIZE nTaplicon BY 15 INSIDE OF nwell STEP 1
pdiffNWnoDNW_LTap NOT q7nTaplicon
}
"r_22_lu1.3.2a" {
@ lu1.3.2a: 6 max. distance of pdiffNWnonIsoPW_TTap area to nTaplicon
q8nTaplicon = SIZE nTaplicon BY 6 INSIDE OF nwell STEP 1
pdiffNWnonIsoPW_TTap NOT q8nTaplicon
}
"r_23_lu1.3.2b" {
@ lu1.3.2b: 15 max. distance of pdiffNWnonIsoPW_LTap area to nTaplicon
q9nTaplicon = SIZE nTaplicon BY 15 INSIDE OF nwell STEP 1
pdiffNWnonIsoPW_LTap NOT q9nTaplicon
}
"r_24_lu1.3.3a" {
@ lu1.3.3a: 6 max. distance of pdiffNWisoPW_TTap area to nTaplicon
q10nTaplicon = SIZE nTaplicon BY 6 INSIDE OF nwell STEP 1
pdiffNWisoPW_TTap NOT q10nTaplicon
}
"r_25_lu1.3.3b" {
@ lu1.3.3b: 15 max. distance of pdiffNWisoPW_LTap area to nTaplicon
q11nTaplicon = SIZE nTaplicon BY 15 INSIDE OF nwell STEP 1
pdiffNWisoPW_LTap NOT q11nTaplicon
}
"r_26_lu1.4" {
@ lu1.4: 50 min. spacing of ioNSDntr & COREID
EXTERNAL ioNSDntr COREID < 50.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_27_lu1.4" {
@ lu1.4: 50 min. spacing of ioPSDntr & COREID
EXTERNAL ioPSDntr COREID < 50.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
/// CALconnectZone started - zoneName was "zone_1"
DISCONNECT
CONNECT nwell NTAP
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT Met3 met3tt
CONNECT Met2 met2tt
CONNECT Met1 met1tt
CONNECT Li1 li1tt
CONNECT NSRCDRN difftt
CONNECT PSRCDRN difftt
CONNECT Li1 li1_pin BY Li1pt
CONNECT Met1 met1_pin BY Met1pt
CONNECT Met2 met2_pin BY Met2pt
CONNECT Met3 met3_pin BY Met3pt
CONNECT switched_intPower_met1 Met1
CONNECT pad Met5
CONNECT probe_pad Met5
CONNECT Met5 Met4 BY Via4
CONNECT Met5 met5tt
CONNECT Met5 met5_pin BY Met5pt
CONNECT Met4 Met3 BY Via3
CONNECT Met4 met4tt
CONNECT Met4 met4_pin BY Met4pt
CONNECT rdl pad BY pmm
CONNECT rdl probe_pad BY pmm
/// CALconnectZone done. zoneName is now zone_2
nSrcDrnExtVcc = NET NSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
pSrcDrnExtVcc = NET PSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
nSrcDrnExtVss = NET NSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
pSrcDrnExtVss = NET PSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
nSrcDrnIntVcc = NET NSRCDRN "vpwr2"
pSrcDrnIntVcc = NET PSRCDRN "vpwr2"
pSrcDrnRegVss = COPY 4005
nSrcDrnRegVss = COPY 4006
shvNTAP = COPY 4007
shvPTAP = COPY 4008
shvNSD = COPY 4009
shvPSD = COPY 4010
shvNTAPvcc = COPY 4011
shvPTAPvcc = COPY 4012
shvNSDvcc = COPY 4013
shvPSDvcc = COPY 4014
dnwSHVsrcDrn = COPY 4015
shvNTAPio = COPY 4016
shvPTAPio = COPY 4017
shvNSDio = COPY 4018
shvPSDio = COPY 4019
probe_padVcc = NET probe_pad "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
probe_padVss = NET probe_pad "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
probe_padVccNSD = NET AREA RATIO NSRCDRN probe_padVcc > 0
probe_padVssNSD = NET AREA RATIO NSRCDRN probe_padVss > 0
probe_padVccPSD = NET AREA RATIO PSRCDRN probe_padVcc > 0
probe_padVssPSD = NET AREA RATIO PSRCDRN probe_padVss > 0
nSrcDrnVcc = (NET NSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2") NOT (nSrcDrnIntVcc OR probe_padVccNSD)
nSrcDrnVss = (NET NSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio") NOT (nSrcDrnRegVss OR probe_padVssNSD)
pSrcDrnVcc = (NET PSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2") NOT (pSrcDrnIntVcc OR probe_padVccPSD)
pSrcDrnVss = (NET PSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio") NOT (pSrcDrnRegVss OR probe_padVssPSD)
s8_esd_xmt = INSIDE CELL diff "s8_esd_signal_50_sym_hv_4k" "s8_esd_signal_50_sym_hv_4k_dnwl_aup1" "s8_esd_signal_50_sym_hv_2k" "s8_esd_signal_40_sym_hv_2k" "s8_esd_signal_23_sym_hv_2k" "s8_esd_signal_30_sym_hv_2k" "s8_esd_signal_50_sym_hv_2k_dnwl_aup1" "s8_esd_signal_50_sym_hv_2k_dnwl_aup1_b" "s8_esd_signal_50_sym_hv_2k_dnwl_aup1_c" "s8_esd_signal_40_sym_hv_2k_dnwl_aup1" "s8_esd_signal_40_sym_hv_2k_dnwl_aup1_b" "s8_esd_signal_40_sym_hv_2k_dnwl_aup1_c" "s8_esd_signal_23_asym_hv_2k_dnwl_aup1" "s8_esd_signal_23_sym_hv_2k_dnwl_aup1" "s8_esd_signal_23_sym_hv_2k_dnwl_aup1_a" "s8_esd_signal_sym_nhvnative" "s8_esd_signal_sym_nhvnative" "s8_esd_pwr2gnd_rc_50_asym_hv_4k" "s8_esd_gnd2gnd_120x2_lv" "s8_esd_gnd2gnd_120x2_lv_isosub" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k_b" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k_b" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k_dnwl" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k_dnwl" "s8_esd_pwr2pwr_50_sym_hv_2k" "s8_esd_pwr2pwr_40_sym_hv_2k" "s8_esd_pwr2pwr_21_sym_hv_2k" "s8_esd_pwr2pwr_40_sym_hv_2k_aup1" "s8_esd_pwr2pwr_40_sym_hv_2k_aup1" "s8_esd_pwr2pwr_50_sym_hv_2k_aup1" "s8_esd_pwr2pwr_50_sym_hv_2k_aup1" "s8_esd_pwr2pwr_40_1p3_1p3_hv_2k" "s8_esd_source_follower" "s8_esd_stdby_pump_cell" "s8_esd_pwr2gnd_rc_50_sym_hv_4k" "s8_esd_pwr2gnd_rc_50_sym_hv_4k_aup1" "s8_esd_pwr2gnd_rc_50_sym_hv_2k" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_revA" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_revB_SouthEastWest" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl_revA" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_revB_south" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl_aup1" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl_aup1" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl_aup" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b_revA" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b_revA" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b_revB_north" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b_revB_north" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_c" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_c_revB_south" "s8_esd_pwr2gnd_rc_40_sym_hv_2k" "s8_esd_pwr2gnd_rc_40_sym_hv_2k_revA" "s8_esd_pwr2gnd_rc_40_sym_hv_2k_revB" "s8_esd_pwr2gnd_rc_40_sym_hv_2k_dnwl_aup" "s8_esd_pwr2gnd_rc_21_sym_hv_2k" "s8_esd_pwr2gnd_rc_21_asym_hv_2k" "s8_esd_pwr2gnd_50_casc_sym_hv_2k" "s8_esd_pwr2gnd_rc_40_asym_lv_4k" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl_aup" "s8_esd_pwr2gnd_rc_40_asym_lv_2k" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_revA" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_revA_InsideCore" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_revB_north" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_revA_west" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl_revA" "s8_esd_pwr2gnd_50_casc_sym_hv_2k_dnwl" "s8_esd_pwr2gnd_50_casc_sym_hv_2k_dnwl_aup1" "s8_esd_pwr2gnd_50_casc_sym_hv_2k_dnwl_aup1" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1_revA" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1_revA" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl_aup1" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl_aup1" "NO_NAME" "mtdr_io_reg_mockup" "s8tee_reg_top" "s8_esd_signal_5_sym_hv_local" "s8_esd_signal_5_sym_hv_local_5term" "s8_esd_signal_5_sym_hv_local_5term_dnwl" "s8_esd_signal_5_sym_lv_local" "s8_esd_localdiode_hv" "s8_esd_localdiode_lv" "s8_esd_res75only" "s8_esd_res75only_small" "s8_esd_res75only_noshorts" "s8_esd_res75only_noshorts_nometal" "s8_esd_res250" "s8_esd_res250only" "s8_esd_res250only_small" "s8_esd_gnd2gnd_120x2_lv" "s8_esd_gnd2gnd_120x2_lv_isosub" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k_b" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k_b" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k_dnwl" "s8_esd_pwr2pwr_40_1p3_1p3_lv_2k_dnwl" "s8_esd_pwr2pwr_21_sym_hv_2k" "s8_esd_pwr2pwr_50_sym_hv_2k" "s8_esd_pwr2pwr_40_sym_hv_2k" "s8_esd_pwr2pwr_50_sym_hv_2k_aup1" "s8_esd_pwr2pwr_50_sym_hv_2k_aup1" "s8_esd_pwr2pwr_40_sym_hv_2k_aup1" "s8_esd_pwr2pwr_40_sym_hv_2k_aup1" "s8_esd_pwr2pwr_40_1p3_1p3_hv_2k" "s8_esd_pwr2gnd_rc_50_sym_hv_4k" "s8_esd_pwr2gnd_rc_50_sym_hv_4k_aup1" "s8_esd_pwr2gnd_rc_50_sym_hv_2k" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_revA" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_revB_SouthEastWest" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl_revA" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_revB_south" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl_aup1" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl_aup1" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl_aup" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b_revA" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b_revA" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b_revB_north" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b_revB_north" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_c" "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_c_revB_south" "s8_esd_pwr2gnd_rc_40_sym_hv_2k" "s8_esd_pwr2gnd_rc_40_sym_hv_2k_revA" "s8_esd_pwr2gnd_rc_40_sym_hv_2k_revB" "s8_esd_pwr2gnd_rc_40_sym_hv_2k_dnwl_aup" "s8_esd_pwr2gnd_rc_21_sym_hv_2k" "s8_esd_pwr2gnd_rc_21_asym_hv_2k" "s8_esd_pwr2gnd_50_casc_sym_hv_2k" "s8_esd_pwr2gnd_rc_40_asym_lv_4k" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl_aup" "s8_esd_pwr2gnd_rc_40_asym_lv_2k" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_revA" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_revA_InsideCore" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_revB_north" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_revA_west" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl_revA" "s8_esd_pwr2gnd_50_casc_sym_hv_2k_dnwl" "s8_esd_pwr2gnd_50_casc_sym_hv_2k_dnwl_aup1" "s8_esd_pwr2gnd_50_casc_sym_hv_2k_dnwl_aup1" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1_revA" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1_revA" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl_aup1" "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl_aup1" "s8_esd_paddiode2gnd_100_hv" "s8_esd_paddiode2gnd_200_hv" "s8_esd_paddiode2gnd_300_hv" "s8_esd_paddiode2gnd_100_dnwl_hv" "s8_esd_paddiode2gnd_200_dnwl_hv" "s8_esd_paddiode2gnd_300_dnwl_hv" "s8_esd_paddiode2pwr_100_hv" "s8_esd_paddiode2pwr_200_hv" "s8_esd_paddiode2pwr_300_hv" "s8_esd_vcseldrv_casc_nmos" "s8_esd_vcseldrv_casc_nmos" "s8_esd_vcseldrv_casc_nmos" "s8_esd_vcseldrv_casc_nmos_no_power" "s8_esd_vcseldrv_casc_nmos_no_power" "s8_esd_vcseldrv_casc_nmos_no_power" "s8_esd_vcseldrv_casc_pmos" "s8_esd_vcseldrv_casc_pmos" "s8_esd_vcseldrv_casc_pmos" "s8_esd_vcseldrv_casc_pmos_no_power" "s8_esd_vcseldrv_casc_pmos_no_power" "s8_esd_vcseldrv_casc_pmos_no_power" "s8psoc3io_sio_pudrvr_reg_pu_natives" "s8psoc3io_sio_pudrvr_reg_pu_natives" "s8ppscio_sio_pudrvr_reg_pu_natives" "s8ppscio_sio_pudrvr_reg_pu_natives"
lu_1_5_xmtCells = EXTENT CELL "s8usbpd_300msw_nsw" "s8fpiom0s8_top_lvc_b2b_wopad" "s8fpiom0s8_top_hvclamp_wopad" "s8usbpd_sbu_sw_top" "s8usbpd_vddd_sw_nsw" "s8anatk_hvldo_top_gating_aup" "s8srsscore_vccd_switch" "s8subpdv2_vddd_sw_nsw" "s8usbpdv2_dpdm_sw_2X2_nch" "s8usbpdv2_vddd_sw_top" "mmiolib_top_hvclamp_wopad" "mmiolib_top_lvc_b2b_wopad" "mmiolib_top_lvclamp_wopad" ORIGINAL
lu_1_5_xmt = s8_esd_xmt OR
(ESDID OR lu_1_5_xmtCells)
ndiffVcc = nSrcDrnVcc NOT lu_1_5_xmt
ndiffVss = nSrcDrnVss NOT lu_1_5_xmt
pdiffVcc = pSrcDrnVcc NOT lu_1_5_xmt
pdiffVss = pSrcDrnVss NOT lu_1_5_xmt
ndiffVccOnPsub = ndiffVcc NOT dnwell
ndiffVssOnPsub = ndiffVss NOT dnwell
ndiffVccOnPwell = ndiffVcc AND dnwell
ndiffVssOnPwell = ndiffVss AND dnwell
pdiffVccnonGateEdge = pdiffVcc NOT COINCIDENT EDGE gate
pdiffVssnonGateEdge = pdiffVss NOT COINCIDENT EDGE gate
ndiffVccnonGateEdgeOnPsub = ndiffVccOnPsub NOT COINCIDENT EDGE gate
ndiffVssnonGateEdgeOnPsub = ndiffVssOnPsub NOT COINCIDENT EDGE gate
ndiffVccnonGateEdgeOnPwell = ndiffVccOnPwell NOT COINCIDENT EDGE gate
ndiffVssnonGateEdgeOnPwell = ndiffVssOnPwell NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5 = INTERACT (EXTERNAL pdiffVccnonGateEdge pdiffVssnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffVccnonGateEdge pdiffVssnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiffVccOnPsub = INTERACT (EXTERNAL ndiffVccnonGateEdgeOnPsub ndiffVssnonGateEdgeOnPsub < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffVccnonGateEdgeOnPsub ndiffVssnonGateEdgeOnPsub < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
InvalidNdiffVccOnPwell = INTERACT (EXTERNAL ndiffVccnonGateEdgeOnPwell ndiffVssnonGateEdgeOnPwell < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffVccnonGateEdgeOnPwell ndiffVssnonGateEdgeOnPwell < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"k_0_s8_esd_xmt" {
@ keep: s8_esd_xmt - s8_esd_xmt
@ Diff inside cells in the s8_esd library listed in Appendix A
COPY s8_esd_xmt
}
"r_28_lu1.5" {
@ lu1.5: 3.00 Min space between vcc pad connected pdiff and vss pad connected pdiff within common nwell or dnwell
COPY InvalidPdiff_lu_1_5
}
"r_29_lu1.5" {
@ lu1.5: 3.00 Min space between vcc pad connected ndiff and vss pad connected ndiff within common Psub
COPY InvalidNdiffVccOnPsub
}
"r_30_lu1.5" {
@ lu1.5: 3.00 Min space between vcc pad connected ndiff and vss pad connected ndiff within common Pwell
COPY InvalidNdiffVccOnPwell
}
nSrcDrnExtIo = NET NSRCDRN "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
pSrcDrnExtIo = NET PSRCDRN "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
probe_padIO = NET probe_pad "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
probe_padIOnsd = NET AREA RATIO NSRCDRN probe_padIO > 0
probe_padIOpsd = NET AREA RATIO PSRCDRN probe_padIO > 0
nSrcDrnIo = (ioNSDntr OR nSrcDrnExtIo) NOT probe_padIOnsd
pSrcDrnIo = (ioPSDntr OR pSrcDrnExtIo) NOT probe_padIOpsd
ndiffIo = nSrcDrnIo NOT lu_1_5_xmt
pdiffIo = pSrcDrnIo NOT lu_1_5_xmt
ndiffIoOnPsub = ndiffIo NOT dnwell
ndiffIoOnPwell = ndiffIo AND dnwell
ndiffIoOnPsubnonGateEdge = ndiffIoOnPsub NOT COINCIDENT EDGE gate
ndiffIoOnPwellnonGateEdge = ndiffIoOnPwell NOT COINCIDENT EDGE gate
pdiffIononGateEdge = pdiffIo NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vcc = INTERACT (EXTERNAL pdiffVccnonGateEdge pdiffIononGateEdge < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffVccnonGateEdge pdiffIononGateEdge < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidPdiff_lu_1_5_vss = INTERACT (EXTERNAL pdiffVssnonGateEdge pdiffIononGateEdge < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffVssnonGateEdge pdiffIononGateEdge < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvNdiffVcctoIo_Psub = INTERACT (EXTERNAL ndiffVccnonGateEdgeOnPsub ndiffIoOnPsubnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffVccnonGateEdgeOnPsub ndiffIoOnPsubnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
InvNdiffVsstoIo_Psub = INTERACT (EXTERNAL ndiffVssnonGateEdgeOnPsub ndiffIoOnPsubnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffVssnonGateEdgeOnPsub ndiffIoOnPsubnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
InvNdiffVcctoIo_Pwell = INTERACT (EXTERNAL ndiffVccnonGateEdgeOnPwell ndiffIoOnPwellnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffVccnonGateEdgeOnPwell ndiffIoOnPwellnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
InvNdiffVsstoIo_Pwell = INTERACT (EXTERNAL ndiffVssnonGateEdgeOnPwell ndiffIoOnPwellnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffVssnonGateEdgeOnPwell ndiffIoOnPwellnonGateEdge < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_31_lu1.5" {
@ lu1.5: 3.00 Min space between vcc pdiff to IO pdiff within common nwell or dnwell
COPY InvalidPdiff_lu_1_5_vcc
}
"r_32_lu1.5" {
@ lu1.5: 3.00 Min space between vss pdiff to IO pdiff within common nwell or dnwell
COPY InvalidPdiff_lu_1_5_vss
}
"r_33_lu1.5" {
@ lu1.5: 3.00 Min space between vcc ndiff to IO ndiff within a common Psub
COPY InvNdiffVcctoIo_Psub
}
"r_34_lu1.5" {
@ lu1.5: 3.00 Min space between vss ndiff to IO ndiff within a common Psub
COPY InvNdiffVsstoIo_Psub
}
"r_35_lu1.5" {
@ lu1.5: 3.00 Min space between vcc ndiff to IO ndiff within a common Pwell
COPY InvNdiffVcctoIo_Pwell
}
"r_36_lu1.5" {
@ lu1.5: 3.00 Min space between vss ndiff to IO ndiff within a common Pwell
COPY InvNdiffVsstoIo_Pwell
}
/// CALconnectZone started - zoneName was "zone_2"
CONNECT ndiffVcc NSRCDRN
CONNECT ndiffVss NSRCDRN
CONNECT pdiffVcc PSRCDRN
CONNECT pdiffVss PSRCDRN
CONNECT ndiffIo NSRCDRN
CONNECT pdiffIo PSRCDRN
CONNECT NSDsigPad NSRCDRN
CONNECT PSDsigPad PSRCDRN
CONNECT NSDsigPadNtr NSRCDRN
CONNECT PSDsigPadNtr PSRCDRN
CONNECT ntapRing NTAP
CONNECT ptapRing PTAP
/// CALconnectZone done. zoneName is now zone_3
ndiffSameNetVcc_vpwr = NET ndiffVcc "vpwr"
ndiffDiffNetVcc_vpwr = ndiffVcc NOT ndiffSameNetVcc_vpwr
pdiffSameNetVcc_vpwr = NET pdiffVcc "vpwr"
pdiffDiffNetVcc_vpwr = pdiffVcc NOT pdiffSameNetVcc_vpwr
ndiffSameNetVccnonGateEdge_vpwr = ndiffSameNetVcc_vpwr NOT COINCIDENT EDGE gate
ndiffDiffNetVccnonGateEdge_vpwr = ndiffDiffNetVcc_vpwr NOT COINCIDENT EDGE gate
pdiffSameNetVccnonGateEdge_vpwr = pdiffSameNetVcc_vpwr NOT COINCIDENT EDGE gate
pdiffDiffNetVccnonGateEdge_vpwr = pdiffDiffNetVcc_vpwr NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vcc_only_vpwr = INTERACT (EXTERNAL pdiffSameNetVccnonGateEdge_vpwr pdiffDiffNetVccnonGateEdge_vpwr < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVccnonGateEdge_vpwr pdiffDiffNetVccnonGateEdge_vpwr < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vcc_only_vpwr = INTERACT (EXTERNAL ndiffSameNetVccnonGateEdge_vpwr ndiffDiffNetVccnonGateEdge_vpwr < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVccnonGateEdge_vpwr ndiffDiffNetVccnonGateEdge_vpwr < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_37_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vcc pads
COPY InvalidNdiff_lu_1_5_vcc_only_vpwr
}
"r_38_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vcc pads
COPY InvalidPdiff_lu_1_5_vcc_only_vpwr
}
ndiffSameNetVcc_vpwr1 = NET ndiffVcc "vpwr1"
ndiffDiffNetVcc_vpwr1 = ndiffVcc NOT ndiffSameNetVcc_vpwr1
pdiffSameNetVcc_vpwr1 = NET pdiffVcc "vpwr1"
pdiffDiffNetVcc_vpwr1 = pdiffVcc NOT pdiffSameNetVcc_vpwr1
ndiffSameNetVccnonGateEdge_vpwr1 = ndiffSameNetVcc_vpwr1 NOT COINCIDENT EDGE gate
ndiffDiffNetVccnonGateEdge_vpwr1 = ndiffDiffNetVcc_vpwr1 NOT COINCIDENT EDGE gate
pdiffSameNetVccnonGateEdge_vpwr1 = pdiffSameNetVcc_vpwr1 NOT COINCIDENT EDGE gate
pdiffDiffNetVccnonGateEdge_vpwr1 = pdiffDiffNetVcc_vpwr1 NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vcc_only_vpwr1 = INTERACT (EXTERNAL pdiffSameNetVccnonGateEdge_vpwr1 pdiffDiffNetVccnonGateEdge_vpwr1 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVccnonGateEdge_vpwr1 pdiffDiffNetVccnonGateEdge_vpwr1 < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vcc_only_vpwr1 = INTERACT (EXTERNAL ndiffSameNetVccnonGateEdge_vpwr1 ndiffDiffNetVccnonGateEdge_vpwr1 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVccnonGateEdge_vpwr1 ndiffDiffNetVccnonGateEdge_vpwr1 < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_39_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vcc pads
COPY InvalidNdiff_lu_1_5_vcc_only_vpwr1
}
"r_40_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vcc pads
COPY InvalidPdiff_lu_1_5_vcc_only_vpwr1
}
ndiffSameNetVcc_vpwr3 = NET ndiffVcc "vpwr3"
ndiffDiffNetVcc_vpwr3 = ndiffVcc NOT ndiffSameNetVcc_vpwr3
pdiffSameNetVcc_vpwr3 = NET pdiffVcc "vpwr3"
pdiffDiffNetVcc_vpwr3 = pdiffVcc NOT pdiffSameNetVcc_vpwr3
ndiffSameNetVccnonGateEdge_vpwr3 = ndiffSameNetVcc_vpwr3 NOT COINCIDENT EDGE gate
ndiffDiffNetVccnonGateEdge_vpwr3 = ndiffDiffNetVcc_vpwr3 NOT COINCIDENT EDGE gate
pdiffSameNetVccnonGateEdge_vpwr3 = pdiffSameNetVcc_vpwr3 NOT COINCIDENT EDGE gate
pdiffDiffNetVccnonGateEdge_vpwr3 = pdiffDiffNetVcc_vpwr3 NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vcc_only_vpwr3 = INTERACT (EXTERNAL pdiffSameNetVccnonGateEdge_vpwr3 pdiffDiffNetVccnonGateEdge_vpwr3 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVccnonGateEdge_vpwr3 pdiffDiffNetVccnonGateEdge_vpwr3 < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vcc_only_vpwr3 = INTERACT (EXTERNAL ndiffSameNetVccnonGateEdge_vpwr3 ndiffDiffNetVccnonGateEdge_vpwr3 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVccnonGateEdge_vpwr3 ndiffDiffNetVccnonGateEdge_vpwr3 < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_41_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vcc pads
COPY InvalidNdiff_lu_1_5_vcc_only_vpwr3
}
"r_42_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vcc pads
COPY InvalidPdiff_lu_1_5_vcc_only_vpwr3
}
ndiffSameNetVcc_vpwr_prb = NET ndiffVcc "vpwr_prb"
ndiffDiffNetVcc_vpwr_prb = ndiffVcc NOT ndiffSameNetVcc_vpwr_prb
pdiffSameNetVcc_vpwr_prb = NET pdiffVcc "vpwr_prb"
pdiffDiffNetVcc_vpwr_prb = pdiffVcc NOT pdiffSameNetVcc_vpwr_prb
ndiffSameNetVccnonGateEdge_vpwr_prb = ndiffSameNetVcc_vpwr_prb NOT COINCIDENT EDGE gate
ndiffDiffNetVccnonGateEdge_vpwr_prb = ndiffDiffNetVcc_vpwr_prb NOT COINCIDENT EDGE gate
pdiffSameNetVccnonGateEdge_vpwr_prb = pdiffSameNetVcc_vpwr_prb NOT COINCIDENT EDGE gate
pdiffDiffNetVccnonGateEdge_vpwr_prb = pdiffDiffNetVcc_vpwr_prb NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vcc_only_vpwr_prb = INTERACT (EXTERNAL pdiffSameNetVccnonGateEdge_vpwr_prb pdiffDiffNetVccnonGateEdge_vpwr_prb < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVccnonGateEdge_vpwr_prb pdiffDiffNetVccnonGateEdge_vpwr_prb < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vcc_only_vpwr_prb = INTERACT (EXTERNAL ndiffSameNetVccnonGateEdge_vpwr_prb ndiffDiffNetVccnonGateEdge_vpwr_prb < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVccnonGateEdge_vpwr_prb ndiffDiffNetVccnonGateEdge_vpwr_prb < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_43_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vcc pads
COPY InvalidNdiff_lu_1_5_vcc_only_vpwr_prb
}
"r_44_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vcc pads
COPY InvalidPdiff_lu_1_5_vcc_only_vpwr_prb
}
ndiffSameNetVcc_vccio = NET ndiffVcc "vccio"
ndiffDiffNetVcc_vccio = ndiffVcc NOT ndiffSameNetVcc_vccio
pdiffSameNetVcc_vccio = NET pdiffVcc "vccio"
pdiffDiffNetVcc_vccio = pdiffVcc NOT pdiffSameNetVcc_vccio
ndiffSameNetVccnonGateEdge_vccio = ndiffSameNetVcc_vccio NOT COINCIDENT EDGE gate
ndiffDiffNetVccnonGateEdge_vccio = ndiffDiffNetVcc_vccio NOT COINCIDENT EDGE gate
pdiffSameNetVccnonGateEdge_vccio = pdiffSameNetVcc_vccio NOT COINCIDENT EDGE gate
pdiffDiffNetVccnonGateEdge_vccio = pdiffDiffNetVcc_vccio NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vcc_only_vccio = INTERACT (EXTERNAL pdiffSameNetVccnonGateEdge_vccio pdiffDiffNetVccnonGateEdge_vccio < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVccnonGateEdge_vccio pdiffDiffNetVccnonGateEdge_vccio < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vcc_only_vccio = INTERACT (EXTERNAL ndiffSameNetVccnonGateEdge_vccio ndiffDiffNetVccnonGateEdge_vccio < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVccnonGateEdge_vccio ndiffDiffNetVccnonGateEdge_vccio < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_45_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vcc pads
COPY InvalidNdiff_lu_1_5_vcc_only_vccio
}
"r_46_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vcc pads
COPY InvalidPdiff_lu_1_5_vcc_only_vccio
}
ndiffSameNetVcc_vpwr2 = NET ndiffVcc "vpwr2"
ndiffDiffNetVcc_vpwr2 = ndiffVcc NOT ndiffSameNetVcc_vpwr2
pdiffSameNetVcc_vpwr2 = NET pdiffVcc "vpwr2"
pdiffDiffNetVcc_vpwr2 = pdiffVcc NOT pdiffSameNetVcc_vpwr2
ndiffSameNetVccnonGateEdge_vpwr2 = ndiffSameNetVcc_vpwr2 NOT COINCIDENT EDGE gate
ndiffDiffNetVccnonGateEdge_vpwr2 = ndiffDiffNetVcc_vpwr2 NOT COINCIDENT EDGE gate
pdiffSameNetVccnonGateEdge_vpwr2 = pdiffSameNetVcc_vpwr2 NOT COINCIDENT EDGE gate
pdiffDiffNetVccnonGateEdge_vpwr2 = pdiffDiffNetVcc_vpwr2 NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vcc_only_vpwr2 = INTERACT (EXTERNAL pdiffSameNetVccnonGateEdge_vpwr2 pdiffDiffNetVccnonGateEdge_vpwr2 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVccnonGateEdge_vpwr2 pdiffDiffNetVccnonGateEdge_vpwr2 < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vcc_only_vpwr2 = INTERACT (EXTERNAL ndiffSameNetVccnonGateEdge_vpwr2 ndiffDiffNetVccnonGateEdge_vpwr2 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVccnonGateEdge_vpwr2 ndiffDiffNetVccnonGateEdge_vpwr2 < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_47_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vcc pads
COPY InvalidNdiff_lu_1_5_vcc_only_vpwr2
}
"r_48_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vcc pads
COPY InvalidPdiff_lu_1_5_vcc_only_vpwr2
}
ndiffSameNetVss_vgnd = NET ndiffVss "vgnd"
ndiffDiffNetVss_vgnd = ndiffVss NOT ndiffSameNetVss_vgnd
pdiffSameNetVss_vgnd = NET pdiffVss "vgnd"
pdiffDiffNetVss_vgnd = pdiffVss NOT pdiffSameNetVss_vgnd
ndiffSameNetVssnonGateEdge_vgnd = ndiffSameNetVss_vgnd NOT COINCIDENT EDGE gate
ndiffDiffNetVssnonGateEdge_vgnd = ndiffDiffNetVss_vgnd NOT COINCIDENT EDGE gate
pdiffSameNetVssnonGateEdge_vgnd = pdiffSameNetVss_vgnd NOT COINCIDENT EDGE gate
pdiffDiffNetVssnonGateEdge_vgnd = pdiffDiffNetVss_vgnd NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vss_only_vgnd = INTERACT (EXTERNAL pdiffSameNetVssnonGateEdge_vgnd pdiffDiffNetVssnonGateEdge_vgnd < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVssnonGateEdge_vgnd pdiffDiffNetVssnonGateEdge_vgnd < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vss_only_vgnd = INTERACT (EXTERNAL ndiffSameNetVssnonGateEdge_vgnd ndiffDiffNetVssnonGateEdge_vgnd < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVssnonGateEdge_vgnd ndiffDiffNetVssnonGateEdge_vgnd < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_49_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vss pads
COPY InvalidNdiff_lu_1_5_vss_only_vgnd
}
"r_50_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vss pads
COPY InvalidPdiff_lu_1_5_vss_only_vgnd
}
ndiffSameNetVss_vgnd1 = NET ndiffVss "vgnd1"
ndiffDiffNetVss_vgnd1 = ndiffVss NOT ndiffSameNetVss_vgnd1
pdiffSameNetVss_vgnd1 = NET pdiffVss "vgnd1"
pdiffDiffNetVss_vgnd1 = pdiffVss NOT pdiffSameNetVss_vgnd1
ndiffSameNetVssnonGateEdge_vgnd1 = ndiffSameNetVss_vgnd1 NOT COINCIDENT EDGE gate
ndiffDiffNetVssnonGateEdge_vgnd1 = ndiffDiffNetVss_vgnd1 NOT COINCIDENT EDGE gate
pdiffSameNetVssnonGateEdge_vgnd1 = pdiffSameNetVss_vgnd1 NOT COINCIDENT EDGE gate
pdiffDiffNetVssnonGateEdge_vgnd1 = pdiffDiffNetVss_vgnd1 NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vss_only_vgnd1 = INTERACT (EXTERNAL pdiffSameNetVssnonGateEdge_vgnd1 pdiffDiffNetVssnonGateEdge_vgnd1 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVssnonGateEdge_vgnd1 pdiffDiffNetVssnonGateEdge_vgnd1 < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vss_only_vgnd1 = INTERACT (EXTERNAL ndiffSameNetVssnonGateEdge_vgnd1 ndiffDiffNetVssnonGateEdge_vgnd1 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVssnonGateEdge_vgnd1 ndiffDiffNetVssnonGateEdge_vgnd1 < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_51_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vss pads
COPY InvalidNdiff_lu_1_5_vss_only_vgnd1
}
"r_52_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vss pads
COPY InvalidPdiff_lu_1_5_vss_only_vgnd1
}
ndiffSameNetVss_vgnd3 = NET ndiffVss "vgnd3"
ndiffDiffNetVss_vgnd3 = ndiffVss NOT ndiffSameNetVss_vgnd3
pdiffSameNetVss_vgnd3 = NET pdiffVss "vgnd3"
pdiffDiffNetVss_vgnd3 = pdiffVss NOT pdiffSameNetVss_vgnd3
ndiffSameNetVssnonGateEdge_vgnd3 = ndiffSameNetVss_vgnd3 NOT COINCIDENT EDGE gate
ndiffDiffNetVssnonGateEdge_vgnd3 = ndiffDiffNetVss_vgnd3 NOT COINCIDENT EDGE gate
pdiffSameNetVssnonGateEdge_vgnd3 = pdiffSameNetVss_vgnd3 NOT COINCIDENT EDGE gate
pdiffDiffNetVssnonGateEdge_vgnd3 = pdiffDiffNetVss_vgnd3 NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vss_only_vgnd3 = INTERACT (EXTERNAL pdiffSameNetVssnonGateEdge_vgnd3 pdiffDiffNetVssnonGateEdge_vgnd3 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVssnonGateEdge_vgnd3 pdiffDiffNetVssnonGateEdge_vgnd3 < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vss_only_vgnd3 = INTERACT (EXTERNAL ndiffSameNetVssnonGateEdge_vgnd3 ndiffDiffNetVssnonGateEdge_vgnd3 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVssnonGateEdge_vgnd3 ndiffDiffNetVssnonGateEdge_vgnd3 < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_53_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vss pads
COPY InvalidNdiff_lu_1_5_vss_only_vgnd3
}
"r_54_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vss pads
COPY InvalidPdiff_lu_1_5_vss_only_vgnd3
}
ndiffSameNetVss_vgnd_prb = NET ndiffVss "vgnd_prb"
ndiffDiffNetVss_vgnd_prb = ndiffVss NOT ndiffSameNetVss_vgnd_prb
pdiffSameNetVss_vgnd_prb = NET pdiffVss "vgnd_prb"
pdiffDiffNetVss_vgnd_prb = pdiffVss NOT pdiffSameNetVss_vgnd_prb
ndiffSameNetVssnonGateEdge_vgnd_prb = ndiffSameNetVss_vgnd_prb NOT COINCIDENT EDGE gate
ndiffDiffNetVssnonGateEdge_vgnd_prb = ndiffDiffNetVss_vgnd_prb NOT COINCIDENT EDGE gate
pdiffSameNetVssnonGateEdge_vgnd_prb = pdiffSameNetVss_vgnd_prb NOT COINCIDENT EDGE gate
pdiffDiffNetVssnonGateEdge_vgnd_prb = pdiffDiffNetVss_vgnd_prb NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vss_only_vgnd_prb = INTERACT (EXTERNAL pdiffSameNetVssnonGateEdge_vgnd_prb pdiffDiffNetVssnonGateEdge_vgnd_prb < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVssnonGateEdge_vgnd_prb pdiffDiffNetVssnonGateEdge_vgnd_prb < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vss_only_vgnd_prb = INTERACT (EXTERNAL ndiffSameNetVssnonGateEdge_vgnd_prb ndiffDiffNetVssnonGateEdge_vgnd_prb < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVssnonGateEdge_vgnd_prb ndiffDiffNetVssnonGateEdge_vgnd_prb < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_55_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vss pads
COPY InvalidNdiff_lu_1_5_vss_only_vgnd_prb
}
"r_56_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vss pads
COPY InvalidPdiff_lu_1_5_vss_only_vgnd_prb
}
ndiffSameNetVss_vgnd_pad = NET ndiffVss "vgnd_pad"
ndiffDiffNetVss_vgnd_pad = ndiffVss NOT ndiffSameNetVss_vgnd_pad
pdiffSameNetVss_vgnd_pad = NET pdiffVss "vgnd_pad"
pdiffDiffNetVss_vgnd_pad = pdiffVss NOT pdiffSameNetVss_vgnd_pad
ndiffSameNetVssnonGateEdge_vgnd_pad = ndiffSameNetVss_vgnd_pad NOT COINCIDENT EDGE gate
ndiffDiffNetVssnonGateEdge_vgnd_pad = ndiffDiffNetVss_vgnd_pad NOT COINCIDENT EDGE gate
pdiffSameNetVssnonGateEdge_vgnd_pad = pdiffSameNetVss_vgnd_pad NOT COINCIDENT EDGE gate
pdiffDiffNetVssnonGateEdge_vgnd_pad = pdiffDiffNetVss_vgnd_pad NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vss_only_vgnd_pad = INTERACT (EXTERNAL pdiffSameNetVssnonGateEdge_vgnd_pad pdiffDiffNetVssnonGateEdge_vgnd_pad < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVssnonGateEdge_vgnd_pad pdiffDiffNetVssnonGateEdge_vgnd_pad < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vss_only_vgnd_pad = INTERACT (EXTERNAL ndiffSameNetVssnonGateEdge_vgnd_pad ndiffDiffNetVssnonGateEdge_vgnd_pad < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVssnonGateEdge_vgnd_pad ndiffDiffNetVssnonGateEdge_vgnd_pad < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_57_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vss pads
COPY InvalidNdiff_lu_1_5_vss_only_vgnd_pad
}
"r_58_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vss pads
COPY InvalidPdiff_lu_1_5_vss_only_vgnd_pad
}
ndiffSameNetVss_vssio = NET ndiffVss "vssio"
ndiffDiffNetVss_vssio = ndiffVss NOT ndiffSameNetVss_vssio
pdiffSameNetVss_vssio = NET pdiffVss "vssio"
pdiffDiffNetVss_vssio = pdiffVss NOT pdiffSameNetVss_vssio
ndiffSameNetVssnonGateEdge_vssio = ndiffSameNetVss_vssio NOT COINCIDENT EDGE gate
ndiffDiffNetVssnonGateEdge_vssio = ndiffDiffNetVss_vssio NOT COINCIDENT EDGE gate
pdiffSameNetVssnonGateEdge_vssio = pdiffSameNetVss_vssio NOT COINCIDENT EDGE gate
pdiffDiffNetVssnonGateEdge_vssio = pdiffDiffNetVss_vssio NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_vss_only_vssio = INTERACT (EXTERNAL pdiffSameNetVssnonGateEdge_vssio pdiffDiffNetVssnonGateEdge_vssio < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetVssnonGateEdge_vssio pdiffDiffNetVssnonGateEdge_vssio < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_vss_only_vssio = INTERACT (EXTERNAL ndiffSameNetVssnonGateEdge_vssio ndiffDiffNetVssnonGateEdge_vssio < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetVssnonGateEdge_vssio ndiffDiffNetVssnonGateEdge_vssio < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_59_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different vss pads
COPY InvalidNdiff_lu_1_5_vss_only_vssio
}
"r_60_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different vss pads
COPY InvalidPdiff_lu_1_5_vss_only_vssio
}
ndiffSameNetIo_io = NET ndiffIo "io"
ndiffDiffNetIo_io = ndiffIo NOT ndiffSameNetIo_io
pdiffSameNetIo_io = NET pdiffIo "io"
pdiffDiffNetIo_io = pdiffIo NOT pdiffSameNetIo_io
ndiffSameNetIononGateEdge_io = ndiffSameNetIo_io NOT COINCIDENT EDGE gate
ndiffDiffNetIononGateEdge_io = ndiffDiffNetIo_io NOT COINCIDENT EDGE gate
pdiffSameNetIononGateEdge_io = pdiffSameNetIo_io NOT COINCIDENT EDGE gate
pdiffDiffNetIononGateEdge_io = pdiffDiffNetIo_io NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_io_only_io = INTERACT (EXTERNAL pdiffSameNetIononGateEdge_io pdiffDiffNetIononGateEdge_io < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetIononGateEdge_io pdiffDiffNetIononGateEdge_io < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_io_only_io = INTERACT (EXTERNAL ndiffSameNetIononGateEdge_io ndiffDiffNetIononGateEdge_io < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetIononGateEdge_io ndiffDiffNetIononGateEdge_io < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_61_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY InvalidPdiff_lu_1_5_io_only_io
}
"r_62_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY InvalidNdiff_lu_1_5_io_only_io
}
ndiffSameNetIo_io1 = NET ndiffIo "io1"
ndiffDiffNetIo_io1 = ndiffIo NOT ndiffSameNetIo_io1
pdiffSameNetIo_io1 = NET pdiffIo "io1"
pdiffDiffNetIo_io1 = pdiffIo NOT pdiffSameNetIo_io1
ndiffSameNetIononGateEdge_io1 = ndiffSameNetIo_io1 NOT COINCIDENT EDGE gate
ndiffDiffNetIononGateEdge_io1 = ndiffDiffNetIo_io1 NOT COINCIDENT EDGE gate
pdiffSameNetIononGateEdge_io1 = pdiffSameNetIo_io1 NOT COINCIDENT EDGE gate
pdiffDiffNetIononGateEdge_io1 = pdiffDiffNetIo_io1 NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_io_only_io1 = INTERACT (EXTERNAL pdiffSameNetIononGateEdge_io1 pdiffDiffNetIononGateEdge_io1 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetIononGateEdge_io1 pdiffDiffNetIononGateEdge_io1 < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_io_only_io1 = INTERACT (EXTERNAL ndiffSameNetIononGateEdge_io1 ndiffDiffNetIononGateEdge_io1 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetIononGateEdge_io1 ndiffDiffNetIononGateEdge_io1 < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_63_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY InvalidPdiff_lu_1_5_io_only_io1
}
"r_64_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY InvalidNdiff_lu_1_5_io_only_io1
}
ndiffSameNetIo_io2 = NET ndiffIo "io2"
ndiffDiffNetIo_io2 = ndiffIo NOT ndiffSameNetIo_io2
pdiffSameNetIo_io2 = NET pdiffIo "io2"
pdiffDiffNetIo_io2 = pdiffIo NOT pdiffSameNetIo_io2
ndiffSameNetIononGateEdge_io2 = ndiffSameNetIo_io2 NOT COINCIDENT EDGE gate
ndiffDiffNetIononGateEdge_io2 = ndiffDiffNetIo_io2 NOT COINCIDENT EDGE gate
pdiffSameNetIononGateEdge_io2 = pdiffSameNetIo_io2 NOT COINCIDENT EDGE gate
pdiffDiffNetIononGateEdge_io2 = pdiffDiffNetIo_io2 NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_io_only_io2 = INTERACT (EXTERNAL pdiffSameNetIononGateEdge_io2 pdiffDiffNetIononGateEdge_io2 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetIononGateEdge_io2 pdiffDiffNetIononGateEdge_io2 < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_io_only_io2 = INTERACT (EXTERNAL ndiffSameNetIononGateEdge_io2 ndiffDiffNetIononGateEdge_io2 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetIononGateEdge_io2 ndiffDiffNetIononGateEdge_io2 < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_65_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY InvalidPdiff_lu_1_5_io_only_io2
}
"r_66_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY InvalidNdiff_lu_1_5_io_only_io2
}
ndiffSameNetIo_io4 = NET ndiffIo "io4"
ndiffDiffNetIo_io4 = ndiffIo NOT ndiffSameNetIo_io4
pdiffSameNetIo_io4 = NET pdiffIo "io4"
pdiffDiffNetIo_io4 = pdiffIo NOT pdiffSameNetIo_io4
ndiffSameNetIononGateEdge_io4 = ndiffSameNetIo_io4 NOT COINCIDENT EDGE gate
ndiffDiffNetIononGateEdge_io4 = ndiffDiffNetIo_io4 NOT COINCIDENT EDGE gate
pdiffSameNetIononGateEdge_io4 = pdiffSameNetIo_io4 NOT COINCIDENT EDGE gate
pdiffDiffNetIononGateEdge_io4 = pdiffDiffNetIo_io4 NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_io_only_io4 = INTERACT (EXTERNAL pdiffSameNetIononGateEdge_io4 pdiffDiffNetIononGateEdge_io4 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetIononGateEdge_io4 pdiffDiffNetIononGateEdge_io4 < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_io_only_io4 = INTERACT (EXTERNAL ndiffSameNetIononGateEdge_io4 ndiffDiffNetIononGateEdge_io4 < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetIononGateEdge_io4 ndiffDiffNetIononGateEdge_io4 < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_67_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY InvalidPdiff_lu_1_5_io_only_io4
}
"r_68_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY InvalidNdiff_lu_1_5_io_only_io4
}
ndiffSameNetIo_io_prb = NET ndiffIo "io_prb"
ndiffDiffNetIo_io_prb = ndiffIo NOT ndiffSameNetIo_io_prb
pdiffSameNetIo_io_prb = NET pdiffIo "io_prb"
pdiffDiffNetIo_io_prb = pdiffIo NOT pdiffSameNetIo_io_prb
ndiffSameNetIononGateEdge_io_prb = ndiffSameNetIo_io_prb NOT COINCIDENT EDGE gate
ndiffDiffNetIononGateEdge_io_prb = ndiffDiffNetIo_io_prb NOT COINCIDENT EDGE gate
pdiffSameNetIononGateEdge_io_prb = pdiffSameNetIo_io_prb NOT COINCIDENT EDGE gate
pdiffDiffNetIononGateEdge_io_prb = pdiffDiffNetIo_io_prb NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_io_only_io_prb = INTERACT (EXTERNAL pdiffSameNetIononGateEdge_io_prb pdiffDiffNetIononGateEdge_io_prb < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetIononGateEdge_io_prb pdiffDiffNetIononGateEdge_io_prb < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_io_only_io_prb = INTERACT (EXTERNAL ndiffSameNetIononGateEdge_io_prb ndiffDiffNetIononGateEdge_io_prb < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetIononGateEdge_io_prb ndiffDiffNetIononGateEdge_io_prb < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_69_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY InvalidPdiff_lu_1_5_io_only_io_prb
}
"r_70_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY InvalidNdiff_lu_1_5_io_only_io_prb
}
ndiffSameNetIo_pad5v = NET ndiffIo "pad5v"
ndiffDiffNetIo_pad5v = ndiffIo NOT ndiffSameNetIo_pad5v
pdiffSameNetIo_pad5v = NET pdiffIo "pad5v"
pdiffDiffNetIo_pad5v = pdiffIo NOT pdiffSameNetIo_pad5v
ndiffSameNetIononGateEdge_pad5v = ndiffSameNetIo_pad5v NOT COINCIDENT EDGE gate
ndiffDiffNetIononGateEdge_pad5v = ndiffDiffNetIo_pad5v NOT COINCIDENT EDGE gate
pdiffSameNetIononGateEdge_pad5v = pdiffSameNetIo_pad5v NOT COINCIDENT EDGE gate
pdiffDiffNetIononGateEdge_pad5v = pdiffDiffNetIo_pad5v NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_io_only_pad5v = INTERACT (EXTERNAL pdiffSameNetIononGateEdge_pad5v pdiffDiffNetIononGateEdge_pad5v < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetIononGateEdge_pad5v pdiffDiffNetIononGateEdge_pad5v < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_io_only_pad5v = INTERACT (EXTERNAL ndiffSameNetIononGateEdge_pad5v ndiffDiffNetIononGateEdge_pad5v < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetIononGateEdge_pad5v ndiffDiffNetIononGateEdge_pad5v < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_71_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY InvalidPdiff_lu_1_5_io_only_pad5v
}
"r_72_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY InvalidNdiff_lu_1_5_io_only_pad5v
}
ndiffSameNetIo_io_pad = NET ndiffIo "io_pad"
ndiffDiffNetIo_io_pad = ndiffIo NOT ndiffSameNetIo_io_pad
pdiffSameNetIo_io_pad = NET pdiffIo "io_pad"
pdiffDiffNetIo_io_pad = pdiffIo NOT pdiffSameNetIo_io_pad
ndiffSameNetIononGateEdge_io_pad = ndiffSameNetIo_io_pad NOT COINCIDENT EDGE gate
ndiffDiffNetIononGateEdge_io_pad = ndiffDiffNetIo_io_pad NOT COINCIDENT EDGE gate
pdiffSameNetIononGateEdge_io_pad = pdiffSameNetIo_io_pad NOT COINCIDENT EDGE gate
pdiffDiffNetIononGateEdge_io_pad = pdiffDiffNetIo_io_pad NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_io_only_io_pad = INTERACT (EXTERNAL pdiffSameNetIononGateEdge_io_pad pdiffDiffNetIononGateEdge_io_pad < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetIononGateEdge_io_pad pdiffDiffNetIononGateEdge_io_pad < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_io_only_io_pad = INTERACT (EXTERNAL ndiffSameNetIononGateEdge_io_pad ndiffDiffNetIononGateEdge_io_pad < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetIononGateEdge_io_pad ndiffDiffNetIononGateEdge_io_pad < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_73_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY InvalidPdiff_lu_1_5_io_only_io_pad
}
"r_74_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY InvalidNdiff_lu_1_5_io_only_io_pad
}
ndiffSameNetIo_pad = NET ndiffIo "pad"
ndiffDiffNetIo_pad = ndiffIo NOT ndiffSameNetIo_pad
pdiffSameNetIo_pad = NET pdiffIo "pad"
pdiffDiffNetIo_pad = pdiffIo NOT pdiffSameNetIo_pad
ndiffSameNetIononGateEdge_pad = ndiffSameNetIo_pad NOT COINCIDENT EDGE gate
ndiffDiffNetIononGateEdge_pad = ndiffDiffNetIo_pad NOT COINCIDENT EDGE gate
pdiffSameNetIononGateEdge_pad = pdiffSameNetIo_pad NOT COINCIDENT EDGE gate
pdiffDiffNetIononGateEdge_pad = pdiffDiffNetIo_pad NOT COINCIDENT EDGE gate
InvalidPdiff_lu_1_5_io_only_pad = INTERACT (EXTERNAL pdiffSameNetIononGateEdge_pad pdiffDiffNetIononGateEdge_pad < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL pdiffSameNetIononGateEdge_pad pdiffDiffNetIononGateEdge_pad < 3.0 ABUT < 90 REGION EXTENTS) AND nwell) == 1
InvalidNdiff_lu_1_5_io_only_pad = INTERACT (EXTERNAL ndiffSameNetIononGateEdge_pad ndiffDiffNetIononGateEdge_pad < 3.0 ABUT < 90 REGION EXTENTS) ((EXTERNAL ndiffSameNetIononGateEdge_pad ndiffDiffNetIononGateEdge_pad < 3.0 ABUT < 90 REGION EXTENTS) AND isolatedSubstrate) == 1
"r_75_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY InvalidPdiff_lu_1_5_io_only_pad
}
"r_76_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY InvalidNdiff_lu_1_5_io_only_pad
}
lu_1_5_PSDsigPad = (INTERACT (EXTERNAL PSDsigPadNtr < 3.0 ABUT < 90 REGION EXTENTS NOT CONNECTED) ((EXTERNAL PSDsigPadNtr < 3.0 ABUT < 90 REGION EXTENTS NOT CONNECTED) AND nwell) == 1) NOT lu_1_5_xmt
lu_1_5_NSDsigPad = (EXTERNAL NSDsigPadNtr < 3.0 ABUT < 90 REGION EXTENTS NOT CONNECTED) NOT lu_1_5_xmt
"r_77_lu1.5" {
@ lu1.5: 3.00 Min space between pdiffs within common nwell or dnwell connected to different IO pads
COPY lu_1_5_PSDsigPad
}
"r_78_lu1.5" {
@ lu1.5: 3.00 Min space between ndiffs within common substrate connected to different IO pads
COPY lu_1_5_NSDsigPad
}
/// CALconnectZone started - zoneName was "zone_3"
DISCONNECT
CONNECT nwell NTAP
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT Met3 met3tt
CONNECT Met2 met2tt
CONNECT Met1 met1tt
CONNECT Li1 li1tt
CONNECT NSRCDRN difftt
CONNECT PSRCDRN difftt
CONNECT Li1 li1_pin BY Li1pt
CONNECT Met1 met1_pin BY Met1pt
CONNECT Met2 met2_pin BY Met2pt
CONNECT Met3 met3_pin BY Met3pt
CONNECT switched_intPower_met1 Met1
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT PolyNoRes gate
CONNECT PolyNoRes polytt
CONNECT PolyNoRes poly_pin BY polypt
CONNECT pad Met5
CONNECT probe_pad Met5
CONNECT Met5 Met4 BY Via4
CONNECT Met5 met5tt
CONNECT Met5 met5_pin BY Met5pt
CONNECT Met4 Met3 BY Via3
CONNECT Met4 met4tt
CONNECT Met4 met4_pin BY Met4pt
CONNECT rdl pad BY pmm
CONNECT rdl probe_pad BY pmm
CONNECT ndiffVcc NSRCDRN
CONNECT ndiffVss NSRCDRN
CONNECT pdiffVcc PSRCDRN
CONNECT pdiffVss PSRCDRN
CONNECT ndiffIo NSRCDRN
CONNECT pdiffIo PSRCDRN
CONNECT NSDsigPad NSRCDRN
CONNECT PSDsigPad PSRCDRN
CONNECT NSDsigPadNtr NSRCDRN
CONNECT PSDsigPadNtr PSRCDRN
CONNECT ntapRing NTAP
CONNECT ptapRing PTAP
/// CALconnectZone done. zoneName is now zone_4
PTAPnotSeal = PTAP NOT SEALID
NTAPnotSeal = NTAP NOT SEALID
PTAPnotSealDonut = DONUT PTAPnotSeal
PTAPnotSealDonut_nodnw = PTAPnotSeal NOT dnwell
NTAPnotSealDonut = DONUT NTAPnotSeal
padCellMet1 = INSIDE CELL metal1 "padPLfp$$*" "padPLhp$$*" "padPLstg$$*" "padPLwlbi$$*"
padCellMet2 = INSIDE CELL metal2 "padPLfp$$*" "padPLhp$$*" "padPLstg$$*" "padPLwlbi$$*"
padCellMet3 = INSIDE CELL metal3 "padPLfp$$*" "padPLhp$$*" "padPLstg$$*" "padPLwlbi$$*"
padCellMet4 = INSIDE CELL metal4 "padPLfp$$*" "padPLhp$$*" "padPLstg$$*" "padPLwlbi$$*"
padCellMet5 = INSIDE CELL metal5 "padPLfp$$*" "padPLhp$$*" "padPLstg$$*" "padPLwlbi$$*"
/// CALderiveGuardRings: Deriving guard ring inner:inner_ptap_DGR second:second_ntap_DGR third:nil
/// Inner ring derivation
q0PTAPnotSealDonut = DONUT PTAPnotSealDonut
q1PTAPnotSealDonut = COPY q0PTAPnotSealDonut
q3PTAPnotSealDonut = HOLES q1PTAPnotSealDonut INNER
q2PTAPnotSealDonut = COPY q3PTAPnotSealDonut
q5PTAPnotSealDonut = TOUCH q1PTAPnotSealDonut q2PTAPnotSealDonut
/// Second ring derivation
q0NTAPnotSealDonut = NOT INTERACT NTAPnotSealDonut q5PTAPnotSealDonut
q1NTAPnotSealDonut = DONUT q0NTAPnotSealDonut
q5NTAPnotSealDonut = COPY q1NTAPnotSealDonut
q4PTAPnotSealDonut = q2PTAPnotSealDonut NOT ENCLOSE q1NTAPnotSealDonut
q6PTAPnotSealDonut = TOUCH q5PTAPnotSealDonut q4PTAPnotSealDonut
q3NTAPnotSealDonut = (HOLES q5NTAPnotSealDonut) ENCLOSE q6PTAPnotSealDonut
q4NTAPnotSealDonut = ((q3NTAPnotSealDonut NOT q5NTAPnotSealDonut) NOT q6PTAPnotSealDonut) NOT q4PTAPnotSealDonut
q6NTAPnotSealDonut = TOUCH q4NTAPnotSealDonut q6PTAPnotSealDonut
q14NTAPnotSealDonut = TOUCH q5NTAPnotSealDonut q6NTAPnotSealDonut
q2NTAPnotSealDonut = HOLES q14NTAPnotSealDonut INNER
q13NTAPnotSealDonut = TOUCH q14NTAPnotSealDonut (q2NTAPnotSealDonut ENCLOSE q6PTAPnotSealDonut)
inner_ptap_DGR = q6PTAPnotSealDonut INSIDE (HOLES q13NTAPnotSealDonut)
second_ntap_DGR = COPY q13NTAPnotSealDonut
inner_hole_ptap_DGR = TOUCH q4PTAPnotSealDonut inner_ptap_DGR
PinnerToSecondReg_DGR = TOUCH q6NTAPnotSealDonut inner_ptap_DGR
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:inner_ntap_DGR second:second_ptap_DGR third:nil
/// Inner ring derivation
q15NTAPnotSealDonut = DONUT NTAPnotSealDonut
q16NTAPnotSealDonut = COPY q15NTAPnotSealDonut
q18NTAPnotSealDonut = HOLES q16NTAPnotSealDonut INNER
q17NTAPnotSealDonut = COPY q18NTAPnotSealDonut
q20NTAPnotSealDonut = TOUCH q16NTAPnotSealDonut q17NTAPnotSealDonut
/// Second ring derivation
q7PTAPnotSealDonut = NOT INTERACT PTAPnotSealDonut q20NTAPnotSealDonut
q8PTAPnotSealDonut = DONUT q7PTAPnotSealDonut
q12PTAPnotSealDonut = COPY q8PTAPnotSealDonut
q19NTAPnotSealDonut = q17NTAPnotSealDonut NOT ENCLOSE q8PTAPnotSealDonut
q21NTAPnotSealDonut = TOUCH q20NTAPnotSealDonut q19NTAPnotSealDonut
q10PTAPnotSealDonut = (HOLES q12PTAPnotSealDonut) ENCLOSE q21NTAPnotSealDonut
q11PTAPnotSealDonut = ((q10PTAPnotSealDonut NOT q12PTAPnotSealDonut) NOT q21NTAPnotSealDonut) NOT q19NTAPnotSealDonut
q13PTAPnotSealDonut = TOUCH q11PTAPnotSealDonut q21NTAPnotSealDonut
q21PTAPnotSealDonut = TOUCH q12PTAPnotSealDonut q13PTAPnotSealDonut
q9PTAPnotSealDonut = HOLES q21PTAPnotSealDonut INNER
q20PTAPnotSealDonut = TOUCH q21PTAPnotSealDonut (q9PTAPnotSealDonut ENCLOSE q21NTAPnotSealDonut)
inner_ntap_DGR = q21NTAPnotSealDonut INSIDE (HOLES q20PTAPnotSealDonut)
second_ptap_DGR = COPY q20PTAPnotSealDonut
inner_hole_ntap_DGR = TOUCH q19NTAPnotSealDonut inner_ntap_DGR
NinnerToSecondReg_DGR = TOUCH q13PTAPnotSealDonut inner_ntap_DGR
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:ptap_SGR second:nil third:nil
/// Inner ring derivation
q0ptap_SGR = COPY inner_ntap_DGR
q22PTAPnotSealDonut = DONUT PTAPnotSealDonut
q23PTAPnotSealDonut = COPY q22PTAPnotSealDonut
q25PTAPnotSealDonut = HOLES q23PTAPnotSealDonut INNER
q24PTAPnotSealDonut = q25PTAPnotSealDonut NOT ENCLOSE q0ptap_SGR
q26PTAPnotSealDonut = COPY q24PTAPnotSealDonut
ptap_SGR = TOUCH q23PTAPnotSealDonut q26PTAPnotSealDonut
hole_ptap_SGR = TOUCH q26PTAPnotSealDonut ptap_SGR
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:ntap_SGR second:nil third:nil
/// Inner ring derivation
q0ntap_SGR = COPY inner_ptap_DGR
q22NTAPnotSealDonut = DONUT NTAPnotSealDonut
q23NTAPnotSealDonut = COPY q22NTAPnotSealDonut
q25NTAPnotSealDonut = HOLES q23NTAPnotSealDonut INNER
q24NTAPnotSealDonut = q25NTAPnotSealDonut NOT ENCLOSE q0ntap_SGR
q26NTAPnotSealDonut = COPY q24NTAPnotSealDonut
ntap_SGR = TOUCH q23NTAPnotSealDonut q26NTAPnotSealDonut
hole_ntap_SGR = TOUCH q26NTAPnotSealDonut ntap_SGR
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:inner_ptap_TGR second:second_ntap_TGR third:third_ptap_TGR
/// Inner ring derivation
q29PTAPnotSealDonut = DONUT PTAPnotSealDonut
q30PTAPnotSealDonut = COPY q29PTAPnotSealDonut
q32PTAPnotSealDonut = HOLES q30PTAPnotSealDonut INNER
q31PTAPnotSealDonut = COPY q32PTAPnotSealDonut
q34PTAPnotSealDonut = TOUCH q30PTAPnotSealDonut q31PTAPnotSealDonut
/// Second ring derivation
q29NTAPnotSealDonut = NOT INTERACT NTAPnotSealDonut q34PTAPnotSealDonut
q30NTAPnotSealDonut = DONUT q29NTAPnotSealDonut
q34NTAPnotSealDonut = COPY q30NTAPnotSealDonut
q33PTAPnotSealDonut = q31PTAPnotSealDonut NOT ENCLOSE q30NTAPnotSealDonut
q35PTAPnotSealDonut = TOUCH q34PTAPnotSealDonut q33PTAPnotSealDonut
q32NTAPnotSealDonut = (HOLES q34NTAPnotSealDonut) ENCLOSE q35PTAPnotSealDonut
q33NTAPnotSealDonut = ((q32NTAPnotSealDonut NOT q34NTAPnotSealDonut) NOT q35PTAPnotSealDonut) NOT q33PTAPnotSealDonut
q35NTAPnotSealDonut = TOUCH q33NTAPnotSealDonut q35PTAPnotSealDonut
q43NTAPnotSealDonut = TOUCH q34NTAPnotSealDonut q35NTAPnotSealDonut
q31NTAPnotSealDonut = HOLES q43NTAPnotSealDonut INNER
q42NTAPnotSealDonut = TOUCH q43NTAPnotSealDonut (q31NTAPnotSealDonut ENCLOSE q35PTAPnotSealDonut < 2)
/// Third ring derivation
q36PTAPnotSealDonut = NOT INTERACT (NOT INTERACT PTAPnotSealDonut q42NTAPnotSealDonut) q35PTAPnotSealDonut
q37PTAPnotSealDonut = DONUT q36PTAPnotSealDonut
q38PTAPnotSealDonut = COPY q37PTAPnotSealDonut
q40PTAPnotSealDonut = (HOLES q38PTAPnotSealDonut) ENCLOSE q42NTAPnotSealDonut
q42PTAPnotSealDonut = ((q40PTAPnotSealDonut NOT q38PTAPnotSealDonut) NOT q42NTAPnotSealDonut) NOT q31NTAPnotSealDonut
q43PTAPnotSealDonut = TOUCH q42PTAPnotSealDonut q42NTAPnotSealDonut
q45PTAPnotSealDonut = TOUCH q38PTAPnotSealDonut q43PTAPnotSealDonut
q39PTAPnotSealDonut = HOLES q45PTAPnotSealDonut INNER
q44PTAPnotSealDonut = TOUCH q45PTAPnotSealDonut (q39PTAPnotSealDonut ENCLOSE q42NTAPnotSealDonut < 2)
third_ptap_TGR = COPY q44PTAPnotSealDonut
second_ntap_TGR = q42NTAPnotSealDonut INSIDE (HOLES third_ptap_TGR)
inner_ptap_TGR = q35PTAPnotSealDonut INSIDE (HOLES second_ntap_TGR)
inner_hole_ptap_TGR = TOUCH q33PTAPnotSealDonut inner_ptap_TGR
NinnerToSecondReg_TGR = TOUCH q35NTAPnotSealDonut inner_ptap_TGR
NsecondToThirdReg_TGR = TOUCH q43PTAPnotSealDonut second_ntap_TGR
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:inner_ntap_TGR second:second_ptap_TGR third:third_ntap_TGR
/// Inner ring derivation
q44NTAPnotSealDonut = DONUT NTAPnotSealDonut
q45NTAPnotSealDonut = COPY q44NTAPnotSealDonut
q47NTAPnotSealDonut = HOLES q45NTAPnotSealDonut INNER
q46NTAPnotSealDonut = COPY q47NTAPnotSealDonut
q49NTAPnotSealDonut = TOUCH q45NTAPnotSealDonut q46NTAPnotSealDonut
/// Second ring derivation
q51PTAPnotSealDonut = NOT INTERACT PTAPnotSealDonut q49NTAPnotSealDonut
q52PTAPnotSealDonut = DONUT q51PTAPnotSealDonut
q56PTAPnotSealDonut = COPY q52PTAPnotSealDonut
q48NTAPnotSealDonut = q46NTAPnotSealDonut NOT ENCLOSE q52PTAPnotSealDonut
q50NTAPnotSealDonut = TOUCH q49NTAPnotSealDonut q48NTAPnotSealDonut
q54PTAPnotSealDonut = (HOLES q56PTAPnotSealDonut) ENCLOSE q50NTAPnotSealDonut
q55PTAPnotSealDonut = ((q54PTAPnotSealDonut NOT q56PTAPnotSealDonut) NOT q50NTAPnotSealDonut) NOT q48NTAPnotSealDonut
q57PTAPnotSealDonut = TOUCH q55PTAPnotSealDonut q50NTAPnotSealDonut
q65PTAPnotSealDonut = TOUCH q56PTAPnotSealDonut q57PTAPnotSealDonut
q53PTAPnotSealDonut = HOLES q65PTAPnotSealDonut INNER
q64PTAPnotSealDonut = TOUCH q65PTAPnotSealDonut (q53PTAPnotSealDonut ENCLOSE q50NTAPnotSealDonut < 2)
/// Third ring derivation
q51NTAPnotSealDonut = NOT INTERACT (NOT INTERACT NTAPnotSealDonut q64PTAPnotSealDonut) q50NTAPnotSealDonut
q52NTAPnotSealDonut = DONUT q51NTAPnotSealDonut
q53NTAPnotSealDonut = COPY q52NTAPnotSealDonut
q55NTAPnotSealDonut = (HOLES q53NTAPnotSealDonut) ENCLOSE q64PTAPnotSealDonut
q57NTAPnotSealDonut = ((q55NTAPnotSealDonut NOT q53NTAPnotSealDonut) NOT q64PTAPnotSealDonut) NOT q53PTAPnotSealDonut
q58NTAPnotSealDonut = TOUCH q57NTAPnotSealDonut q64PTAPnotSealDonut
q60NTAPnotSealDonut = TOUCH q53NTAPnotSealDonut q58NTAPnotSealDonut
q54NTAPnotSealDonut = HOLES q60NTAPnotSealDonut INNER
q59NTAPnotSealDonut = TOUCH q60NTAPnotSealDonut (q54NTAPnotSealDonut ENCLOSE q64PTAPnotSealDonut < 2)
third_ntap_TGR = COPY q59NTAPnotSealDonut
second_ptap_TGR = q64PTAPnotSealDonut INSIDE (HOLES third_ntap_TGR)
inner_ntap_TGR = q50NTAPnotSealDonut INSIDE (HOLES second_ptap_TGR)
inner_hole_ntap_TGR = TOUCH q48NTAPnotSealDonut inner_ntap_TGR
PinnerToSecondReg_TGR = TOUCH q57PTAPnotSealDonut inner_ntap_TGR
PsecondToThirdReg_TGR = TOUCH q58NTAPnotSealDonut second_ptap_TGR
/// CALderiveGuardRings complete
"k_1_ptap_SGR" {
@ keep: ptap_SGR - ptap_SGR
COPY ptap_SGR
}
"k_2_hole_ptap_SGR" {
@ keep: hole_ptap_SGR - hole_ptap_SGR
COPY hole_ptap_SGR
}
"k_3_ntap_SGR" {
@ keep: ntap_SGR - ntap_SGR
COPY ntap_SGR
}
"k_4_hole_ntap_SGR" {
@ keep: hole_ntap_SGR - hole_ntap_SGR
COPY hole_ntap_SGR
}
"k_5_inner_ptap_DGR" {
@ keep: inner_ptap_DGR - inner_ptap_DGR
COPY inner_ptap_DGR
}
"k_6_inner_hole_ptap_DGR" {
@ keep: inner_hole_ptap_DGR - inner_hole_ptap_DGR
COPY inner_hole_ptap_DGR
}
"k_7_PinnerToSecondReg_DGR" {
@ keep: PinnerToSecondReg_DGR - PinnerToSecondReg_DGR
COPY PinnerToSecondReg_DGR
}
"k_8_second_ntap_DGR" {
@ keep: second_ntap_DGR - second_ntap_DGR
COPY second_ntap_DGR
}
"k_9_inner_ntap_DGR" {
@ keep: inner_ntap_DGR - inner_ntap_DGR
COPY inner_ntap_DGR
}
"k_10_inner_hole_ntap_DGR" {
@ keep: inner_hole_ntap_DGR - inner_hole_ntap_DGR
COPY inner_hole_ntap_DGR
}
"k_11_NinnerToSecondReg_DGR" {
@ keep: NinnerToSecondReg_DGR - NinnerToSecondReg_DGR
COPY NinnerToSecondReg_DGR
}
"k_12_second_ptap_DGR" {
@ keep: second_ptap_DGR - second_ptap_DGR
COPY second_ptap_DGR
}
"k_13_inner_ptap_TGR" {
@ keep: inner_ptap_TGR - inner_ptap_TGR
COPY inner_ptap_TGR
}
"k_14_second_ntap_TGR" {
@ keep: second_ntap_TGR - second_ntap_TGR
COPY second_ntap_TGR
}
"k_15_inner_hole_ptap_TGR" {
@ keep: inner_hole_ptap_TGR - inner_hole_ptap_TGR
COPY inner_hole_ptap_TGR
}
"k_16_NinnerToSecondReg_TGR" {
@ keep: NinnerToSecondReg_TGR - NinnerToSecondReg_TGR
COPY NinnerToSecondReg_TGR
}
"k_17_NsecondToThirdReg_TGR" {
@ keep: NsecondToThirdReg_TGR - NsecondToThirdReg_TGR
COPY NsecondToThirdReg_TGR
}
"k_18_third_ptap_TGR" {
@ keep: third_ptap_TGR - third_ptap_TGR
COPY third_ptap_TGR
}
"k_19_inner_ntap_TGR" {
@ keep: inner_ntap_TGR - inner_ntap_TGR
COPY inner_ntap_TGR
}
"k_20_second_ptap_TGR" {
@ keep: second_ptap_TGR - second_ptap_TGR
COPY second_ptap_TGR
}
"k_21_inner_hole_ntap_TGR" {
@ keep: inner_hole_ntap_TGR - inner_hole_ntap_TGR
COPY inner_hole_ntap_TGR
}
"k_22_PinnerToSecondReg_TGR" {
@ keep: PinnerToSecondReg_TGR - PinnerToSecondReg_TGR
COPY PinnerToSecondReg_TGR
}
"k_23_PsecondToThirdReg_TGR" {
@ keep: PsecondToThirdReg_TGR - PsecondToThirdReg_TGR
COPY PsecondToThirdReg_TGR
}
"k_24_third_ntap_TGR" {
@ keep: third_ntap_TGR - third_ntap_TGR
COPY third_ntap_TGR
}
/// CALconnectZone started - zoneName was "zone_4"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_5
endCapPolyNoRes = TOUCH PolyNoRes ResPoly
endCapMet1NoEsdRes = TOUCH Met1 Met1EsdRes
endCapMet2NoEsdRes = TOUCH Met2 Met2EsdRes
endCapMet3NoEsdRes = TOUCH Met3 Met3EsdRes
endCapNSRCDRN = TOUCH NSRCDRN nDiffRes
endCapPSRCDRN = TOUCH PSRCDRN pDiffRes
endCapPTAPPWRes = TOUCH PTAP pwellres
endCapMet4NoEsdRes = TOUCH Met4 Met4EsdRes
endCapMet5NoEsdRes = TOUCH Met5 Met5EsdRes
/// CALconnectZone started - zoneName was "zone_5"
CONNECT endCapPolyNoRes PolyNoRes
CONNECT endCapMet1NoEsdRes Met1
CONNECT endCapMet2NoEsdRes Met2
CONNECT endCapMet3NoEsdRes Met3
CONNECT endCapNSRCDRN NSRCDRN
CONNECT endCapPSRCDRN PSRCDRN
CONNECT endCapPTAPPWRes PTAP
CONNECT endCapMet4NoEsdRes Met4
CONNECT endCapMet5NoEsdRes Met5
/// CALconnectZone done. zoneName is now zone_6
lu11_4_exempt = EXTENT CELL "s8iom0s8_top_gpio" "s8iom0s8_top_xres" "s8iom0s8_top_power_hvc_wpad" "s8iom0s8_top_ground_hvc_wpad" "s8iom0s8_top_hvclamp_wopad" "s8iom0s8_top_power_lvc_wpad" "s8iom0s8_top_ground_lvc_wpad" "s8iom0s8_top_lvc_b2b_wopad" "s8iom0s8_top_lvclamp" "s8iom0s8_analog_pad" "s8iom0s8_top_xres_2" "s8ctbm_NFET_con_diff_abt_260" "s8ctbm_PFET_con_diff_abt_520" "s8usbpd_sbu_sw_top" "s8framio_esd_paddiode2pwr_100_lv" "s8framio_esd_paddiode2gnd_100_dnwl_lv" ORIGINAL
NSRCDRN_nonExempt = NSRCDRN NOT ESDID
PSRCDRN_nonExempt = PSRCDRN NOT ESDID
NSRCDRN_lu11 = NET NSRCDRN_nonExempt "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
PSRCDRN_lu11 = NET PSRCDRN_nonExempt "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
gateNonESD = (gate NOT ESDID) NOT lu11_4_exempt
badGateNtmp = (INTERACT gateNonESD NSDsigPad == 2.0) OR (INTERACT gateNonESD NSRCDRN_lu11 BY NET == 2.0)
badGatePtmp = (INTERACT gateNonESD PSDsigPad == 2.0) OR (INTERACT gateNonESD PSRCDRN_lu11 BY NET == 2.0)
gateEdgeN = EXPAND EDGE (badGateNtmp INSIDE EDGE diff) INSIDE BY 0.005
gateEdgeP = EXPAND EDGE (badGatePtmp INSIDE EDGE diff) INSIDE BY 0.005
CONNECT gate gateEdgeP
CONNECT gate gateEdgeN
testgateP = NET AREA RATIO gateEdgeP < 2000.000000 [AREA(gateEdgeP)/0.005000 /2.000000 ] RDB lu.11.4_pgate.db gateEdgeP
"r_79_lu.11.4" {
@ lu.11.4 Pgate non ESD with Width less than 2000 um with src and drain connected to external pads
INTERACT gate testgateP
}
testgateN = NET AREA RATIO gateEdgeN < 2000.000000 [AREA(gateEdgeN)/0.005000 /2.000000 ] RDB lu.11.4_ngate.db gateEdgeN
"r_80_lu.11.4" {
@ lu.11.4 Ngate non ESD with Width less than 2000 um with src and drain connected to external pads
INTERACT gate testgateN
}
vccEndCapPolyNoRes = NET endCapPolyNoRes "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCapResPoly = TOUCH ResPoly vccEndCapPolyNoRes
vccEndCapPolyNoResVD = TOUCH vccEndCapPolyNoRes vccEndCapResPoly
vssEndCapPolyNoRes = NET endCapPolyNoRes "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCapResPoly = TOUCH ResPoly vssEndCapPolyNoRes
vssEndCapPolyNoResVD = TOUCH vssEndCapPolyNoRes vssEndCapResPoly
ResPolyVDConnect = ResPoly NOT (vccEndCapResPoly OR vssEndCapResPoly)
PolyNoResVDConnect = PolyNoRes NOT (vccEndCapPolyNoResVD OR vssEndCapPolyNoResVD)
vccEndCapNSRCDRN = NET NSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCapnDiffRes = TOUCH nDiffRes vccEndCapNSRCDRN
vccEndCapNSRCDRNVD = TOUCH vccEndCapNSRCDRN vccEndCapnDiffRes
vssEndCapNSRCDRN = NET NSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCapnDiffRes = TOUCH nDiffRes vssEndCapNSRCDRN
vssEndCapNSRCDRNVD = TOUCH vssEndCapNSRCDRN vssEndCapnDiffRes
nDiffResVDConnect = nDiffRes NOT (vccEndCapnDiffRes OR vssEndCapnDiffRes)
NSRCDRNVDConnect = NSRCDRN NOT (vccEndCapNSRCDRNVD OR vssEndCapNSRCDRNVD)
vccEndCapPSRCDRN = NET PSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCappDiffRes = TOUCH pDiffRes vccEndCapPSRCDRN
vccEndCapPSRCDRNVD = TOUCH vccEndCapPSRCDRN vccEndCappDiffRes
vssEndCapPSRCDRN = NET PSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCappDiffRes = TOUCH pDiffRes vssEndCapPSRCDRN
vssEndCapPSRCDRNVD = TOUCH vssEndCapPSRCDRN vssEndCappDiffRes
pDiffResVDConnect = pDiffRes NOT (vccEndCappDiffRes OR vssEndCappDiffRes)
PSRCDRNVDConnect = PSRCDRN NOT (vccEndCapPSRCDRNVD OR vssEndCapPSRCDRNVD)
vccEndCapPTAPPWRes = NET endCapPTAPPWRes "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCapPwellRes = TOUCH pwellres vccEndCapPTAPPWRes
vccEndCapPTAPVD = TOUCH vccEndCapPTAPPWRes vccEndCapPwellRes
vssEndCapPTAPPWRes = NET endCapPTAPPWRes "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCapPwellRes = TOUCH pwellres vssEndCapPTAPPWRes
vssEndCapPTAPVD = TOUCH vssEndCapPTAPPWRes vssEndCapPwellRes
PwellResVDConnect = pwellres NOT (vccEndCapPwellRes OR vssEndCapPwellRes)
PTAPPWResVDConnect = endCapPTAPPWRes NOT (vccEndCapPTAPVD OR vssEndCapPTAPVD)
vccEndCapMet1NoEsdRes = NET endCapMet1NoEsdRes "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCapMet1EsdRes = TOUCH Met1EsdRes vccEndCapMet1NoEsdRes
vccEndCapMet1NoEsdResVD = TOUCH vccEndCapMet1NoEsdRes vccEndCapMet1EsdRes
vssEndCapMet1NoEsdRes = NET endCapMet1NoEsdRes "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCapMet1EsdRes = TOUCH Met1EsdRes vssEndCapMet1NoEsdRes
vssEndCapMet1NoEsdResVD = TOUCH vssEndCapMet1NoEsdRes vssEndCapMet1EsdRes
Met1EsdResVDConnect = Met1EsdRes NOT (vccEndCapMet1EsdRes OR vssEndCapMet1EsdRes)
Met1EsdNoResVDConnect = Met1 NOT (vccEndCapMet1NoEsdResVD OR vssEndCapMet1NoEsdResVD)
vccEndCapMet2NoEsdRes = NET endCapMet2NoEsdRes "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCapMet2EsdRes = TOUCH Met2EsdRes vccEndCapMet2NoEsdRes
vccEndCapMet2NoEsdResVD = TOUCH vccEndCapMet2NoEsdRes vccEndCapMet2EsdRes
vssEndCapMet2NoEsdRes = NET endCapMet2NoEsdRes "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCapMet2EsdRes = TOUCH Met2EsdRes vssEndCapMet2NoEsdRes
vssEndCapMet2NoEsdResVD = TOUCH vssEndCapMet2NoEsdRes vssEndCapMet2EsdRes
Met2EsdResVDConnect = Met2EsdRes NOT (vccEndCapMet2EsdRes OR vssEndCapMet2EsdRes)
Met2EsdNoResVDConnect = Met2 NOT (vccEndCapMet2NoEsdResVD OR vssEndCapMet2NoEsdResVD)
vccEndCapMet3NoEsdRes = NET endCapMet3NoEsdRes "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCapMet3EsdRes = TOUCH Met3EsdRes vccEndCapMet3NoEsdRes
vccEndCapMet3NoEsdResVD = TOUCH vccEndCapMet3NoEsdRes vccEndCapMet3EsdRes
vssEndCapMet3NoEsdRes = NET endCapMet3NoEsdRes "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCapMet3EsdRes = TOUCH Met3EsdRes vssEndCapMet3NoEsdRes
vssEndCapMet3NoEsdResVD = TOUCH vssEndCapMet3NoEsdRes vssEndCapMet2EsdRes
Met3EsdResVDConnect = Met3EsdRes NOT (vccEndCapMet3EsdRes OR vssEndCapMet3EsdRes)
Met3EsdNoResVDConnect = Met3 NOT (vccEndCapMet3NoEsdResVD OR vssEndCapMet3NoEsdResVD)
ioEndCapPolyNoRes = NET endCapPolyNoRes "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
vccEndCapMet4NoEsdRes = NET endCapMet4NoEsdRes "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCapMet4EsdRes = TOUCH Met4EsdRes vccEndCapMet4NoEsdRes
vccEndCapMet4NoEsdResVD = TOUCH vccEndCapMet4NoEsdRes vccEndCapMet4EsdRes
vssEndCapMet4NoEsdRes = NET endCapMet4NoEsdRes "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCapMet4EsdRes = TOUCH Met4EsdRes vssEndCapMet4NoEsdRes
vssEndCapMet4NoEsdResVD = TOUCH vssEndCapMet4NoEsdRes vssEndCapMet2EsdRes
Met4EsdResVDConnect = Met4EsdRes NOT (vccEndCapMet4EsdRes OR vssEndCapMet4EsdRes)
Met4EsdNoResVDConnect = Met4 NOT (vccEndCapMet4NoEsdResVD OR vssEndCapMet4NoEsdResVD)
vccEndCapMet5NoEsdRes = NET endCapMet5NoEsdRes "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccEndCapMet5EsdRes = TOUCH Met5EsdRes vccEndCapMet5NoEsdRes
vccEndCapMet5NoEsdResVD = TOUCH vccEndCapMet5NoEsdRes vccEndCapMet5EsdRes
vssEndCapMet5NoEsdRes = NET endCapMet5NoEsdRes "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssEndCapMet5EsdRes = TOUCH Met5EsdRes vssEndCapMet5NoEsdRes
vssEndCapMet5NoEsdResVD = TOUCH vssEndCapMet5NoEsdRes vssEndCapMet2EsdRes
Met5EsdResVDConnect = Met5EsdRes NOT (vccEndCapMet5EsdRes OR vssEndCapMet5EsdRes)
Met5EsdNoResVDConnect = Met5 NOT (vccEndCapMet5NoEsdResVD OR vssEndCapMet5NoEsdResVD)
LU4_ioPad = NET pad "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
LU4_NSRCDRNspNtr = NOT INTERACT (NSDsigPadNtr OR (NET AREA RATIO NSRCDRN lu4_ioPad > 0)) ENID
LU4_PSRCDRNspNtr = NOT INTERACT (PSDsigPadNtr OR (NET AREA RATIO PSRCDRN lu4_ioPad > 0)) ENID
LU4_NTAPspNtr = NOT INTERACT (NTAPsigPadNtr OR (NET AREA RATIO NTAP lu4_ioPad > 0)) ENID
LU4_PTAPspNtr = NOT INTERACT (PTAPsigPadNtr OR (NET AREA RATIO PTAP lu4_ioPad > 0)) ENID
lu4_ioNSDnet = NET AREA RATIO NSRCDRN LU4_ioPad > 0
lu4_ioPSDnet = NET AREA RATIO PSRCDRN LU4_ioPad > 0
lu4_ioNSD = NSDsigPadNtr OR lu4_ioNSDnet
lu4_ioPSD = PSDsigPadNtr OR lu4_ioPSDnet
lu4_ioPSD_Nwell = INTERACT nwell lu4_ioPSD
lu4_12_a_xmtDiff = INSIDE CELL diff "s8sio_lvttl2k_io_r" "s8sio_gp4k_outbuf"
lu4_12_a_ioPSDxmtCell = lu4_ioPSD AND lu4_12_a_xmtDiff
lu4_12_a_ioPSDxmtCell_Nwell = INTERACT nwell lu4_12_a_ioPSDxmtCell
lu4_12_a_ioPSDnonXmt = lu4_ioPSD NOT lu4_12_a_ioPSDxmtCell
lu4_12_a_ioPSDnonXmt_Nwell = INTERACT nwell lu4_12_a_ioPSDnonXmt
lu4_vssNSD = NET NSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
lu4_12_vssNSDxmtCell = lu4_vssNSD AND lu4_12_a_xmtDiff
lu4_12_vssNSDnonXmt = lu4_vssNSD NOT lu4_12_vssNSDxmtCell
lu4_vssNw = NET nwell "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
lu4_vccPSD = (NET PSRCDRN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2") OR (NET AREA RATIO PSRCDRN switched_intPower_met1 > 0)
Pwell = (dnwell NOT nwell) AND isolatedSubNoPWR
Pwellstamp = STAMP Pwell BY isolatedSubNoPWR
pwellSigPadNtr = pwell INSIDE SigPadWellNtr
lu4_ioPwellNet = NET Pwellstamp "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
lu4_ioPwell = pwellSigPadNtr OR lu4_ioPwellNet
lu4_fpg1Cells = EXTENT CELL "s8fpafeg1_io_gnd2gnd_180x2_lv_dnwl_aup" "s8fpafeg1_io_gnd2gnd_240x1_lv_dnwl_aup" ORIGINAL
lu4_ioPwellNoXmt = lu4_ioPwell NOT lu4_fpg1Cells
lu4_ioPwellReduceXmt = lu4_ioPwell AND lu4_fpg1Cells
lu4_vccPw = (NET Pwellstamp "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2") OR (NET AREA RATIO Pwellstamp switched_intPower_met1 > 0)
lu4_ioNwellNet = NET nwell "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
lu4_ioNwell = nwellSigPadNtr OR lu4_ioNwellNet
lu_4_12f_xmt = EXTENT CELL "s8usbpdv2_20sbu_sw_ovp_ngate" ORIGINAL
lu4_12f_ioNwell = lu4_ioNwell NOT lu_4_12f_xmt
/// CALconnectZone started - zoneName was "zone_6"
CONNECT lu4_ioNSD NSRCDRN
CONNECT lu4_ioPSD PSRCDRN
CONNECT lu4_12_a_ioPSDxmtCell PSRCDRN
CONNECT lu4_12_a_ioPSDnonXmt PSRCDRN
CONNECT lu4_ioPwell isolatedSubNoPWR
CONNECT lu4_ioPwellNoXmt isolatedSubNoPWR
CONNECT lu4_ioPwellReduceXmt isolatedSubNoPWR
CONNECT Pwellstamp isolatedSubNoPWR
CONNECT lu4_ioPSD_Nwell nwell
CONNECT lu4_12_a_ioPSDxmtCell_Nwell nwell
CONNECT lu4_12_a_ioPSDnonXmt_Nwell nwell
CONNECT lu4_ioNwell nwell
CONNECT lu4_12f_ioNwell nwell
/// CALconnectZone done. zoneName is now zone_7
lu4_ioPSD_NwellConn = NET AREA RATIO lu4_ioPSD lu4_ioPSD_Nwell > 0 INSIDE OF LAYER nwell
lu4_12_ioPSDnonXmt_NwellConn = NET AREA RATIO lu4_12_a_ioPSDnonXmt lu4_12_a_ioPSDnonXmt_Nwell > 0 INSIDE OF LAYER nwell
lu4_12_ioPSDxmtCell_NwellConn = NET AREA RATIO lu4_12_a_ioPSDxmtCell lu4_12_a_ioPSDxmtCell_Nwell > 0 INSIDE OF LAYER nwell
lu4_12_c_j_ioPSD = lu4_ioPSD NOT lu4_ioPSD_NwellConn
lu4_12_a_1 = lu4_12_a_ioPSDnonXmt NOT lu4_12_ioPSDnonXmt_NwellConn
lu4_12_a_2 = lu4_12_a_ioPSDxmtCell NOT lu4_12_ioPSDxmtCell_NwellConn
lu4_ioNSD_PwellConn = NET AREA RATIO lu4_ioNSD Pwellstamp > 0 INSIDE OF LAYER Pwell
lu4_12e_g_m_n_ioNSD = lu4_ioNSD NOT lu4_ioNSD_PwellConn
/// CALconnectZone started - zoneName was "zone_7"
CONNECT lu4_12_c_j_ioPSD PSRCDRN
CONNECT lu4_ioPSD_NwellConn PSRCDRN
/// CALconnectZone done. zoneName is now zone_8
"r_81_lu.4.12a" {
@ lu.4.12a: 27 min. spacing of pdiff metallically connected to signal pad & ndiff metallically connected to ground net
EXTERNAL lu4_12_a_1 lu4_12_vssNSDnonXmt < 27.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_82_lu.4.12a" {
@ lu.4.12a: 27 min. spacing of pdiff metallically connected to signal pad & ndiff (inside exempt cell names) metallically connected to ground net
EXTERNAL lu4_12_a_1 lu4_12_vssNSDxmtCell < 27.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_83_lu.4.12a" {
@ lu.4.12a: 27 min. spacing of pdiff (inside exempt cell names) metallically connected to signal pad & ndiff metallically connected to ground net
EXTERNAL lu4_12_a_2 lu4_12_vssNSDnonXmt < 27.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_84_lu.4.12b" {
@ lu.4.12b: 40 min. spacing of lu4_ioPwellNoXmt & ndiff metallically connected to ground net
EXTERNAL lu4_ioPwellNoXmt lu4_vssNSD < 40.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_85_lu.4.12c" {
@ lu.4.12c: 40 min. spacing of pdiff metallically connected to signal pad & nwell metallically connected to ground net
EXTERNAL lu4_12_c_j_ioPSD lu4_vssNw < 40.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_86_lu.4.12d" {
@ lu.4.12d: 40 min. spacing of lu4_ioPwellNoXmt & nwell metallically connected to ground net
EXTERNAL lu4_ioPwellNoXmt lu4_vssNw < 40.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_87_lu.4.12e" {
@ lu.4.12e: 27 min. spacing of ndiff metallically connected to signal pad & pdiff metallically connected to supply or switched_power net
EXTERNAL lu4_12e_g_m_n_ioNSD lu4_vccPSD < 27.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_88_lu.4.12f" {
@ lu.4.12f: 40 min. spacing of nwell metallically connected to signal pad & pdiff metallically connected to supply or switched_power net
EXTERNAL lu4_12f_ioNwell lu4_vccPSD < 40.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_89_lu.4.12g" {
@ lu.4.12g: 40 min. spacing of ndiff metallically connected to signal pad & pwell metallically connected to supply or switched_power net
EXTERNAL lu4_12e_g_m_n_ioNSD lu4_vccPw < 40.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_90_lu.4.12h" {
@ lu.4.12h: 40 min. spacing of nwell metallically connected to signal pad & pwell metallically connected to supply or switched_power net
EXTERNAL lu4_ioNwell lu4_vccPw < 40.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_91_lu.4.12i" {
@ lu.4.12i: 27 min. spacing of pdiff metallically connected to signal pad & ndiff metallically connected to signal pad
EXTERNAL lu4_ioPSD lu4_ioNSD < 27.0 ABUT < 90 SINGULAR REGION NOT CONNECTED EXCLUDE FALSE
}
"r_92_lu.4.12j" {
@ lu.4.12j: 40 min. spacing of pdiff metallically connected to signal pad & nwell metallically connected to signal pad
EXTERNAL lu4_12_c_j_ioPSD lu4_ioNwell < 40.0 ABUT < 90 SINGULAR REGION NOT CONNECTED EXCLUDE FALSE
}
"r_93_lu.4.12k" {
@ lu.4.12k: 40 min. spacing of lu4_ioPwellNoXmt & ndiff metallically connected to signal pad
EXTERNAL lu4_ioPwellNoXmt lu4_ioNSD < 40.0 ABUT < 90 SINGULAR REGION NOT CONNECTED EXCLUDE FALSE
}
"r_94_lu.4.12l" {
@ lu.4.12l: 40 min. spacing of pwell metallically connected to signal pad & nwell metallically connected to signal pad
EXTERNAL lu4_ioPwell lu4_ioNwell < 40.0 ABUT < 90 SINGULAR REGION NOT CONNECTED EXCLUDE FALSE
}
"r_95_lu.4.12b" {
@ lu.4.12b: 27 min. spacing of lu4_ioPwellReduceXmt & ndiff metallically connected to ground net
EXTERNAL lu4_ioPwellReduceXmt lu4_vssNSD < 27.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_96_lu.4.12k" {
@ lu.4.12k: 27 min. spacing of lu4_ioPwellReduceXmt & ndiff metallically connected to signal pad
EXTERNAL lu4_ioPwellReduceXmt lu4_ioNSD < 27.0 ABUT < 90 SINGULAR REGION NOT CONNECTED EXCLUDE FALSE
}
LU5_nWellExtVcc_resOpen = NET nwell "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
/// CALconnectZone started - zoneName was "zone_8"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT PolyNoResVDConnect PolyNoRes
CONNECT ResPolyVDConnect PolyNoResVDConnect
CONNECT vssEndCapResPoly PolyNoResVDConnect
CONNECT vccEndCapResPoly PolyNoResVDConnect
CONNECT NSRCDRNVDConnect NSRCDRN
CONNECT nDiffResVDConnect NSRCDRNVDConnect
CONNECT vssEndCapnDiffRes NSRCDRNVDConnect
CONNECT vccEndCapnDiffRes NSRCDRNVDConnect
CONNECT PSRCDRNVDConnect PSRCDRN
CONNECT pDiffResVDConnect PSRCDRNVDConnect
CONNECT vssEndCappDiffRes PSRCDRNVDConnect
CONNECT vccEndCappDiffRes PSRCDRNVDConnect
CONNECT PTAPPWResVDConnect PTAP
CONNECT PwellResVDConnect isolatedSubNoPWR
CONNECT vccEndCapPwellRes isolatedSubNoPWR
CONNECT vssEndCapPwellRes isolatedSubNoPWR
CONNECT Met1EsdNoResVDConnect Met1
CONNECT Met1EsdResVDConnect Met1EsdNoResVDConnect
CONNECT vssEndCapMet1EsdRes Met1EsdNoResVDConnect
CONNECT vccEndCapMet1EsdRes Met1EsdNoResVDConnect
CONNECT Met2EsdNoResVDConnect Met2
CONNECT Met2EsdResVDConnect Met2EsdNoResVDConnect
CONNECT vssEndCapMet2EsdRes Met2EsdNoResVDConnect
CONNECT vccEndCapMet2EsdRes Met2EsdNoResVDConnect
CONNECT Met3EsdNoResVDConnect Met3
CONNECT Met3EsdResVDConnect Met3EsdNoResVDConnect
CONNECT vssEndCapMet3EsdRes Met3EsdNoResVDConnect
CONNECT vccEndCapMet3EsdRes Met3EsdNoResVDConnect
CONNECT Met4EsdNoResVDConnect Met4
CONNECT Met4EsdResVDConnect Met4EsdNoResVDConnect
CONNECT vssEndCapMet4EsdRes Met4EsdNoResVDConnect
CONNECT vccEndCapMet4EsdRes Met4EsdNoResVDConnect
CONNECT Met5EsdNoResVDConnect Met5
CONNECT Met5EsdResVDConnect Met5EsdNoResVDConnect
CONNECT vssEndCapMet5EsdRes Met5EsdNoResVDConnect
CONNECT vccEndCapMet5EsdRes Met5EsdNoResVDConnect
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_9
vccResPolyXmt = NET AREA RATIO vccEndCapResPoly OVER vssEndCapResPoly vssEndCapnDiffRes vssEndCappDiffRes vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssResPolyXmt = NET AREA RATIO vssEndCapResPoly OVER vccEndCapResPoly vccEndCapnDiffRes vccEndCappDiffRes vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vccEndCapMet4EsdRes vccEndCapMet5EsdRes > 0
xmtResPoly = vccResPolyXmt OR vssResPolyXmt
vccPwellResXmt = NET AREA RATIO vccEndCapPwellRes OVER vssEndCapResPoly vssEndCapnDiffRes vssEndCappDiffRes vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssPwellResXmt = NET AREA RATIO vssEndCapPwellRes OVER vccEndCapResPoly vccEndCapnDiffRes vccEndCappDiffRes vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vccEndCapMet4EsdRes vccEndCapMet5EsdRes > 0
xmtPwellRes = vccPwellResXmt OR vssPwellResXmt
vccEndCapnDiffResXmt = NET AREA RATIO vccEndCapnDiffRes OVER vssEndCapnDiffRes vssEndCappDiffRes vssEndCapResPoly vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssEndCapnDiffResXmt = NET AREA RATIO vssEndCapnDiffRes OVER vccEndCapnDiffRes vccEndCappDiffRes vccEndCapResPoly vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vccEndCapMet4EsdRes vccEndCapMet5EsdRes > 0
xmtnDiffRes = vccEndCapnDiffResXmt OR vssEndCapnDiffResXmt
vccEndCappDiffResXmt = NET AREA RATIO vccEndCappDiffRes OVER vssEndCappDiffRes vssEndCapnDiffRes vssEndCapResPoly vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssEndCappDiffResXmt = NET AREA RATIO vssEndCappDiffRes OVER vccEndCappDiffRes vccEndCapnDiffRes vccEndCapResPoly vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
xmtpDiffRes = vccEndCappDiffResXmt OR vssEndCappDiffResXmt
vccEndCapMet1EsdResXmt = NET AREA RATIO vccEndCapMet1EsdRes OVER vssEndCappDiffRes vssEndCapnDiffRes vssEndCapResPoly vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssEndCapMet1EsdResXmt = NET AREA RATIO vssEndCapMet1EsdRes OVER vccEndCappDiffRes vccEndCapnDiffRes vccEndCapResPoly vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vccEndCapMet4EsdRes vccEndCapMet5EsdRes > 0
xmtMet1EsdRes = vccEndCapMet1EsdResXmt OR vssEndCapMet1EsdResXmt
vccEndCapMet2EsdResXmt = NET AREA RATIO vccEndCapMet2EsdRes OVER vssEndCappDiffRes vssEndCapnDiffRes vssEndCapResPoly vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssEndCapMet2EsdResXmt = NET AREA RATIO vssEndCapMet2EsdRes OVER vccEndCappDiffRes vccEndCapnDiffRes vccEndCapResPoly vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vccEndCapMet4EsdRes vccEndCapMet5EsdRes > 0
xmtMet2EsdRes = vccEndCapMet2EsdResXmt OR vssEndCapMet2EsdResXmt
vccEndCapMet3EsdResXmt = NET AREA RATIO vccEndCapMet3EsdRes OVER vssEndCappDiffRes vssEndCapnDiffRes vssEndCapResPoly vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssEndCapMet3EsdResXmt = NET AREA RATIO vssEndCapMet3EsdRes OVER vccEndCappDiffRes vccEndCapnDiffRes vccEndCapResPoly vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vccEndCapMet4EsdRes vccEndCapMet5EsdRes > 0
xmtMet3EsdRes = vccEndCapMet3EsdResXmt OR vssEndCapMet3EsdResXmt
vccEndCapMet4EsdResXmt = NET AREA RATIO vccEndCapMet4EsdRes OVER vssEndCappDiffRes vssEndCapnDiffRes vssEndCapResPoly vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssEndCapMet4EsdResXmt = NET AREA RATIO vssEndCapMet4EsdRes OVER vccEndCappDiffRes vccEndCapnDiffRes vccEndCapResPoly vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vccEndCapMet4EsdRes vccEndCapMet5EsdRes > 0
xmtMet4EsdRes = vccEndCapMet4EsdResXmt OR vssEndCapMet4EsdResXmt
vccEndCapMet5EsdResXmt = NET AREA RATIO vccEndCapMet4EsdRes OVER vssEndCappDiffRes vssEndCapnDiffRes vssEndCapResPoly vssEndCapPwellRes vssEndCapMet1EsdRes vssEndCapMet2EsdRes vssEndCapMet3EsdRes vssEndCapMet4EsdRes vssEndCapMet5EsdRes > 0
vssEndCapMet5EsdResXmt = NET AREA RATIO vssEndCapMet4EsdRes OVER vccEndCappDiffRes vccEndCapnDiffRes vccEndCapResPoly vccEndCapPwellRes vccEndCapMet1EsdRes vccEndCapMet2EsdRes vccEndCapMet3EsdRes vccEndCapMet4EsdRes vccEndCapMet5EsdRes > 0
xmtMet5EsdRes = vccEndCapMet5EsdResXmt OR vssEndCapMet5EsdResXmt
Diff_leaker = WITH TEXT diffres "leaker" textlabel
Poly_leaker = WITH TEXT polyres "leaker" textlabel
Pwell_leaker = WITH TEXT pwellres "leaker" textlabel
Met1_leaker = WITH TEXT met1res "leaker" textlabel
Met2_leaker = WITH TEXT met2res "leaker" textlabel
Met3_leaker = WITH TEXT met3res "leaker" textlabel
Diff_openRes = WITH TEXT diffres "openRes" textlabel
Poly_openRes = WITH TEXT polyres "openRes" textlabel
Pwell_openRes = WITH TEXT pwellres "openRes" textlabel
Met1_openRes = WITH TEXT met1res "openRes" textlabel
Met2_openRes = WITH TEXT met2res "openRes" textlabel
Met3_openRes = WITH TEXT met3res "openRes" textlabel
Diff_bias = (WITH TEXT diffres "pwr_bias" textlabel) OR (WITH TEXT diffres "gnd_bias" textlabel)
Poly_bias = (WITH TEXT polyres "pwr_bias" textlabel) OR (WITH TEXT polyres "gnd_bias" textlabel)
Pwell_bias = (WITH TEXT pwellres "pwr_bias" textlabel) OR (WITH TEXT pwellres "gnd_bias" textlabel)
Met1_bias = (WITH TEXT met1res "pwr_bias" textlabel) OR (WITH TEXT met1res "gnd_bias" textlabel)
Met2_bias = (WITH TEXT met2res "pwr_bias" textlabel) OR (WITH TEXT met2res "gnd_bias" textlabel)
Met3_bias = (WITH TEXT met3res "pwr_bias" textlabel) OR (WITH TEXT met3res "gnd_bias" textlabel)
Diff_10k_res = WITH TEXT diffres "10KOhm" textlabel
Poly_10k_res = WITH TEXT polyres "10KOhm" textlabel
Pwell_10k_res = WITH TEXT pwellres "10KOhm" textlabel
Met1_10k_res = WITH TEXT met1res "10KOhm" textlabel
Met2_10k_res = WITH TEXT met2res "10KOhm" textlabel
Met3_10k_res = WITH TEXT met3res "10KOhm" textlabel
Diff_1k_res = WITH TEXT diffres "1KOhm" textlabel
Poly_1k_res = WITH TEXT polyres "1KOhm" textlabel
Pwell_1k_res = WITH TEXT pwellres "1KOhm" textlabel
Met1_1k_res = WITH TEXT met1res "1KOhm" textlabel
Met2_1k_res = WITH TEXT met2res "1KOhm" textlabel
Met3_1k_res = WITH TEXT met3res "1KOhm" textlabel
Diff_100k_res = (WITH TEXT diffres "100KOhm" textlabel) OR Diff_10k_res
Poly_100k_res = (WITH TEXT polyres "100KOhm" textlabel) OR Poly_10k_res
Pwell_100k_res = (WITH TEXT pwellres "100KOhm" textlabel) OR Pwell_10k_res
Met1_100k_res = (WITH TEXT met1res "100KOhm" textlabel) OR Met1_10k_res
Met2_100k_res = (WITH TEXT met2res "100KOhm" textlabel) OR Met2_10k_res
Met3_100k_res = (WITH TEXT met3res "100KOhm" textlabel) OR Met3_10k_res
Pwell_250_res = WITH TEXT pwellres "250Ohm" textlabel
Diff_250_res = WITH TEXT diffres "250Ohm" textlabel
Poly_250_res = WITH TEXT polyres "250Ohm" textlabel
Met1_250_res = WITH TEXT met1res "250Ohm" textlabel
Met2_250_res = WITH TEXT met2res "250Ohm" textlabel
Met3_250_res = WITH TEXT met3res "250Ohm" textlabel
Met1EsdResnoVD = Met1EsdRes NOT (xmtMet1EsdRes OR
(Met1_leaker OR
(Met1_bias OR Met1_openRes)))
Met2EsdResnoVD = Met2EsdRes NOT (xmtMet2EsdRes OR
(Met2_leaker OR
(Met2_bias OR Met2_openRes)))
Met3EsdResnoVD = Met3EsdRes NOT (xmtMet3EsdRes OR
(Met3_leaker OR
(Met3_bias OR Met3_openRes)))
Met1EsdRes_no100KOhm = Met1EsdResnoVD NOT Met1_100k_res
Met2EsdRes_no100KOhm = Met2EsdResnoVD NOT Met2_100k_res
Met3EsdRes_no100KOhm = Met3EsdResnoVD NOT Met3_100k_res
Met1EsdRes_no1KOhm = Met1EsdResnoVD NOT Met1_1k_res
Met2EsdRes_no1KOhm = Met2EsdResnoVD NOT Met2_1k_res
Met3EsdRes_no1KOhm = Met3EsdResnoVD NOT Met3_1k_res
Met1EsdRes_no250Ohm = Met1EsdResnoVD NOT Met1_250_res
Met2EsdRes_no250Ohm = Met2EsdResnoVD NOT Met2_250_res
Met3EsdRes_no250Ohm = Met3EsdResnoVD NOT Met3_250_res
ndiff_res = nDiffRes NOT (xmtnDiffRes OR
(Diff_leaker OR
(Diff_bias OR Diff_openRes)))
pdiff_res = pDiffRes NOT (xmtpDiffRes OR
(Diff_leaker OR
(Diff_bias OR Diff_openRes)))
ndiff_esdRes = (ndiff_res AND ESDID) NOT (xmtnDiffRes OR
(Diff_leaker OR
(Diff_bias OR Diff_openRes)))
pdiff_esdRes = (pdiff_res AND ESDID) NOT (xmtpDiffRes OR
(Diff_leaker OR
(Diff_bias OR Diff_openRes)))
pwell_res = pwellres NOT (xmtPwellRes OR
(Pwell_leaker OR
(Pwell_bias OR Pwell_openRes)))
poly_res = ResPoly NOT (xmtResPoly OR
(Poly_leaker OR
(Poly_bias OR Poly_openRes)))
poly_resNoEsd = (poly_res NOT ESDID) NOT (xmtResPoly OR
(Poly_leaker OR Poly_bias))
poly_esdRes = (poly_res AND ESDID) NOT (xmtResPoly OR
(Poly_leaker OR Poly_bias))
polyResEsdLib = (INSIDE CELL polyres "s8_esd_res75only" "s8_esd_res75only_small" "s8_esd_res75only_noshorts" "s8_esd_res75only_noshorts_nometal" "s8_esd_res250" "s8_esd_res250only" "s8_esd_res250only_small") NOT (xmtResPoly OR
(Poly_leaker OR Poly_bias))
lu4_ndiff_res = ndiff_res NOT Diff_100k_res
lu4_pdiff_res = pdiff_res NOT Diff_100k_res
lu4_ndiff_esdRes = ndiff_esdRes NOT Diff_100k_res
lu4_pdiff_esdRes = pdiff_esdRes NOT Diff_100k_res
lu4_pwell_res = pwell_res NOT Pwell_100k_res
lu4_poly_res = poly_res NOT Poly_100k_res
lu4_poly_esdRes = poly_esdRes NOT Poly_100k_res
lu4_ndiff_res250 = ndiff_res NOT Diff_250_res
lu4_pdiff_res250 = pdiff_res NOT Diff_250_res
lu4_ndiff_esdRes250 = ndiff_esdRes NOT Diff_250_res
lu4_pdiff_esdRes250 = pdiff_esdRes NOT Diff_250_res
lu4_pwell_res250 = pwell_res NOT Pwell_250_res
lu4_poly_res250 = poly_res NOT Poly_250_res
lu4_poly_esdRes250 = poly_esdRes NOT Poly_250_res
shv_ndiff_res = ndiff_res NOT Diff_1k_res
shv_pdiff_res = pdiff_res NOT Diff_1k_res
shv_ndiff_esdRes = ndiff_esdRes NOT Diff_1k_res
shv_pdiff_esdRes = pdiff_esdRes NOT Diff_1k_res
shv_pwell_res = pwell_res NOT Pwell_1k_res
shv_poly_res = poly_res NOT Poly_1k_res
shv_poly_esdRes = poly_esdRes NOT Poly_1k_res
Met4_leaker = WITH TEXT met4res "leaker" textlabel
Met4_openRes = WITH TEXT met4res "openRes" textlabel
Met4_bias = (WITH TEXT met4res "pwr_bias" textlabel) OR (WITH TEXT met4res "gnd_bias" textlabel)
Met4_100k_res = WITH TEXT met4res "100KOhm" textlabel
Met4_1k_res = WITH TEXT met4res "1KOhm" textlabel
Met4_250_res = WITH TEXT met4res "250Ohm" textlabel
Met4_75_res = WITH TEXT met4res "75Ohm" textlabel
Met4EsdResnoVD = Met4EsdRes NOT (xmtMet4EsdRes OR
(Met4_leaker OR
(Met4_bias OR Met4_openRes)))
Met4EsdRes_no100KOhm = Met4EsdResnoVD NOT Met4_100k_res
Met4EsdRes_no250Ohm = Met4EsdResnoVD NOT Met4_250_res
Met4EsdRes_no1KOhm = Met4EsdResnoVD NOT Met4_1k_res
Met5_leaker = WITH TEXT met5res "leaker" textlabel
Met5_openRes = WITH TEXT met5res "openRes" textlabel
Met5_bias = (WITH TEXT met5res "pwr_bias" textlabel) OR (WITH TEXT met5res "gnd_bias" textlabel)
Met5_100k_res = WITH TEXT met5res "100KOhm" textlabel
Met5_1k_res = WITH TEXT met5res "1KOhm" textlabel
Met5_250_res = WITH TEXT met5res "250Ohm" textlabel
Met5_75_res = WITH TEXT met5res "75Ohm" textlabel
Met5EsdResnoVD = Met5EsdRes NOT (xmtMet5EsdRes OR
(Met5_leaker OR
(Met5_bias OR Met5_openRes)))
Met5EsdRes_no100KOhm = Met5EsdResnoVD NOT Met5_100k_res
Met5EsdRes_no250Ohm = Met5EsdResnoVD NOT Met5_250_res
Met5EsdRes_no1KOhm = Met5EsdResnoVD NOT Met5_1k_res
/// CALconnectZone started - zoneName was "zone_9"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT NSRCDRN lu4_ndiff_esdRes
CONNECT PSRCDRN lu4_pdiff_esdRes
CONNECT NSRCDRN lu4_ndiff_res
CONNECT PSRCDRN lu4_pdiff_res
CONNECT PolyNoRes lu4_poly_esdRes
CONNECT PolyNoRes lu4_poly_res
CONNECT Met1 Met1EsdRes_no100KOhm
CONNECT Met2 Met2EsdRes_no100KOhm
CONNECT Met3 Met3EsdRes_no100KOhm
CONNECT isolatedSubNoPWR lu4_pwell_res
CONNECT Met4 Met4EsdRes_no100KOhm
CONNECT Met5 Met5EsdRes_no100KOhm
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_10
LU4_NSRCDRNspRes = NOT INTERACT (NSDsigPadConn OR (NET NSRCDRN "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad")) ENID
LU4_PSRCDRNspResNet = NOT INTERACT (NET PSRCDRN "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad") ENID
LU4_PSRCDRNspRes = PSDsigPadConn OR LU4_PSRCDRNspResNet
LU4_s8esdg4_cells = INSIDE CELL diffTap "s8esdg4_net_d1_420_aup" "s8esdg4_net_d2_360_sub_aup" "s8esdg4_net_d4_60_aup" "s8blerf_top" "s8fpafeg1_io_gnd2gnd_180x2_lv_dnwl_aup" "s8fpafeg1_io_gnd2gnd_240x1_lv_dnwl_aup" "s8fpafeg1_io_gnd2gnd_240x2_lv_dnwl_aup_tall" "s8usbpd_esd_cdm_uhv" "s8usbpd_csa_top" "s8usbpd_ngdo_top" "s8usbpdv2_csa_top" "s8usbpd_esd_21v_vbus_iec" "s8usbpdv2_20vconn_sw_300ma_ocp_switch2" "s8usbpdv2_esd_21v_hbm" "s8rf_n20vhv1_aup" "s8usbpdv2_csa_esd_hbm_21v_10x4" "s8usbpdv2_csa_esd_cdm_uhv" "s8usbpd_esd_shv_iec" "s8usbpd_esd_shv_sbu_iec" "s8usbpdv2_esd_shv_iec_sbu" "s8usbpd_pgdo_pu_top" "s8usbpd_pgdo_top" "s8usbpd_ea_top" "s8usbpdv2_20sbu_sw_ovp_ngate" "s8usbpdv2_20vconn_sw_300ma_ovp_ngate"
LU4_NTAPspRes = NOT INTERACT (NTAPsigPad OR (NET NTAP "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad")) ENID
LU4_PTAPspRes = NOT INTERACT (PTAPsigPad OR (NET PTAP "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad")) ENID
LU4_nwellSameNetTmp = INTERACT nwell LU4_PSRCDRNspResNet == 1 BY NET
LU4_nwellSameNetTmp2 = EXTERNAL LU4_nwellSameNetTmp [LU4_PSRCDRNspResNet] == 0 CONNECTED INSIDE ALSO
LU4_nwellSameNetTmp3 = LU4_PSRCDRNspResNet WITH EDGE LU4_nwellSameNetTmp2
LU4_nwellSameNet = INTERACT LU4_nwellSameNetTmp LU4_nwellSameNetTmp3
LU4_NSRCDRNspRes_pwell = STAMP (LU4_NSRCDRNspRes AND dnwell) BY NSRCDRN
LU4_NSRCDRNspRes_psub = LU4_NSRCDRNspRes NOT LU4_NSRCDRNspRes_pwell
LU4_PTAPspRes_pwell = STAMP (LU4_PTAPspRes AND dnwell) BY PTAP
PTAPnotSealDonut_nonIo = PTAPnotSealDonut NOT LU4_PTAPspRes
NTAPnotSealDonut_nonIo = NTAPnotSealDonut NOT LU4_NTAPspRes
PTAPnotSealDonut_nodnw_nonIo = PTAPnotSealDonut_nodnw NOT LU4_PTAPspRes
Nwell_LU4_PSRCDRNspRes = INTERACT Nwell LU4_PSRCDRNspRes
Nwell_LU4_NTAPspRes = INTERACT Nwell LU4_NTAPspRes
isoSub_LU4_NSRCDRNspRes = INTERACT isolatedSubNoPWR LU4_NSRCDRNspRes
isoSub_LU4_PTAPspRes_nodnw = NOT INTERACT (INTERACT isolatedSubNoPWR LU4_PTAPspRes) dnwell
isoSub_LU4_PTAPspRes_dnw = INTERACT (INTERACT isolatedSubNoPWR LU4_PTAPspRes) dnwell
LU4_PTAPspRes_PwellXmt = NET AREA RATIO LU4_PTAPspRes_pwell LU4_NSRCDRNspRes_pwell > 0 INSIDE OF LAYER dnwell
LU4_NTAPspRes_Xmt = LU4_NTAPspRes AND (INSIDE CELL tap "s8_esd_paddiode2pwr_100_hv" "s8_esd_paddiode2pwr_200_hv" "s8_esd_paddiode2pwr_300_hv")
LU4_PSRCDRNspRes_commonWell = LU4_PSRCDRNspRes AND (INTERACT Nwell_LU4_PSRCDRNspRes LU4_PSRCDRNspRes > 1)
LU4_NTAPspRes_commonWell = (LU4_NTAPspRes AND (INTERACT Nwell_LU4_NTAPspRes LU4_NTAPspRes > 1)) NOT LU4_NTAPspRes_Xmt
LU4_NSRCDRNspRes_commonSub = LU4_NSRCDRNspRes AND (INTERACT isoSub_LU4_NSRCDRNspRes LU4_NSRCDRNspRes > 1)
LU4_PTAPspRes_commonPWSub = (LU4_PTAPspRes AND (INTERACT isoSub_LU4_PTAPspRes_dnw LU4_PTAPspRes > 1)) NOT LU4_PTAPspRes_PwellXmt
LU4_PTAPspRes_commonNPWSub = LU4_PTAPspRes AND (INTERACT isoSub_LU4_PTAPspRes_nodnw LU4_PTAPspRes > 1)
LU4_PSRCDRNspRes_indWell = LU4_PSRCDRNspRes AND (INTERACT Nwell_LU4_PSRCDRNspRes LU4_PSRCDRNspRes == 1)
LU4_NTAPspRes_indWell = (LU4_NTAPspRes AND (INTERACT Nwell_LU4_NTAPspRes LU4_NTAPspRes == 1)) NOT LU4_NTAPspRes_Xmt
LU4_NSRCDRNspRes_indSub = LU4_NSRCDRNspRes AND (INTERACT isoSub_LU4_NSRCDRNspRes LU4_NSRCDRNspRes == 1)
LU4_PTAPspRes_indNPWSub = LU4_PTAPspRes AND (INTERACT isoSub_LU4_PTAPspRes_nodnw LU4_PTAPspRes == 1)
LU4_PTAPspRes_indPWSub = (LU4_PTAPspRes AND (INTERACT isoSub_LU4_PTAPspRes_dnw LU4_PTAPspRes == 1)) NOT LU4_PTAPspRes_PwellXmt
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_forIWPSD second:lu4_secondRingP_forIWPSD third:nil
/// Inner ring derivation
q0lu4_innerRingN_forIWPSD = COPY LU4_PSRCDRNspRes_indWell
q66NTAPnotSealDonut = DONUT NTAPnotSealDonut < 2
q67NTAPnotSealDonut = COPY q66NTAPnotSealDonut
q69NTAPnotSealDonut = (HOLES q67NTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingN_forIWPSD
q68NTAPnotSealDonut = COPY q69NTAPnotSealDonut
q71NTAPnotSealDonut = TOUCH q67NTAPnotSealDonut q68NTAPnotSealDonut
/// Second ring derivation
q66PTAPnotSealDonut = NOT INTERACT PTAPnotSealDonut q71NTAPnotSealDonut
q67PTAPnotSealDonut = DONUT q66PTAPnotSealDonut
q71PTAPnotSealDonut = COPY q67PTAPnotSealDonut
q70NTAPnotSealDonut = q68NTAPnotSealDonut NOT ENCLOSE q67PTAPnotSealDonut
q72NTAPnotSealDonut = TOUCH q71NTAPnotSealDonut q70NTAPnotSealDonut
q69PTAPnotSealDonut = (HOLES q71PTAPnotSealDonut) ENCLOSE q72NTAPnotSealDonut
q70PTAPnotSealDonut = ((q69PTAPnotSealDonut NOT q71PTAPnotSealDonut) NOT q72NTAPnotSealDonut) NOT q70NTAPnotSealDonut
q72PTAPnotSealDonut = TOUCH q70PTAPnotSealDonut q72NTAPnotSealDonut
q80PTAPnotSealDonut = TOUCH q71PTAPnotSealDonut q72PTAPnotSealDonut
q68PTAPnotSealDonut = HOLES q80PTAPnotSealDonut INNER
q79PTAPnotSealDonut = TOUCH q80PTAPnotSealDonut (q68PTAPnotSealDonut ENCLOSE q72NTAPnotSealDonut < 2)
lu4_innerRingN_forIWPSD = q72NTAPnotSealDonut INSIDE (HOLES q79PTAPnotSealDonut)
lu4_secondRingP_forIWPSD = COPY q79PTAPnotSealDonut
lu4_NinnerRegion_forIWPSD = TOUCH q70NTAPnotSealDonut lu4_innerRingN_forIWPSD
lu4_NinnerToSecReg_forIWPSD = TOUCH q72PTAPnotSealDonut lu4_innerRingN_forIWPSD
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_forISPTAP second:lu4_secondRingP_forISPTAP third:nil
/// Inner ring derivation
q0lu4_innerRingN_forISPTAP = COPY LU4_PTAPspRes_indNPWSub
q73NTAPnotSealDonut = DONUT NTAPnotSealDonut < 2
q74NTAPnotSealDonut = COPY q73NTAPnotSealDonut
q76NTAPnotSealDonut = (HOLES q74NTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingN_forISPTAP
q75NTAPnotSealDonut = COPY q76NTAPnotSealDonut
q78NTAPnotSealDonut = TOUCH q74NTAPnotSealDonut q75NTAPnotSealDonut
/// Second ring derivation
q0PTAPnotSealDonut_nonIo = NOT INTERACT PTAPnotSealDonut_nonIo q78NTAPnotSealDonut
q1PTAPnotSealDonut_nonIo = DONUT q0PTAPnotSealDonut_nonIo
q5PTAPnotSealDonut_nonIo = COPY q1PTAPnotSealDonut_nonIo
q77NTAPnotSealDonut = q75NTAPnotSealDonut NOT ENCLOSE q1PTAPnotSealDonut_nonIo
q79NTAPnotSealDonut = TOUCH q78NTAPnotSealDonut q77NTAPnotSealDonut
q3PTAPnotSealDonut_nonIo = (HOLES q5PTAPnotSealDonut_nonIo) ENCLOSE q79NTAPnotSealDonut
q4PTAPnotSealDonut_nonIo = ((q3PTAPnotSealDonut_nonIo NOT q5PTAPnotSealDonut_nonIo) NOT q79NTAPnotSealDonut) NOT q77NTAPnotSealDonut
q6PTAPnotSealDonut_nonIo = TOUCH q4PTAPnotSealDonut_nonIo q79NTAPnotSealDonut
q14PTAPnotSealDonut_nonIo = TOUCH q5PTAPnotSealDonut_nonIo q6PTAPnotSealDonut_nonIo
q2PTAPnotSealDonut_nonIo = HOLES q14PTAPnotSealDonut_nonIo INNER
q13PTAPnotSealDonut_nonIo = TOUCH q14PTAPnotSealDonut_nonIo (q2PTAPnotSealDonut_nonIo ENCLOSE q79NTAPnotSealDonut < 2)
lu4_innerRingN_forISPTAP = q79NTAPnotSealDonut INSIDE (HOLES q13PTAPnotSealDonut_nonIo)
lu4_secondRingP_forISPTAP = COPY q13PTAPnotSealDonut_nonIo
lu4_NinnerRegion_forISPTAP = TOUCH q77NTAPnotSealDonut lu4_innerRingN_forISPTAP
lu4_NinnerToSecReg_forISPTAP = TOUCH q6PTAPnotSealDonut_nonIo lu4_innerRingN_forISPTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_forIPWSPTAP second:lu4_secondRingP_forIPWSPTAP third:nil
/// Inner ring derivation
q0lu4_innerRingN_forIPWSPTAP = COPY LU4_PTAPspRes_indPWSub
q80NTAPnotSealDonut = DONUT NTAPnotSealDonut < 2
q81NTAPnotSealDonut = COPY q80NTAPnotSealDonut
q83NTAPnotSealDonut = (HOLES q81NTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingN_forIPWSPTAP
q82NTAPnotSealDonut = COPY q83NTAPnotSealDonut
q85NTAPnotSealDonut = TOUCH q81NTAPnotSealDonut q82NTAPnotSealDonut
/// Second ring derivation
q0PTAPnotSealDonut_nodnw_nonIo = NOT INTERACT PTAPnotSealDonut_nodnw_nonIo q85NTAPnotSealDonut
q1PTAPnotSealDonut_nodnw_nonIo = DONUT q0PTAPnotSealDonut_nodnw_nonIo
q5PTAPnotSealDonut_nodnw_nonIo = COPY q1PTAPnotSealDonut_nodnw_nonIo
q84NTAPnotSealDonut = q82NTAPnotSealDonut NOT ENCLOSE q1PTAPnotSealDonut_nodnw_nonIo
q86NTAPnotSealDonut = TOUCH q85NTAPnotSealDonut q84NTAPnotSealDonut
q3PTAPnotSealDonut_nodnw_nonIo = (HOLES q5PTAPnotSealDonut_nodnw_nonIo) ENCLOSE q86NTAPnotSealDonut
q4PTAPnotSealDonut_nodnw_nonIo = ((q3PTAPnotSealDonut_nodnw_nonIo NOT q5PTAPnotSealDonut_nodnw_nonIo) NOT q86NTAPnotSealDonut) NOT q84NTAPnotSealDonut
q6PTAPnotSealDonut_nodnw_nonIo = TOUCH q4PTAPnotSealDonut_nodnw_nonIo q86NTAPnotSealDonut
q14PTAPnotSealDonut_nodnw_nonIo = TOUCH q5PTAPnotSealDonut_nodnw_nonIo q6PTAPnotSealDonut_nodnw_nonIo
q2PTAPnotSealDonut_nodnw_nonIo = HOLES q14PTAPnotSealDonut_nodnw_nonIo INNER
q13PTAPnotSealDonut_nodnw_nonIo = TOUCH q14PTAPnotSealDonut_nodnw_nonIo (q2PTAPnotSealDonut_nodnw_nonIo ENCLOSE q86NTAPnotSealDonut < 2)
lu4_innerRingN_forIPWSPTAP = q86NTAPnotSealDonut INSIDE (HOLES q13PTAPnotSealDonut_nodnw_nonIo)
lu4_secondRingP_forIPWSPTAP = COPY q13PTAPnotSealDonut_nodnw_nonIo
lu4_NinnerRegion_forIPWSPTAP = TOUCH q84NTAPnotSealDonut lu4_innerRingN_forIPWSPTAP
lu4_NinnerToSecReg_forIPWSPTAP = TOUCH q6PTAPnotSealDonut_nodnw_nonIo lu4_innerRingN_forIPWSPTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_forCWPSD second:lu4_secondRingP_forCWPSD third:nil
/// Inner ring derivation
q0lu4_innerRingN_forCWPSD = COPY LU4_PSRCDRNspRes_commonWell
q87NTAPnotSealDonut = DONUT NTAPnotSealDonut
q88NTAPnotSealDonut = COPY q87NTAPnotSealDonut
q90NTAPnotSealDonut = (HOLES q88NTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingN_forCWPSD
q89NTAPnotSealDonut = COPY q90NTAPnotSealDonut
q92NTAPnotSealDonut = TOUCH q88NTAPnotSealDonut q89NTAPnotSealDonut
/// Second ring derivation
q81PTAPnotSealDonut = NOT INTERACT PTAPnotSealDonut q92NTAPnotSealDonut
q82PTAPnotSealDonut = DONUT q81PTAPnotSealDonut
q86PTAPnotSealDonut = COPY q82PTAPnotSealDonut
q91NTAPnotSealDonut = q89NTAPnotSealDonut NOT ENCLOSE q82PTAPnotSealDonut
q93NTAPnotSealDonut = TOUCH q92NTAPnotSealDonut q91NTAPnotSealDonut
q84PTAPnotSealDonut = (HOLES q86PTAPnotSealDonut) ENCLOSE q93NTAPnotSealDonut
q85PTAPnotSealDonut = ((q84PTAPnotSealDonut NOT q86PTAPnotSealDonut) NOT q93NTAPnotSealDonut) NOT q91NTAPnotSealDonut
q87PTAPnotSealDonut = TOUCH q85PTAPnotSealDonut q93NTAPnotSealDonut
q95PTAPnotSealDonut = TOUCH q86PTAPnotSealDonut q87PTAPnotSealDonut
q83PTAPnotSealDonut = HOLES q95PTAPnotSealDonut INNER
q94PTAPnotSealDonut = TOUCH q95PTAPnotSealDonut (q83PTAPnotSealDonut ENCLOSE q93NTAPnotSealDonut)
lu4_innerRingN_forCWPSD = q93NTAPnotSealDonut INSIDE (HOLES q94PTAPnotSealDonut)
lu4_secondRingP_forCWPSD = COPY q94PTAPnotSealDonut
lu4_NinnerRegion_forCWPSD = TOUCH q91NTAPnotSealDonut lu4_innerRingN_forCWPSD
lu4_NinnerToSecReg_forCWPSD = TOUCH q87PTAPnotSealDonut lu4_innerRingN_forCWPSD
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_forCSPTAP second:lu4_secondRingP_forCSPTAP third:nil
/// Inner ring derivation
q0lu4_innerRingN_forCSPTAP = COPY LU4_PTAPspRes_commonNPWSub
q94NTAPnotSealDonut = DONUT NTAPnotSealDonut < 2
q95NTAPnotSealDonut = COPY q94NTAPnotSealDonut
q97NTAPnotSealDonut = (HOLES q95NTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingN_forCSPTAP
q96NTAPnotSealDonut = COPY q97NTAPnotSealDonut
q99NTAPnotSealDonut = TOUCH q95NTAPnotSealDonut q96NTAPnotSealDonut
/// Second ring derivation
q15PTAPnotSealDonut_nonIo = NOT INTERACT PTAPnotSealDonut_nonIo q99NTAPnotSealDonut
q16PTAPnotSealDonut_nonIo = DONUT q15PTAPnotSealDonut_nonIo
q20PTAPnotSealDonut_nonIo = COPY q16PTAPnotSealDonut_nonIo
q98NTAPnotSealDonut = q96NTAPnotSealDonut NOT ENCLOSE q16PTAPnotSealDonut_nonIo
q100NTAPnotSealDonut = TOUCH q99NTAPnotSealDonut q98NTAPnotSealDonut
q18PTAPnotSealDonut_nonIo = (HOLES q20PTAPnotSealDonut_nonIo) ENCLOSE q100NTAPnotSealDonut
q19PTAPnotSealDonut_nonIo = ((q18PTAPnotSealDonut_nonIo NOT q20PTAPnotSealDonut_nonIo) NOT q100NTAPnotSealDonut) NOT q98NTAPnotSealDonut
q21PTAPnotSealDonut_nonIo = TOUCH q19PTAPnotSealDonut_nonIo q100NTAPnotSealDonut
q29PTAPnotSealDonut_nonIo = TOUCH q20PTAPnotSealDonut_nonIo q21PTAPnotSealDonut_nonIo
q17PTAPnotSealDonut_nonIo = HOLES q29PTAPnotSealDonut_nonIo INNER
q28PTAPnotSealDonut_nonIo = TOUCH q29PTAPnotSealDonut_nonIo (q17PTAPnotSealDonut_nonIo ENCLOSE q100NTAPnotSealDonut < 2)
lu4_innerRingN_forCSPTAP = q100NTAPnotSealDonut INSIDE (HOLES q28PTAPnotSealDonut_nonIo)
lu4_secondRingP_forCSPTAP = COPY q28PTAPnotSealDonut_nonIo
lu4_NinnerRegion_forCSPTAP = TOUCH q98NTAPnotSealDonut lu4_innerRingN_forCSPTAP
lu4_NinnerToSecReg_forCSPTAP = TOUCH q21PTAPnotSealDonut_nonIo lu4_innerRingN_forCSPTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_forCPWSPTAP second:lu4_secondRingP_forCPWSPTAP third:nil
/// Inner ring derivation
q0lu4_innerRingN_forCPWSPTAP = COPY LU4_PTAPspRes_commonPWSub
q101NTAPnotSealDonut = DONUT NTAPnotSealDonut < 2
q102NTAPnotSealDonut = COPY q101NTAPnotSealDonut
q104NTAPnotSealDonut = (HOLES q102NTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingN_forCPWSPTAP
q103NTAPnotSealDonut = COPY q104NTAPnotSealDonut
q106NTAPnotSealDonut = TOUCH q102NTAPnotSealDonut q103NTAPnotSealDonut
/// Second ring derivation
q15PTAPnotSealDonut_nodnw_nonIo = NOT INTERACT PTAPnotSealDonut_nodnw_nonIo q106NTAPnotSealDonut
q16PTAPnotSealDonut_nodnw_nonIo = DONUT q15PTAPnotSealDonut_nodnw_nonIo
q20PTAPnotSealDonut_nodnw_nonIo = COPY q16PTAPnotSealDonut_nodnw_nonIo
q105NTAPnotSealDonut = q103NTAPnotSealDonut NOT ENCLOSE q16PTAPnotSealDonut_nodnw_nonIo
q107NTAPnotSealDonut = TOUCH q106NTAPnotSealDonut q105NTAPnotSealDonut
q18PTAPnotSealDonut_nodnw_nonIo = (HOLES q20PTAPnotSealDonut_nodnw_nonIo) ENCLOSE q107NTAPnotSealDonut
q19PTAPnotSealDonut_nodnw_nonIo = ((q18PTAPnotSealDonut_nodnw_nonIo NOT q20PTAPnotSealDonut_nodnw_nonIo) NOT q107NTAPnotSealDonut) NOT q105NTAPnotSealDonut
q21PTAPnotSealDonut_nodnw_nonIo = TOUCH q19PTAPnotSealDonut_nodnw_nonIo q107NTAPnotSealDonut
q29PTAPnotSealDonut_nodnw_nonIo = TOUCH q20PTAPnotSealDonut_nodnw_nonIo q21PTAPnotSealDonut_nodnw_nonIo
q17PTAPnotSealDonut_nodnw_nonIo = HOLES q29PTAPnotSealDonut_nodnw_nonIo INNER
q28PTAPnotSealDonut_nodnw_nonIo = TOUCH q29PTAPnotSealDonut_nodnw_nonIo (q17PTAPnotSealDonut_nodnw_nonIo ENCLOSE q107NTAPnotSealDonut < 2)
lu4_innerRingN_forCPWSPTAP = q107NTAPnotSealDonut INSIDE (HOLES q28PTAPnotSealDonut_nodnw_nonIo)
lu4_secondRingP_forCPWSPTAP = COPY q28PTAPnotSealDonut_nodnw_nonIo
lu4_NinnerRegion_forCPWSPTAP = TOUCH q105NTAPnotSealDonut lu4_innerRingN_forCPWSPTAP
lu4_NinnerToSecReg_forCPWSPTAP = TOUCH q21PTAPnotSealDonut_nodnw_nonIo lu4_innerRingN_forCPWSPTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_forISNSD second:lu4_secondRingN_forISNSD third:nil
/// Inner ring derivation
q0lu4_innerRingP_forISNSD = COPY LU4_NSRCDRNspRes_indSub
q96PTAPnotSealDonut = DONUT PTAPnotSealDonut < 2
q97PTAPnotSealDonut = COPY q96PTAPnotSealDonut
q99PTAPnotSealDonut = (HOLES q97PTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingP_forISNSD
q98PTAPnotSealDonut = COPY q99PTAPnotSealDonut
q101PTAPnotSealDonut = TOUCH q97PTAPnotSealDonut q98PTAPnotSealDonut
/// Second ring derivation
q108NTAPnotSealDonut = NOT INTERACT NTAPnotSealDonut q101PTAPnotSealDonut
q109NTAPnotSealDonut = DONUT q108NTAPnotSealDonut
q113NTAPnotSealDonut = COPY q109NTAPnotSealDonut
q100PTAPnotSealDonut = q98PTAPnotSealDonut NOT ENCLOSE q109NTAPnotSealDonut
q102PTAPnotSealDonut = TOUCH q101PTAPnotSealDonut q100PTAPnotSealDonut
q111NTAPnotSealDonut = (HOLES q113NTAPnotSealDonut) ENCLOSE q102PTAPnotSealDonut
q112NTAPnotSealDonut = ((q111NTAPnotSealDonut NOT q113NTAPnotSealDonut) NOT q102PTAPnotSealDonut) NOT q100PTAPnotSealDonut
q114NTAPnotSealDonut = TOUCH q112NTAPnotSealDonut q102PTAPnotSealDonut
q122NTAPnotSealDonut = TOUCH q113NTAPnotSealDonut q114NTAPnotSealDonut
q110NTAPnotSealDonut = HOLES q122NTAPnotSealDonut INNER
q121NTAPnotSealDonut = TOUCH q122NTAPnotSealDonut (q110NTAPnotSealDonut ENCLOSE q102PTAPnotSealDonut < 2)
lu4_innerRingP_forISNSD = q102PTAPnotSealDonut INSIDE (HOLES q121NTAPnotSealDonut)
lu4_secondRingN_forISNSD = COPY q121NTAPnotSealDonut
lu4_PinnerRegion_forISNSD = TOUCH q100PTAPnotSealDonut lu4_innerRingP_forISNSD
lu4_PinnerToSecReg_forISNSD = TOUCH q114NTAPnotSealDonut lu4_innerRingP_forISNSD
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_forIWNTAP second:lu4_secondRingN_forIWNTAP third:nil
/// Inner ring derivation
q0lu4_innerRingP_forIWNTAP = COPY LU4_NTAPspRes_indWell
q103PTAPnotSealDonut = DONUT PTAPnotSealDonut < 2
q104PTAPnotSealDonut = COPY q103PTAPnotSealDonut
q106PTAPnotSealDonut = (HOLES q104PTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingP_forIWNTAP
q105PTAPnotSealDonut = COPY q106PTAPnotSealDonut
q108PTAPnotSealDonut = TOUCH q104PTAPnotSealDonut q105PTAPnotSealDonut
/// Second ring derivation
q0NTAPnotSealDonut_nonIo = NOT INTERACT NTAPnotSealDonut_nonIo q108PTAPnotSealDonut
q1NTAPnotSealDonut_nonIo = DONUT q0NTAPnotSealDonut_nonIo
q5NTAPnotSealDonut_nonIo = COPY q1NTAPnotSealDonut_nonIo
q107PTAPnotSealDonut = q105PTAPnotSealDonut NOT ENCLOSE q1NTAPnotSealDonut_nonIo
q109PTAPnotSealDonut = TOUCH q108PTAPnotSealDonut q107PTAPnotSealDonut
q3NTAPnotSealDonut_nonIo = (HOLES q5NTAPnotSealDonut_nonIo) ENCLOSE q109PTAPnotSealDonut
q4NTAPnotSealDonut_nonIo = ((q3NTAPnotSealDonut_nonIo NOT q5NTAPnotSealDonut_nonIo) NOT q109PTAPnotSealDonut) NOT q107PTAPnotSealDonut
q6NTAPnotSealDonut_nonIo = TOUCH q4NTAPnotSealDonut_nonIo q109PTAPnotSealDonut
q14NTAPnotSealDonut_nonIo = TOUCH q5NTAPnotSealDonut_nonIo q6NTAPnotSealDonut_nonIo
q2NTAPnotSealDonut_nonIo = HOLES q14NTAPnotSealDonut_nonIo INNER
q13NTAPnotSealDonut_nonIo = TOUCH q14NTAPnotSealDonut_nonIo (q2NTAPnotSealDonut_nonIo ENCLOSE q109PTAPnotSealDonut < 2)
lu4_innerRingP_forIWNTAP = q109PTAPnotSealDonut INSIDE (HOLES q13NTAPnotSealDonut_nonIo)
lu4_secondRingN_forIWNTAP = COPY q13NTAPnotSealDonut_nonIo
lu4_PinnerRegion_forIWNTAP = TOUCH q107PTAPnotSealDonut lu4_innerRingP_forIWNTAP
lu4_PinnerToSecReg_forIWNTAP = TOUCH q6NTAPnotSealDonut_nonIo lu4_innerRingP_forIWNTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_forCSNSD second:lu4_secondRingN_forCSNSD third:nil
/// Inner ring derivation
q0lu4_innerRingP_forCSNSD = COPY LU4_NSRCDRNspRes_commonSub
q110PTAPnotSealDonut = DONUT PTAPnotSealDonut
q111PTAPnotSealDonut = COPY q110PTAPnotSealDonut
q113PTAPnotSealDonut = (HOLES q111PTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingP_forCSNSD
q112PTAPnotSealDonut = COPY q113PTAPnotSealDonut
q115PTAPnotSealDonut = TOUCH q111PTAPnotSealDonut q112PTAPnotSealDonut
/// Second ring derivation
q123NTAPnotSealDonut = NOT INTERACT NTAPnotSealDonut q115PTAPnotSealDonut
q124NTAPnotSealDonut = DONUT q123NTAPnotSealDonut
q128NTAPnotSealDonut = COPY q124NTAPnotSealDonut
q114PTAPnotSealDonut = q112PTAPnotSealDonut NOT ENCLOSE q124NTAPnotSealDonut
q116PTAPnotSealDonut = TOUCH q115PTAPnotSealDonut q114PTAPnotSealDonut
q126NTAPnotSealDonut = (HOLES q128NTAPnotSealDonut) ENCLOSE q116PTAPnotSealDonut
q127NTAPnotSealDonut = ((q126NTAPnotSealDonut NOT q128NTAPnotSealDonut) NOT q116PTAPnotSealDonut) NOT q114PTAPnotSealDonut
q129NTAPnotSealDonut = TOUCH q127NTAPnotSealDonut q116PTAPnotSealDonut
q137NTAPnotSealDonut = TOUCH q128NTAPnotSealDonut q129NTAPnotSealDonut
q125NTAPnotSealDonut = HOLES q137NTAPnotSealDonut INNER
q136NTAPnotSealDonut = TOUCH q137NTAPnotSealDonut (q125NTAPnotSealDonut ENCLOSE q116PTAPnotSealDonut)
lu4_innerRingP_forCSNSD = q116PTAPnotSealDonut INSIDE (HOLES q136NTAPnotSealDonut)
lu4_secondRingN_forCSNSD = COPY q136NTAPnotSealDonut
lu4_PinnerRegion_forCSNSD = TOUCH q114PTAPnotSealDonut lu4_innerRingP_forCSNSD
lu4_PinnerToSecReg_forCSNSD = TOUCH q129NTAPnotSealDonut lu4_innerRingP_forCSNSD
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_forCWNTAP second:lu4_secondRingN_forCWNTAP third:nil
/// Inner ring derivation
q0lu4_innerRingP_forCWNTAP = COPY LU4_NTAPspRes_commonWell
q117PTAPnotSealDonut = DONUT PTAPnotSealDonut
q118PTAPnotSealDonut = COPY q117PTAPnotSealDonut
q120PTAPnotSealDonut = (HOLES q118PTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingP_forCWNTAP
q119PTAPnotSealDonut = COPY q120PTAPnotSealDonut
q122PTAPnotSealDonut = TOUCH q118PTAPnotSealDonut q119PTAPnotSealDonut
/// Second ring derivation
q15NTAPnotSealDonut_nonIo = NOT INTERACT NTAPnotSealDonut_nonIo q122PTAPnotSealDonut
q16NTAPnotSealDonut_nonIo = DONUT q15NTAPnotSealDonut_nonIo < 2
q20NTAPnotSealDonut_nonIo = COPY q16NTAPnotSealDonut_nonIo
q121PTAPnotSealDonut = q119PTAPnotSealDonut NOT ENCLOSE q16NTAPnotSealDonut_nonIo
q123PTAPnotSealDonut = TOUCH q122PTAPnotSealDonut q121PTAPnotSealDonut
q18NTAPnotSealDonut_nonIo = (HOLES q20NTAPnotSealDonut_nonIo) ENCLOSE q123PTAPnotSealDonut
q19NTAPnotSealDonut_nonIo = ((q18NTAPnotSealDonut_nonIo NOT q20NTAPnotSealDonut_nonIo) NOT q123PTAPnotSealDonut) NOT q121PTAPnotSealDonut
q21NTAPnotSealDonut_nonIo = TOUCH q19NTAPnotSealDonut_nonIo q123PTAPnotSealDonut
q29NTAPnotSealDonut_nonIo = TOUCH q20NTAPnotSealDonut_nonIo q21NTAPnotSealDonut_nonIo
q17NTAPnotSealDonut_nonIo = HOLES q29NTAPnotSealDonut_nonIo INNER
q28NTAPnotSealDonut_nonIo = TOUCH q29NTAPnotSealDonut_nonIo (q17NTAPnotSealDonut_nonIo ENCLOSE q123PTAPnotSealDonut)
lu4_innerRingP_forCWNTAP = q123PTAPnotSealDonut INSIDE (HOLES q28NTAPnotSealDonut_nonIo)
lu4_secondRingN_forCWNTAP = COPY q28NTAPnotSealDonut_nonIo
lu4_PinnerRegion_forCWNTAP = TOUCH q121PTAPnotSealDonut lu4_innerRingP_forCWNTAP
lu4_PinnerToSecReg_forCWNTAP = TOUCH q21NTAPnotSealDonut_nonIo lu4_innerRingP_forCWNTAP
/// CALderiveGuardRings complete
disallow_PSD_PTAP_commonRing = (TOUCH lu4_secondRingP_forIWPSD (INTERACT (INTERACT (HOLES lu4_secondRingP_forIWPSD) (LU4_PTAPspRes_indPWSub OR LU4_PTAPspRes_indNPWSub)) LU4_PSRCDRNspRes_indWell)) NOT LU4_s8esdg4_cells
needGR_LU4_PSRCDRNspRes_indWell = LU4_PSRCDRNspRes_indWell NOT (LU4_s8esdg4_cells OR lu4_NinnerRegion_forIWPSD)
disallow_PTAP_PSD_commonRing = (TOUCH lu4_secondRingP_forISPTAP (INTERACT (INTERACT (HOLES lu4_secondRingP_forISPTAP) LU4_PSRCDRNspRes_indWell) (LU4_PTAPspRes_indPWSub OR LU4_PTAPspRes_indNPWSub))) NOT LU4_s8esdg4_cells
needGR_LU4_PTAPspRes_indNPWSub = LU4_PTAPspRes_indNPWSub NOT (LU4_s8esdg4_cells OR lu4_NinnerRegion_forISPTAP)
needGR_LU4_PTAPspRes_indPWSub = LU4_PTAPspRes_indPWSub NOT (LU4_s8esdg4_cells OR lu4_NinnerRegion_forIPWSPTAP)
needGR_LU4_PSRCDRNspRes_commonWell = LU4_PSRCDRNspRes_commonWell NOT (LU4_s8esdg4_cells OR lu4_NinnerRegion_forCWPSD)
needGR_LU4_PTAPspRes_commonNPWSub = LU4_PTAPspRes_commonNPWSub NOT (LU4_s8esdg4_cells OR lu4_NinnerRegion_forCSPTAP)
needGR_LU4_PTAPspRes_commonPWSub = LU4_PTAPspRes_commonPWSub NOT (LU4_s8esdg4_cells OR lu4_NinnerRegion_forCPWSPTAP)
disallow_NSD_NTAP_commonRing = (TOUCH lu4_secondRingN_forISNSD (INTERACT (INTERACT (HOLES lu4_secondRingN_forISNSD) LU4_NTAPspRes_indWell) LU4_NSRCDRNspRes_indSub)) NOT LU4_s8esdg4_cells
needGR_LU4_NSRCDRNspRes_indSub = LU4_NSRCDRNspRes_indSub NOT (LU4_s8esdg4_cells OR lu4_PinnerRegion_forISNSD)
disallow_NTAP_NSD_commonRing = (TOUCH lu4_secondRingN_forIWNTAP (INTERACT (INTERACT (HOLES lu4_secondRingN_forIWNTAP) LU4_NSRCDRNspRes_indSub) LU4_NTAPspRes_indWell)) NOT LU4_s8esdg4_cells
needGR_LU4_NTAPspRes_indWell = LU4_NTAPspRes_indWell NOT (LU4_s8esdg4_cells OR lu4_PinnerRegion_forIWNTAP)
disallow_NTAP_NTAP_commonRing = (TOUCH lu4_innerRingP_forIWNTAP (INTERACT lu4_PinnerRegion_forIWNTAP LU4_NTAPspRes_indWell > 1)) NOT LU4_s8esdg4_cells
needGR_LU4_NSRCDRNspRes_commonSub = LU4_NSRCDRNspRes_commonSub NOT (LU4_s8esdg4_cells OR lu4_PinnerRegion_forCSNSD)
needGR_LU4_NTAPspRes_commonWell = LU4_NTAPspRes_commonWell NOT (LU4_s8esdg4_cells OR lu4_PinnerRegion_forCWNTAP)
"r_97_lu.4.1.1a" {
@ lu.4.1.1a: Pdiff connected to signal pad and ptap connected to signal pad cannot have a common outer guard ring
COPY disallow_PSD_PTAP_commonRing
}
"r_98_lu.4.1.1a/c/e" {
@ lu.4.1.1a/c/e: Pdiff connected to signal pad must have ntap inner ring and ptap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_PSRCDRNspRes_indWell
}
"r_99_lu.4.1.1a" {
@ lu.4.1.1a: Ptap connected to signal pad and pdiff connected to signal pad cannot have a common outer guard ring
COPY disallow_PTAP_PSD_commonRing
}
"r_100_lu.4.1.1a/c/e" {
@ lu.4.1.1a/c/e: Ptap connected to signal pad must have ntap inner ring and ptap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_PTAPspRes_indNPWSub
}
"r_101_lu.4.1.1a/c/e" {
@ lu.4.1.1a/c/e: Ptap in pwell connected to signal pad must have ntap inner ring and ptap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_PTAPspRes_indPWSub
}
"r_102_lu.4.1.1b" {
@ lu.4.1.1b: Pdiffs connected to signal pad in common well must have ntap inner ring and ptap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_PSRCDRNspRes_commonWell
}
"r_103_lu.4.1.1b" {
@ lu.4.1.1b: Ptaps connected to signal pad in common substrate must have ntap inner ring and ptap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_PTAPspRes_commonNPWSub
}
"r_104_lu.4.1.1b" {
@ lu.4.1.1b: Ptaps in pwell connected to signal pad in common pwell must have ntap inner ring and ptap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_PTAPspRes_commonPWSub
}
"r_105_lu.4.1.1g" {
@ lu.4.1.1g: Ndiff connected to signal pad and ntap connected to signal pad cannot have a common outer guard ring
COPY disallow_NSD_NTAP_commonRing
}
"r_106_lu.4.1.1g/c/e" {
@ lu.4.1.1g/c/e: Ndiff connected to signal pad must have a ptap inner ring and ntap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_NSRCDRNspRes_indSub
}
"r_107_lu.4.1.1g" {
@ lu.4.1.1g: Ntap connected to signal pad and Ndiff connected to signal pad cannot have a common outer guardring
COPY disallow_NTAP_NSD_commonRing
}
"r_108_lu.4.1.1g/c/e" {
@ lu.4.1.1g/c/e: Ntap connected to signal pad must have a ptap inner ring and ntap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_NTAPspRes_indWell
}
"r_109_lu.4.1.1g" {
@ lu.4.1.1g: Two Ntaps connected to signal pad cannot be within common inner and outer guardrings
COPY disallow_NTAP_NTAP_commonRing
}
"r_110_lu.4.1.1h" {
@ lu.4.1.1h: Ndiff connected to signal pad in common pwell must have ptap inner ring and outer ntap ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_NSRCDRNspRes_commonSub
}
"r_111_lu.4.1.1h" {
@ lu.4.1.1h: Ntap connected to signal pad in common well must have ptap inner ring and ntap outer ring. Refer MTDR for sharing restrictions
COPY needGR_LU4_NTAPspRes_commonWell
}
/// CALconnectZone started - zoneName was "zone_10"
DISCONNECT
CONNECT nwell NTAP
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT NSRCDRN lu4_ndiff_esdRes250
CONNECT PSRCDRN lu4_pdiff_esdRes250
CONNECT NSRCDRN lu4_ndiff_res250
CONNECT PSRCDRN lu4_pdiff_res250
CONNECT PolyNoRes lu4_poly_esdRes250
CONNECT PolyNoRes lu4_poly_res250
CONNECT Met1 Met1EsdRes_no250Ohm
CONNECT Met2 Met2EsdRes_no250Ohm
CONNECT Met3 Met3EsdRes_no250Ohm
CONNECT isolatedSubNoPWR lu4_pwell_res250
CONNECT Met4 Met4EsdRes_no250Ohm
CONNECT Met5 Met5EsdRes_no250Ohm
CONNECT paddg Met5
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl paddg BY pmm
CONNECT rdl pad BY pmm
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_11
LU4_nwellVssConn = NET nwell "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
dnwellConn = STAMP dnwANDnwell by nwell
LU4_ExemptNwell = INSIDE CELL nwell "s8usbpd_amux_denfet_top"
dnwellVss = (NOT INTERACT (NET AREA RATIO dnwellConn LU4_nwellVssConn > 0) dnwSHVsrcDRN) NOT LU4_ExemptNwell
"r_112_lu.4.2.1b" {
@ lu.4.2.1b: Grounded deep nwell is not allowed
COPY dnwellVss
}
poly_esdRes_75 = EXTENT CELL "s8_esd_res75only"
lu11_3_poly_res = poly_res NOT poly_esdRes_75
lu11_3_poly_esdRes = poly_esdRes NOT poly_esdRes_75
/// CALconnectZone started - zoneName was "zone_11"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT NSRCDRN ndiff_esdRes
CONNECT PSRCDRN pdiff_esdRes
CONNECT NSRCDRN ndiff_res
CONNECT PSRCDRN pdiff_res
CONNECT Met1 Met1EsdResnoVD
CONNECT Met2 Met2EsdResnoVD
CONNECT Met3 Met3EsdResnoVD
CONNECT isolatedSubNoPWR pwell_res
CONNECT Met4 Met4EsdResnoVD
CONNECT Met5 Met5EsdResnoVD
CONNECT PolyNoRes lu11_3_poly_res
CONNECT PolyNoRes lu11_3_poly_esdRes
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_12
M5RDLpad5x5 = RECTANGLE (pad AND
(met5 AND
(rdl AND pmm))) == 5.0 BY == 5.0
bondpad = pad NOT M5RDLpad5x5
unlistedPad = NOT NET bondpad "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad" "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio" "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
"r_113_lu.11.3" {
@ lu.11.3: Top-level pad is not listed to latchup
COPY unlistedPad
}
LU5_nWellExtVcc_resShorted = NET nwell "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
met2ConVccSPwr = NET AREA RATIO met2 switched_intPower_met1 > 0
met1ConVccSPwr = NET AREA RATIO met1 switched_intPower_met1 > 0
li1ConVccSPwr = NET AREA RATIO li1 switched_intPower_met1 > 0
met2ConVss = NET met2 "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
met1ConVss = NET met1 "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
li1ConVss = NET li1 "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
met2ConVcc = NET met2 "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
met1ConVcc = NET met1 "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
li1ConVcc = NET li1 "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
LU5_nWellNonVcc_resShorted = NOT NET nwell "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
LU5_nWellNonVcc = LU5_nWellNonVcc_resShorted OR (LU5_nWellExtVcc_resShorted NOT LU5_nWellExtVcc_resOpen)
LU5_AtRisk_NonVccNwell = COPY 4020
LU5_pDiffExtVcc_inAtRiskNonVccNwell = COPY 4021
/// CALconnectZone started - zoneName was "zone_12"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT LU5_pDiffExtVcc_inAtRiskNonVccNwell PSRCDRN
CONNECT LU5_AtRisk_NonVccNwell NTAP
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_13
LU5_pDiffVccOrIo_conn_nwellNonVcc = NET AREA RATIO LU5_pDiffExtVcc_inAtRiskNonVccNwell LU5_AtRisk_NonVccNwell > 0 INSIDE OF LAYER LU5_nWellNonVcc
LU5_nonExemptPdiff = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT LU5_pDiffVccOrIo_conn_nwellNonVcc
LU5_nonExemptARNonVccNwell = INTERACT LU5_AtRisk_NonVccNwell LU5_nonExemptPdiff
LU5_ExemptARNonVccNwell_1 = (INTERACT LU5_AtRisk_NonVccNwell LU5_pDiffVccOrIo_conn_nwellNonVcc) NOT LU5_nonExemptARNonVccNwell
LU5_ioNSDOrNwell = lu4_ioNSD OR lu4_ioNwell
LU5_ioNSDOrNwellSz = SIZE LU5_ioNSDOrNwell BY 50
LU5_ExemptARNonVccNwell_2 = NOT INTERACT LU5_AtRisk_NonVccNwell LU5_ioNSDOrNwellSz
lu4_12_m_AnyPdiff_inAtRisk_NonVccNwell = PSRCDRN AND LU5_AtRisk_NonVccNwell
LU5_ExemptARNonVccNwell_3 = INSIDE CELL nwell "s8bbcnv_psoc5_top_18" "p3ag_p_sio" "s8bbcnv_ov2s_top_27" "s8bbcnv_proc_top_18" "s8bbcnv_m8s8_top_18" "s8bbcnv_m8s8_top_27"
LU5_ExemptARNonVccNwell_4 = INSIDE CELL nwell "s8p3iomacro_gpio_macro" "s8p3iomacro_gpio_macro_ao" "s8p3iomacro_sio_macro" "s8tnvpuv_top" "s8ctbm_top"
LU5_AtRiskNonVccNwellNonExempt = LU5_AtRisk_NonVccNwell NOT (LU5_ExemptARNonVccNwell_1 OR
(LU5_ExemptARNonVccNwell_2 OR
(LU5_ExemptARNonVccNwell_3 OR LU5_ExemptARNonVccNwell_4)))
"k_25_LU5_pDiffVccOrIo_conn_nwellNonVcc" {
@ keep: LU5_pDiffVccOrIo_conn_nwellNonVcc - LU5_pDiffVccOrIo_conn_nwellNonVcc
@ LU5_pDiffVccOrIo_conn_nwellNonVcc
COPY LU5_pDiffVccOrIo_conn_nwellNonVcc
}
"k_26_LU5_nonExemptPdiff" {
@ keep: LU5_nonExemptPdiff - LU5_nonExemptPdiff
@ LU5_nonExemptPdiff
COPY LU5_nonExemptPdiff
}
"k_27_LU5_nonExemptARNonVccNwell" {
@ keep: LU5_nonExemptARNonVccNwell - LU5_nonExemptARNonVccNwell
@ LU5_nonExemptARNonVccNwell
COPY LU5_nonExemptARNonVccNwell
}
"k_28_LU5_ExemptARNonVccNwell_1" {
@ keep: LU5_ExemptARNonVccNwell_1 - LU5_ExemptARNonVccNwell_1
@ LU5_ExemptARNonVccNwell_1
COPY LU5_ExemptARNonVccNwell_1
}
"k_29_LU5_ioNSDOrNwellSz" {
@ keep: LU5_ioNSDOrNwellSz - LU5_ioNSDOrNwellSz
@ LU5_ioNSDOrNwellSz
COPY LU5_ioNSDOrNwellSz
}
"k_30_LU5_ExemptARNonVccNwell_3" {
@ keep: LU5_ExemptARNonVccNwell_3 - LU5_ExemptARNonVccNwell_3
@ LU5_ExemptARNonVccNwell_3
COPY LU5_ExemptARNonVccNwell_3
}
"k_31_LU5_ExemptARNonVccNwell_4" {
@ keep: LU5_ExemptARNonVccNwell_4 - LU5_ExemptARNonVccNwell_4
@ LU5_ExemptARNonVccNwell_2
COPY LU5_ExemptARNonVccNwell_4
}
"k_32_LU5_ExemptARNonVccNwell_2" {
@ keep: LU5_ExemptARNonVccNwell_2 - LU5_ExemptARNonVccNwell_2
@ LU5_ExemptARNonVccNwell_4
COPY LU5_ExemptARNonVccNwell_2
}
"k_33_LU5_AtRiskNonVccNwellNonExempt" {
@ keep: LU5_AtRiskNonVccNwellNonExempt - LU5_AtRiskNonVccNwellNonExempt
@ LU5_AtRiskNonVccNwellNonExempt
COPY LU5_AtRiskNonVccNwellNonExempt
}
pdiffCon3p3or5v = COPY 4022
LU5_AtRiskNonVccNwellNonExempt_3p3V = INTERACT LU5_AtRiskNonVccNwellNonExempt pdiffCon3p3or5v
LU5_AtRiskNonVccNwellNonExempt_Norm = LU5_AtRiskNonVccNwellNonExempt NOT LU5_AtRiskNonVccNwellNonExempt_3p3V
lu5_1_inner_ptap_lyr = COPY PTAPnotSealDonut
lu5_1_ntapNotNonVcc = NTAPnotSealDonut NOT (NTAP AND LU5_AtRiskNonVccNwellNonExempt)
lu5_1_second_ntap_lyr_nwell = INTERACT nwell lu5_1_ntapNotNonVcc
lu5_1_second_ntap_lyr_nwellRing = DONUT lu5_1_second_ntap_lyr_nwell
lu5_1_second_ntap_lyr_nwellHoles = INTERACT (HOLES lu5_1_second_ntap_lyr_nwellRing) lu5_1_inner_ptap_lyr
lu5_1_second_ntap_lyr = lu5_1_ntapNotNonVcc AND (TOUCH lu5_1_second_ntap_lyr_nwellRing lu5_1_second_ntap_lyr_nwellHoles)
/// CALderiveGuardRings: Deriving guard ring inner:lu5_1_innerRingP second:lu5_1_secondRingN third:nil
/// Inner ring derivation
q0lu5_1_innerRingP = COPY LU5_AtRiskNonVccNwellNonExempt
q0lu5_1_inner_ptap_lyr = DONUT lu5_1_inner_ptap_lyr
q1lu5_1_inner_ptap_lyr = COPY q0lu5_1_inner_ptap_lyr
q3lu5_1_inner_ptap_lyr = (HOLES q1lu5_1_inner_ptap_lyr INNER) ENCLOSE q0lu5_1_innerRingP
q2lu5_1_inner_ptap_lyr = COPY q3lu5_1_inner_ptap_lyr
q5lu5_1_inner_ptap_lyr = TOUCH q1lu5_1_inner_ptap_lyr q2lu5_1_inner_ptap_lyr
/// Second ring derivation
q0lu5_1_second_ntap_lyr = NOT INTERACT lu5_1_second_ntap_lyr q5lu5_1_inner_ptap_lyr
q1lu5_1_second_ntap_lyr = DONUT q0lu5_1_second_ntap_lyr
q5lu5_1_second_ntap_lyr = COPY q1lu5_1_second_ntap_lyr
q4lu5_1_inner_ptap_lyr = q2lu5_1_inner_ptap_lyr NOT ENCLOSE q1lu5_1_second_ntap_lyr
q6lu5_1_inner_ptap_lyr = TOUCH q5lu5_1_inner_ptap_lyr q4lu5_1_inner_ptap_lyr
q3lu5_1_second_ntap_lyr = (HOLES q5lu5_1_second_ntap_lyr) ENCLOSE q6lu5_1_inner_ptap_lyr
q4lu5_1_second_ntap_lyr = ((q3lu5_1_second_ntap_lyr NOT q5lu5_1_second_ntap_lyr) NOT q6lu5_1_inner_ptap_lyr) NOT q4lu5_1_inner_ptap_lyr
q6lu5_1_second_ntap_lyr = TOUCH q4lu5_1_second_ntap_lyr q6lu5_1_inner_ptap_lyr
q14lu5_1_second_ntap_lyr = TOUCH q5lu5_1_second_ntap_lyr q6lu5_1_second_ntap_lyr
q2lu5_1_second_ntap_lyr = HOLES q14lu5_1_second_ntap_lyr INNER
q13lu5_1_second_ntap_lyr = TOUCH q14lu5_1_second_ntap_lyr (q2lu5_1_second_ntap_lyr ENCLOSE q6lu5_1_inner_ptap_lyr < 2)
lu5_1_innerRingP = q6lu5_1_inner_ptap_lyr INSIDE (HOLES q13lu5_1_second_ntap_lyr)
lu5_1_secondRingN = COPY q13lu5_1_second_ntap_lyr
lu5_1_PinnerRegion = TOUCH q4lu5_1_inner_ptap_lyr lu5_1_innerRingP
lu5_1_PinnerToSecReg = TOUCH q6lu5_1_second_ntap_lyr lu5_1_innerRingP
/// CALderiveGuardRings complete
lu5_6_inner_ptap_lyr = COPY PTAPnotSealDonut
lu5_6_ntapNotNonVcc = NTAPnotSealDonut NOT (NTAP AND LU5_AtRiskNonVccNwellNonExempt)
lu5_6_second_ntap_lyr_nwell = INTERACT nwell lu5_6_ntapNotNonVcc
lu5_6_second_ntap_lyr_nwellRing = DONUT lu5_6_second_ntap_lyr_nwell
lu5_6_second_ntap_lyr_nwellHoles = INTERACT (HOLES lu5_6_second_ntap_lyr_nwellRing INNER) lu5_6_inner_ptap_lyr
lu5_6_second_ntap_lyr = lu5_6_ntapNotNonVcc AND (TOUCH lu5_6_second_ntap_lyr_nwellRing lu5_6_second_ntap_lyr_nwellHoles)
/// CALderiveGuardRings: Deriving guard ring inner:lu5_6_innerRingP second:lu5_6_secondRingN third:nil
/// Inner ring derivation
q0lu5_6_innerRingP = COPY LU5_AtRiskNonVccNwellNonExempt_3p3V
q0lu5_6_inner_ptap_lyr = DONUT lu5_6_inner_ptap_lyr
q1lu5_6_inner_ptap_lyr = COPY q0lu5_6_inner_ptap_lyr
q3lu5_6_inner_ptap_lyr = (HOLES q1lu5_6_inner_ptap_lyr INNER) ENCLOSE q0lu5_6_innerRingP
q2lu5_6_inner_ptap_lyr = COPY q3lu5_6_inner_ptap_lyr
q5lu5_6_inner_ptap_lyr = TOUCH q1lu5_6_inner_ptap_lyr q2lu5_6_inner_ptap_lyr
/// Second ring derivation
q0lu5_6_second_ntap_lyr = NOT INTERACT lu5_6_second_ntap_lyr q5lu5_6_inner_ptap_lyr
q1lu5_6_second_ntap_lyr = DONUT q0lu5_6_second_ntap_lyr
q5lu5_6_second_ntap_lyr = COPY q1lu5_6_second_ntap_lyr
q4lu5_6_inner_ptap_lyr = q2lu5_6_inner_ptap_lyr NOT ENCLOSE q1lu5_6_second_ntap_lyr
q6lu5_6_inner_ptap_lyr = TOUCH q5lu5_6_inner_ptap_lyr q4lu5_6_inner_ptap_lyr
q3lu5_6_second_ntap_lyr = (HOLES q5lu5_6_second_ntap_lyr) ENCLOSE q6lu5_6_inner_ptap_lyr
q4lu5_6_second_ntap_lyr = ((q3lu5_6_second_ntap_lyr NOT q5lu5_6_second_ntap_lyr) NOT q6lu5_6_inner_ptap_lyr) NOT q4lu5_6_inner_ptap_lyr
q6lu5_6_second_ntap_lyr = TOUCH q4lu5_6_second_ntap_lyr q6lu5_6_inner_ptap_lyr
q14lu5_6_second_ntap_lyr = TOUCH q5lu5_6_second_ntap_lyr q6lu5_6_second_ntap_lyr
q2lu5_6_second_ntap_lyr = HOLES q14lu5_6_second_ntap_lyr INNER
q13lu5_6_second_ntap_lyr = TOUCH q14lu5_6_second_ntap_lyr (q2lu5_6_second_ntap_lyr ENCLOSE q6lu5_6_inner_ptap_lyr < 2)
lu5_6_innerRingP = q6lu5_6_inner_ptap_lyr INSIDE (HOLES q13lu5_6_second_ntap_lyr)
lu5_6_secondRingN = COPY q13lu5_6_second_ntap_lyr
lu5_6_PinnerRegion = TOUCH q4lu5_6_inner_ptap_lyr lu5_6_innerRingP
lu5_6_PinnerToSecReg = TOUCH q6lu5_6_second_ntap_lyr lu5_6_innerRingP
/// CALderiveGuardRings complete
bad_pDiffVcc_and_nWellNonVcc_Norm = LU5_AtRiskNonVccNwellNonExempt_Norm NOT lu5_1_PinnerRegion
bad_pDiffVcc_and_nWellNonVcc_3p3V = LU5_AtRiskNonVccNwellNonExempt_3p3V NOT lu5_6_PinnerRegion
"k_34_bad_pDiffVcc_and_nWellNonVcc_Norm" {
@ keep: bad_pDiffVcc_and_nWellNonVcc_Norm - bad_pDiffVcc_and_nWellNonVcc_Norm
COPY bad_pDiffVcc_and_nWellNonVcc_Norm
}
"k_35_bad_pDiffVcc_and_nWellNonVcc_3p3V" {
@ keep: bad_pDiffVcc_and_nWellNonVcc_3p3V - bad_pDiffVcc_and_nWellNonVcc_3p3V
COPY bad_pDiffVcc_and_nWellNonVcc_3p3V
}
"r_114_lu.5.1a/b" {
@ lu.5.1a/b: p+ diff metallically connected to Vcc,switched_power or io Net in an At-Risk Non-Vcc nwell must have a p+ tap inner guard ring and n+ tap outer guard ring
COPY bad_pDiffVcc_and_nWellNonVcc_Norm
}
"r_115_lu.5.6" {
@ lu.5.6: p+ diff metallically connected to 3.3V in an At-Risk Non-Vcc nwell must have a p+ tap inner guard ring and n+ tap outer guard ring
COPY bad_pDiffVcc_and_nWellNonVcc_3p3V
}
/// CALconnectZone started - zoneName was "zone_13"
CONNECT NSRCDRN ndiff_esdRes
CONNECT PSRCDRN pdiff_esdRes
CONNECT NSRCDRN ndiff_res
CONNECT PSRCDRN pdiff_res
CONNECT PolyNoRes poly_esdRes
CONNECT PolyNoRes poly_res
CONNECT Met1 Met1EsdResnoVD
CONNECT Met2 Met2EsdResnoVD
CONNECT Met3 Met3EsdResnoVD
CONNECT isolatedSubNoPWR pwell_res
CONNECT Met4 Met4EsdResnoVD
CONNECT Met5 Met5EsdResnoVD
CONNECT lu5_1_secondRingN NTAP
CONNECT lu5_1_innerRingP PTAP
CONNECT Li1 lu5_1_innerRingP BY Licon1Pfom
CONNECT Li1 lu5_1_secondRingN BY Licon1Nfom
CONNECT lu5_6_secondRingN NTAP
CONNECT lu5_6_innerRingP PTAP
CONNECT Li1 lu5_6_innerRingP BY Licon1Pfom
CONNECT Li1 lu5_6_secondRingN BY Licon1Nfom
/// CALconnectZone done. zoneName is now zone_14
lu5_1_secondRingN_sPwrConn = NET AREA RATIO lu5_1_secondRingN switched_intPower_met1 > 0
lu5_1_secondRingN_Chk = lu5_1_secondRingN NOT lu5_1_secondRingN_sPwrConn
lu5_1_innerPLicon1 = licon1 AND lu5_1_inner_ptap_lyr
lu5_1_innerPLi1 = (INTERACT Li1 lu5_1_innerPLicon1) AND lu5_1_inner_ptap_lyr
lu5_1_innerPMcon = mcon AND lu5_1_innerPLi1
lu5_1_innerPMet1 = (INTERACT metal1 lu5_1_innerPMcon) AND lu5_1_inner_ptap_lyr
q2lu5_1_innerRingP = lu5_1_innerRingP OUTSIDE lu5_1_innerPLi1
q3lu5_1_innerRingP = NOT DONUT (lu5_1_innerRingP AND lu5_1_innerPLi1)
q1lu5_1_innerRingP = q2lu5_1_innerRingP OR q3lu5_1_innerRingP
"r_116_lu.5.1a/b" {
@ lu.5.1a/b: inner p tap guard ring around at-risk non-vcc nwell requires a continuous Li1 strapping ring
q4lu5_1_innerRingP = COPY q1lu5_1_innerRingP
COPY q4lu5_1_innerRingP
}
q1lu5_1_innerPLicon1 = lu5_1_innerPLicon1 AND lu5_1_innerRingP
q0lu5_1_innerPLicon1 = SIZE q1lu5_1_innerPLicon1 BY 1 INSIDE OF lu5_1_innerRingP STEP 0.19
"k_36_q0lu5_1_innerPLicon1" {
@ keep: q0lu5_1_innerPLicon1 - q0lu5_1_innerPLicon1
@ Guard ring checked for lu.5.1a/b (must be a continuous DONUT)
COPY q0lu5_1_innerPLicon1
}
q6lu5_1_innerRingP = NOT DONUT q0lu5_1_innerPLicon1
"r_117_lu.5.1a/b" {
@ lu.5.1a/b: Guard ring inner p tap guard ring around at-risk non-vcc nwell must be fully contacted with 2.0 max contact space
@ See the keep layer database for the full guard ring being checked
q7lu5_1_innerRingP = COPY q6lu5_1_innerRingP
COPY q7lu5_1_innerRingP
}
lu5_1_secondNLicon1 = licon1 AND lu5_1_second_ntap_lyr
lu5_1_secondNLi1 = (INTERACT Li1 lu5_1_secondNLicon1) AND lu5_1_second_ntap_lyr
lu5_1_secondNMcon = mcon AND lu5_1_secondNLi1
lu5_1_secondNMet1 = (INTERACT metal1 lu5_1_secondNMcon) AND lu5_1_second_ntap_lyr
q1lu5_1_secondRingN = lu5_1_secondRingN OUTSIDE lu5_1_secondNLi1
q2lu5_1_secondRingN = NOT DONUT (lu5_1_secondRingN AND lu5_1_secondNLi1)
q0lu5_1_secondRingN = q1lu5_1_secondRingN OR q2lu5_1_secondRingN
"r_118_lu.5.1a/b" {
@ lu.5.1a/b: outer n tap guard ring around at-risk non-vcc nwell requires a continuous Li1 strapping ring
q3lu5_1_secondRingN = COPY q0lu5_1_secondRingN
COPY q3lu5_1_secondRingN
}
q1lu5_1_secondNLicon1 = lu5_1_secondNLicon1 AND lu5_1_secondRingN
q0lu5_1_secondNLicon1 = SIZE q1lu5_1_secondNLicon1 BY 1 INSIDE OF lu5_1_secondRingN STEP 0.19
"k_37_q0lu5_1_secondNLicon1" {
@ keep: q0lu5_1_secondNLicon1 - q0lu5_1_secondNLicon1
@ Guard ring checked for lu.5.1a/b (must be a continuous DONUT)
COPY q0lu5_1_secondNLicon1
}
q5lu5_1_secondRingN = NOT DONUT q0lu5_1_secondNLicon1
"r_119_lu.5.1a/b" {
@ lu.5.1a/b: Guard ring outer n tap guard ring around at-risk non-vcc nwell must be fully contacted with 2.0 max contact space
@ See the keep layer database for the full guard ring being checked
q6lu5_1_secondRingN = COPY q5lu5_1_secondRingN
COPY q6lu5_1_secondRingN
}
"r_120_lu.5.1a" {
@ lu.5.1a: inner p tap guard ring around at-risk non-vcc nwell must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET lu5_1_innerRingP "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
"r_121_lu.5.1b" {
@ lu.5.1b: ntap outer ring around at-risk non-vcc nwell must connect to externally connected non-regulated vccNets
NOT NET lu5_1_secondRingN_Chk "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
}
"r_122_lu.5.6" {
@ lu.5.6: inner p tap guard ring around at-risk non-vcc nwell must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET lu5_6_innerRingP "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
"r_123_lu.5.6" {
@ lu.5.6: outer n tap guard ring around at-risk non-vcc nwell must connect to vccNets or switched_power nets
NOT NET lu5_6_secondRingN "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
}
lu5_6_pdiff = INTERACT lu5_6_PinnerRegion nwell > 1
lu5_6_ndiff = INTERACT NDIFF lu5_6_PinnerRegion
"r_124_lu.5.6" {
@ lu.5.6: At Risk Non Vcc Nwell connected to 3.3V or higher requires own guardRing, no other nwell allowed
COPY lu5_6_pdiff
}
"r_125_lu.5.6" {
@ lu.5.6: At Risk Non Vcc Nwell connected to 3.3V or higher should not have n+diff between itself and guardRing
COPY lu5_6_ndiff
}
/// CALderiveGuardRings: Deriving guard ring inner:lu5_2_innerRingP second:lu5_2_secondRingN third:nil
/// Inner ring derivation
q0lu5_2_innerRingP = COPY pnp
q0nonPnpPTap = DONUT nonPnpPTap < 2
q1nonPnpPTap = COPY q0nonPnpPTap
q3nonPnpPTap = (HOLES q1nonPnpPTap INNER) ENCLOSE q0lu5_2_innerRingP
q2nonPnpPTap = COPY q3nonPnpPTap
q5nonPnpPTap = TOUCH q1nonPnpPTap q2nonPnpPTap
/// Second ring derivation
q0nonPnpNTap = NOT INTERACT nonPnpNTap q5nonPnpPTap
q1nonPnpNTap = DONUT q0nonPnpNTap < 2
q5nonPnpNTap = COPY q1nonPnpNTap
q4nonPnpPTap = q2nonPnpPTap NOT ENCLOSE q1nonPnpNTap
q6nonPnpPTap = TOUCH q5nonPnpPTap q4nonPnpPTap
q3nonPnpNTap = (HOLES q5nonPnpNTap) ENCLOSE q6nonPnpPTap
q4nonPnpNTap = ((q3nonPnpNTap NOT q5nonPnpNTap) NOT q6nonPnpPTap) NOT q4nonPnpPTap
q6nonPnpNTap = TOUCH q4nonPnpNTap q6nonPnpPTap
q14nonPnpNTap = TOUCH q5nonPnpNTap q6nonPnpNTap
q2nonPnpNTap = HOLES q14nonPnpNTap INNER
q13nonPnpNTap = TOUCH q14nonPnpNTap (q2nonPnpNTap ENCLOSE q6nonPnpPTap < 2)
lu5_2_innerRingP = q6nonPnpPTap INSIDE (HOLES q13nonPnpNTap)
lu5_2_secondRingN = COPY q13nonPnpNTap
lu5_2_PinnerRegion = TOUCH q4nonPnpPTap lu5_2_innerRingP
lu5_2_PinnerToSecReg = TOUCH q6nonPnpNTap lu5_2_innerRingP
/// CALderiveGuardRings complete
bad_pnpDevice = pnp NOT lu5_2_PinnerRegion
"r_126_lu.5.2" {
@ lu.5.2: Double guard rings are required around a PNP device
COPY bad_pnpDevice
}
/// CALconnectZone started - zoneName was "zone_14"
CONNECT lu5_2_secondRingN NTAP
CONNECT lu5_2_innerRingP PTAP
CONNECT Li1 lu5_2_innerRingP BY Licon1Pfom
CONNECT Li1 lu5_2_secondRingN BY Licon1Nfom
/// CALconnectZone done. zoneName is now zone_15
lu5_2_nonPnpPTapLicon1 = licon1 AND nonPnpPTap
lu5_2_nonPnpPTapLi1 = (INTERACT Li1 lu5_2_nonPnpPTapLicon1) AND nonPnpPTap
lu5_2_nonPnpPTapMcon = mcon AND lu5_2_nonPnpPTapLi1
lu5_2_nonPnpPTapMet1 = (INTERACT metal1 lu5_2_nonPnpPTapMcon) AND nonPnpPTap
q2lu5_2_innerRingP = lu5_2_innerRingP OUTSIDE lu5_2_nonPnpPTapLi1
q3lu5_2_innerRingP = NOT DONUT (lu5_2_innerRingP AND lu5_2_nonPnpPTapLi1)
q1lu5_2_innerRingP = q2lu5_2_innerRingP OR q3lu5_2_innerRingP
"r_127_lu.5.2" {
@ lu.5.2: inner p tap guard ring requires a continuous Li1 strapping ring
q4lu5_2_innerRingP = COPY q1lu5_2_innerRingP
COPY q4lu5_2_innerRingP
}
q1lu5_2_nonPnpPTapLicon1 = lu5_2_nonPnpPTapLicon1 AND lu5_2_innerRingP
q0lu5_2_nonPnpPTapLicon1 = SIZE q1lu5_2_nonPnpPTapLicon1 BY 1 INSIDE OF lu5_2_innerRingP STEP 0.19
"k_38_q0lu5_2_nonPnpPTapLicon1" {
@ keep: q0lu5_2_nonPnpPTapLicon1 - q0lu5_2_nonPnpPTapLicon1
@ Guard ring checked for lu.5.2 (must be a continuous DONUT)
COPY q0lu5_2_nonPnpPTapLicon1
}
q6lu5_2_innerRingP = NOT DONUT q0lu5_2_nonPnpPTapLicon1
"r_128_lu.5.2" {
@ lu.5.2: Guard ring inner p tap guard ring must be fully contacted with 2.0 max contact space
@ See the keep layer database for the full guard ring being checked
q7lu5_2_innerRingP = COPY q6lu5_2_innerRingP
COPY q7lu5_2_innerRingP
}
lu5_2_nonPnpNTapLicon1 = licon1 AND nonPnpNTap
lu5_2_nonPnpNTapLi1 = (INTERACT Li1 lu5_2_nonPnpNTapLicon1) AND nonPnpNTap
lu5_2_nonPnpNTapMcon = mcon AND lu5_2_nonPnpNTapLi1
lu5_2_nonPnpNTapMet1 = (INTERACT metal1 lu5_2_nonPnpNTapMcon) AND nonPnpNTap
q1lu5_2_secondRingN = lu5_2_secondRingN OUTSIDE lu5_2_nonPnpNTapLi1
q2lu5_2_secondRingN = NOT DONUT (lu5_2_secondRingN AND lu5_2_nonPnpNTapLi1)
q0lu5_2_secondRingN = q1lu5_2_secondRingN OR q2lu5_2_secondRingN
"r_129_lu.5.2" {
@ lu.5.2: outer n tap guard ring requires a continuous Li1 strapping ring
q3lu5_2_secondRingN = COPY q0lu5_2_secondRingN
COPY q3lu5_2_secondRingN
}
q1lu5_2_nonPnpNTapLicon1 = lu5_2_nonPnpNTapLicon1 AND lu5_2_secondRingN
q0lu5_2_nonPnpNTapLicon1 = SIZE q1lu5_2_nonPnpNTapLicon1 BY 1 INSIDE OF lu5_2_secondRingN STEP 0.19
"k_39_q0lu5_2_nonPnpNTapLicon1" {
@ keep: q0lu5_2_nonPnpNTapLicon1 - q0lu5_2_nonPnpNTapLicon1
@ Guard ring checked for lu.5.2 (must be a continuous DONUT)
COPY q0lu5_2_nonPnpNTapLicon1
}
q5lu5_2_secondRingN = NOT DONUT q0lu5_2_nonPnpNTapLicon1
"r_130_lu.5.2" {
@ lu.5.2: Guard ring outer n tap guard ring must be fully contacted with 2.0 max contact space
@ See the keep layer database for the full guard ring being checked
q6lu5_2_secondRingN = COPY q5lu5_2_secondRingN
COPY q6lu5_2_secondRingN
}
lu5_2_1stRingP_noXmt = lu5_2_innerRingP NOT (EXTENT CELL "s8p3ana_top")
lu5_2_secondRingN_sPwrConn = NET AREA RATIO lu5_2_secondRingN switched_intPower_met1 > 0
lu5_2_secondRingN_Chk = lu5_2_secondRingN NOT lu5_2_secondRingN_sPwrConn
"r_131_lu.5.2" {
@ lu.5.2: lu5_2_1stRingP_noXmt must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET lu5_2_1stRingP_noXmt "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
"r_132_lu.5.2" {
@ lu.5.2: lu5_2_secondRingN_Chk must connect to vccNets or switched_power nets
NOT NET lu5_2_secondRingN_Chk "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
}
/// CALconnectZone started - zoneName was "zone_15"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT NSRCDRN ndiff_esdRes
CONNECT PSRCDRN pdiff_esdRes
CONNECT NSRCDRN ndiff_res
CONNECT PSRCDRN pdiff_res
CONNECT PolyNoRes poly_esdRes
CONNECT PolyNoRes poly_res
CONNECT Met1 Met1EsdResnoVD
CONNECT Met2 Met2EsdResnoVD
CONNECT Met3 Met3EsdResnoVD
CONNECT isolatedSubNoPWR pwell_res
CONNECT Met4 Met4EsdResnoVD
CONNECT Met5 Met5EsdResnoVD
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_16
/// CALconnectZone started - zoneName was "zone_16"
CONNECT LU5_pDiffExtVcc_inAtRiskNonVccNwell PSRCDRN
CONNECT lu4_12_m_AnyPdiff_inAtRisk_NonVccNwell PSRCDRN
CONNECT lu4_12e_g_m_n_ioNSD NSRCDRN
CONNECT LU5_pDiffExtVcc_inAtRiskNonVccNwell PSRCDRN
CONNECT LU5_AtRisk_NonVccNwell nwell
/// CALconnectZone done. zoneName is now zone_17
lu4_12_m_Pdiff_xmt4 = NET AREA RATIO LU5_pDiffExtVcc_inAtRiskNonVccNwell LU5_AtRisk_NonVccNwell > 0 INSIDE OF LAYER LU5_nWellNonVcc
lu4_12_m_AnyPdiff_xmt4 = NET AREA RATIO lu4_12_m_AnyPdiff_inAtRisk_NonVccNwell LU5_AtRisk_NonVccNwell > 0 INSIDE OF LAYER LU5_nWellNonVcc
lu4_12_m_Pdiff_xmt4All = lu4_12_m_Pdiff_xmt4 OR lu4_12_m_AnyPdiff_xmt4
lu4_12_m_Pdiff_nonXmt4 = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT lu4_12_m_Pdiff_xmt4All
lu4_12_m_Pdiff_xmt4a = PSRCDRN WITH EDGE (lu4_12_m_Pdiff_nonXmt4 COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_Pdiff_xmt4All)))
lu4_12_m_Pdiff_nonXmt4Final = lu4_12_m_Pdiff_nonXmt4 NOT lu4_12_m_Pdiff_xmt4a
lu4_12_m_Ndiff_nonXmt3 = COPY lu4_12e_g_m_n_ioNSD
lu4_12_n_Ndiff_nonXmt3 = COPY lu4_12e_g_m_n_ioNSD
lu4_12_n_Nwell_pdiffTie = INTERACT LU5_AtRisk_NonVccNwell lu4_12_m_Pdiff_xmt4
lu4_12_n_Pdiff_nonXmt = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT lu4_12_m_Pdiff_xmt4
lu4_12_n_Nwell_trulyXmt = lu4_12_n_Nwell_pdiffTie NOT (INTERACT LU5_AtRisk_NonVccNwell lu4_12_n_Pdiff_nonXmt)
lu4_12_n_Nwell_nonXmt4 = LU5_AtRisk_NonVccNwell NOT lu4_12_n_Nwell_trulyXmt
lu4_12_n_Pdiff_nonXmt4 = LU5_pDiffExtVcc_inAtRiskNonVccNwell AND lu4_12_n_Nwell_nonXmt4
/// CALconnectZone started - zoneName was "zone_17"
CONNECT lu4_12_m_Pdiff_nonXmt4Final PSRCDRN
CONNECT PSDsigPadNtr PSRCDRN
CONNECT lu4_12_m_Ndiff_nonXmt3 NSRCDRN
CONNECT NSDsigPadNtr NSRCDRN
CONNECT lu4_12_n_Ndiff_nonXmt3 NSRCDRN
CONNECT lu4_12_n_Nwell_nonXmt4 NTAP
CONNECT lu4_12_n_Pdiff_nonXmt4 PSRCDRN
/// CALconnectZone done. zoneName is now zone_18
lu4_12_m_NdiffIo_on_io = NET lu4_12_m_Ndiff_nonXmt3 "io"
lu4_12_m_NdiffIo_NtrId_on_io = NET NSDsigPadNtr "io"
lu4_12_m_NdiffIo_all_on_io = lu4_12_m_NdiffIo_on_io OR lu4_12_m_NdiffIo_NtrId_on_io
lu4_12_m_NdiffIoSz_on_io = SIZE lu4_12_m_NdiffIo_all_on_io BY 33
lu4_12_m_PdiffIo_on_io = NET lu4_12_m_Pdiff_nonXmt4Final "io"
lu4_12_m_PdiffIo_NtrId_on_io = NET PSDsigPadNtr "io"
lu4_12_m_PdiffIo_all_on_io = lu4_12_m_PdiffIo_on_io OR lu4_12_m_PdiffIo_NtrId_on_io
lu4_12_m_NdiffIo_notOn_io = lu4_12_m_Ndiff_nonXmt3 NOT lu4_12_m_NdiffIo_all_on_io
lu4_12_m_PdiffIo_notOn_io = lu4_12_m_Pdiff_nonXmt4Final NOT lu4_12_m_PdiffIo_all_on_io
lu4_12_m_xmtPdiffIo_notOn_io = lu4_12_m_PdiffIo_notOn_io COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_PdiffIo_all_on_io))
lu4_12_m_finalPdiffIo_notOn_io = INTERACT (lu4_12_m_PdiffIo_notOn_io NOT (lu4_12_m_PdiffIo_notOn_io WITH EDGE lu4_12_m_xmtPdiffIo_notOn_io)) lu4_12_m_NdiffIoSz_on_io
"r_133_lu.4.12m" {
@ lu.4.12m: 33 min. spacing of Ndiff on net "io" & Pdiff not on net "io" in an At-Risk Nwell
EXTERNAL lu4_12_m_NdiffIo_all_on_io lu4_12_m_finalPdiffIo_notOn_io < 33.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_n_NdiffIo_on_io = NET lu4_12_n_Ndiff_nonXmt3 "io"
lu4_12_n_NdiffIo_NtrId_on_io = NET NSDsigPadNtr "io"
lu4_12_n_NdiffIo_all_on_io = lu4_12_n_NdiffIo_on_io OR lu4_12_n_NdiffIo_NtrId_on_io
lu4_12_n_NdiffIoSz_on_io = SIZE lu4_12_n_NdiffIo_all_on_io BY 16.75
lu4_12_n_PdiffIo_on_io = NET lu4_12_n_Pdiff_nonXmt4 "io"
lu4_12_n_PdiffIo_NtrId_on_io = NET PSDsigPadNtr "io"
lu4_12_n_PdiffIo_all_on_io = lu4_12_n_PdiffIo_on_io OR lu4_12_n_PdiffIo_NtrId_on_io
lu4_12_n_NdiffIo_notOn_io = lu4_12_n_Ndiff_nonXmt3 NOT lu4_12_n_NdiffIo_all_on_io
lu4_12_n_PdiffIo_notOn_io = lu4_12_n_Pdiff_nonXmt4 NOT lu4_12_n_PdiffIo_all_on_io
lu4_12_n_PdiffNonXmt_io = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT (lu4_12_m_Pdiff_xmt4 OR lu4_12_n_PdiffIo_all_on_io)
lu4_12_n_Nwell_io = INTERACT (INTERACT lu4_12_n_Nwell_nonXmt4 lu4_12_n_PdiffNonXmt_io) lu4_12_n_NdiffIoSz_on_io
"r_134_lu.4.12n" {
@ lu.4.12n: 16.75 min. spacing of Ndiff on net "io" & Nwell with Pdiff not on net "io" in an At-Risk Nwell
EXTERNAL lu4_12_n_NdiffIo_all_on_io lu4_12_n_Nwell_io < 16.75 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_m_NdiffIo_on_io1 = NET lu4_12_m_Ndiff_nonXmt3 "io1"
lu4_12_m_NdiffIo_NtrId_on_io1 = NET NSDsigPadNtr "io1"
lu4_12_m_NdiffIo_all_on_io1 = lu4_12_m_NdiffIo_on_io1 OR lu4_12_m_NdiffIo_NtrId_on_io1
lu4_12_m_NdiffIoSz_on_io1 = SIZE lu4_12_m_NdiffIo_all_on_io1 BY 33
lu4_12_m_PdiffIo_on_io1 = NET lu4_12_m_Pdiff_nonXmt4Final "io1"
lu4_12_m_PdiffIo_NtrId_on_io1 = NET PSDsigPadNtr "io1"
lu4_12_m_PdiffIo_all_on_io1 = lu4_12_m_PdiffIo_on_io1 OR lu4_12_m_PdiffIo_NtrId_on_io1
lu4_12_m_NdiffIo_notOn_io1 = lu4_12_m_Ndiff_nonXmt3 NOT lu4_12_m_NdiffIo_all_on_io1
lu4_12_m_PdiffIo_notOn_io1 = lu4_12_m_Pdiff_nonXmt4Final NOT lu4_12_m_PdiffIo_all_on_io1
lu4_12_m_xmtPdiffIo_notOn_io1 = lu4_12_m_PdiffIo_notOn_io1 COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_PdiffIo_all_on_io1))
lu4_12_m_finalPdiffIo_notOn_io1 = INTERACT (lu4_12_m_PdiffIo_notOn_io1 NOT (lu4_12_m_PdiffIo_notOn_io1 WITH EDGE lu4_12_m_xmtPdiffIo_notOn_io1)) lu4_12_m_NdiffIoSz_on_io1
"r_135_lu.4.12m" {
@ lu.4.12m: 33 min. spacing of Ndiff on net "io1" & Pdiff not on net "io1" in an At-Risk Nwell
EXTERNAL lu4_12_m_NdiffIo_all_on_io1 lu4_12_m_finalPdiffIo_notOn_io1 < 33.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_n_NdiffIo_on_io1 = NET lu4_12_n_Ndiff_nonXmt3 "io1"
lu4_12_n_NdiffIo_NtrId_on_io1 = NET NSDsigPadNtr "io1"
lu4_12_n_NdiffIo_all_on_io1 = lu4_12_n_NdiffIo_on_io1 OR lu4_12_n_NdiffIo_NtrId_on_io1
lu4_12_n_NdiffIoSz_on_io1 = SIZE lu4_12_n_NdiffIo_all_on_io1 BY 16.75
lu4_12_n_PdiffIo_on_io1 = NET lu4_12_n_Pdiff_nonXmt4 "io1"
lu4_12_n_PdiffIo_NtrId_on_io1 = NET PSDsigPadNtr "io1"
lu4_12_n_PdiffIo_all_on_io1 = lu4_12_n_PdiffIo_on_io1 OR lu4_12_n_PdiffIo_NtrId_on_io1
lu4_12_n_NdiffIo_notOn_io1 = lu4_12_n_Ndiff_nonXmt3 NOT lu4_12_n_NdiffIo_all_on_io1
lu4_12_n_PdiffIo_notOn_io1 = lu4_12_n_Pdiff_nonXmt4 NOT lu4_12_n_PdiffIo_all_on_io1
lu4_12_n_PdiffNonXmt_io1 = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT (lu4_12_m_Pdiff_xmt4 OR lu4_12_n_PdiffIo_all_on_io1)
lu4_12_n_Nwell_io1 = INTERACT (INTERACT lu4_12_n_Nwell_nonXmt4 lu4_12_n_PdiffNonXmt_io1) lu4_12_n_NdiffIoSz_on_io1
"r_136_lu.4.12n" {
@ lu.4.12n: 16.75 min. spacing of Ndiff on net "io1" & Nwell with Pdiff not on net "io1" in an At-Risk Nwell
EXTERNAL lu4_12_n_NdiffIo_all_on_io1 lu4_12_n_Nwell_io1 < 16.75 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_m_NdiffIo_on_io2 = NET lu4_12_m_Ndiff_nonXmt3 "io2"
lu4_12_m_NdiffIo_NtrId_on_io2 = NET NSDsigPadNtr "io2"
lu4_12_m_NdiffIo_all_on_io2 = lu4_12_m_NdiffIo_on_io2 OR lu4_12_m_NdiffIo_NtrId_on_io2
lu4_12_m_NdiffIoSz_on_io2 = SIZE lu4_12_m_NdiffIo_all_on_io2 BY 33
lu4_12_m_PdiffIo_on_io2 = NET lu4_12_m_Pdiff_nonXmt4Final "io2"
lu4_12_m_PdiffIo_NtrId_on_io2 = NET PSDsigPadNtr "io2"
lu4_12_m_PdiffIo_all_on_io2 = lu4_12_m_PdiffIo_on_io2 OR lu4_12_m_PdiffIo_NtrId_on_io2
lu4_12_m_NdiffIo_notOn_io2 = lu4_12_m_Ndiff_nonXmt3 NOT lu4_12_m_NdiffIo_all_on_io2
lu4_12_m_PdiffIo_notOn_io2 = lu4_12_m_Pdiff_nonXmt4Final NOT lu4_12_m_PdiffIo_all_on_io2
lu4_12_m_xmtPdiffIo_notOn_io2 = lu4_12_m_PdiffIo_notOn_io2 COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_PdiffIo_all_on_io2))
lu4_12_m_finalPdiffIo_notOn_io2 = INTERACT (lu4_12_m_PdiffIo_notOn_io2 NOT (lu4_12_m_PdiffIo_notOn_io2 WITH EDGE lu4_12_m_xmtPdiffIo_notOn_io2)) lu4_12_m_NdiffIoSz_on_io2
"r_137_lu.4.12m" {
@ lu.4.12m: 33 min. spacing of Ndiff on net "io2" & Pdiff not on net "io2" in an At-Risk Nwell
EXTERNAL lu4_12_m_NdiffIo_all_on_io2 lu4_12_m_finalPdiffIo_notOn_io2 < 33.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_n_NdiffIo_on_io2 = NET lu4_12_n_Ndiff_nonXmt3 "io2"
lu4_12_n_NdiffIo_NtrId_on_io2 = NET NSDsigPadNtr "io2"
lu4_12_n_NdiffIo_all_on_io2 = lu4_12_n_NdiffIo_on_io2 OR lu4_12_n_NdiffIo_NtrId_on_io2
lu4_12_n_NdiffIoSz_on_io2 = SIZE lu4_12_n_NdiffIo_all_on_io2 BY 16.75
lu4_12_n_PdiffIo_on_io2 = NET lu4_12_n_Pdiff_nonXmt4 "io2"
lu4_12_n_PdiffIo_NtrId_on_io2 = NET PSDsigPadNtr "io2"
lu4_12_n_PdiffIo_all_on_io2 = lu4_12_n_PdiffIo_on_io2 OR lu4_12_n_PdiffIo_NtrId_on_io2
lu4_12_n_NdiffIo_notOn_io2 = lu4_12_n_Ndiff_nonXmt3 NOT lu4_12_n_NdiffIo_all_on_io2
lu4_12_n_PdiffIo_notOn_io2 = lu4_12_n_Pdiff_nonXmt4 NOT lu4_12_n_PdiffIo_all_on_io2
lu4_12_n_PdiffNonXmt_io2 = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT (lu4_12_m_Pdiff_xmt4 OR lu4_12_n_PdiffIo_all_on_io2)
lu4_12_n_Nwell_io2 = INTERACT (INTERACT lu4_12_n_Nwell_nonXmt4 lu4_12_n_PdiffNonXmt_io2) lu4_12_n_NdiffIoSz_on_io2
"r_138_lu.4.12n" {
@ lu.4.12n: 16.75 min. spacing of Ndiff on net "io2" & Nwell with Pdiff not on net "io2" in an At-Risk Nwell
EXTERNAL lu4_12_n_NdiffIo_all_on_io2 lu4_12_n_Nwell_io2 < 16.75 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_m_NdiffIo_on_io4 = NET lu4_12_m_Ndiff_nonXmt3 "io4"
lu4_12_m_NdiffIo_NtrId_on_io4 = NET NSDsigPadNtr "io4"
lu4_12_m_NdiffIo_all_on_io4 = lu4_12_m_NdiffIo_on_io4 OR lu4_12_m_NdiffIo_NtrId_on_io4
lu4_12_m_NdiffIoSz_on_io4 = SIZE lu4_12_m_NdiffIo_all_on_io4 BY 33
lu4_12_m_PdiffIo_on_io4 = NET lu4_12_m_Pdiff_nonXmt4Final "io4"
lu4_12_m_PdiffIo_NtrId_on_io4 = NET PSDsigPadNtr "io4"
lu4_12_m_PdiffIo_all_on_io4 = lu4_12_m_PdiffIo_on_io4 OR lu4_12_m_PdiffIo_NtrId_on_io4
lu4_12_m_NdiffIo_notOn_io4 = lu4_12_m_Ndiff_nonXmt3 NOT lu4_12_m_NdiffIo_all_on_io4
lu4_12_m_PdiffIo_notOn_io4 = lu4_12_m_Pdiff_nonXmt4Final NOT lu4_12_m_PdiffIo_all_on_io4
lu4_12_m_xmtPdiffIo_notOn_io4 = lu4_12_m_PdiffIo_notOn_io4 COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_PdiffIo_all_on_io4))
lu4_12_m_finalPdiffIo_notOn_io4 = INTERACT (lu4_12_m_PdiffIo_notOn_io4 NOT (lu4_12_m_PdiffIo_notOn_io4 WITH EDGE lu4_12_m_xmtPdiffIo_notOn_io4)) lu4_12_m_NdiffIoSz_on_io4
"r_139_lu.4.12m" {
@ lu.4.12m: 33 min. spacing of Ndiff on net "io4" & Pdiff not on net "io4" in an At-Risk Nwell
EXTERNAL lu4_12_m_NdiffIo_all_on_io4 lu4_12_m_finalPdiffIo_notOn_io4 < 33.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_n_NdiffIo_on_io4 = NET lu4_12_n_Ndiff_nonXmt3 "io4"
lu4_12_n_NdiffIo_NtrId_on_io4 = NET NSDsigPadNtr "io4"
lu4_12_n_NdiffIo_all_on_io4 = lu4_12_n_NdiffIo_on_io4 OR lu4_12_n_NdiffIo_NtrId_on_io4
lu4_12_n_NdiffIoSz_on_io4 = SIZE lu4_12_n_NdiffIo_all_on_io4 BY 16.75
lu4_12_n_PdiffIo_on_io4 = NET lu4_12_n_Pdiff_nonXmt4 "io4"
lu4_12_n_PdiffIo_NtrId_on_io4 = NET PSDsigPadNtr "io4"
lu4_12_n_PdiffIo_all_on_io4 = lu4_12_n_PdiffIo_on_io4 OR lu4_12_n_PdiffIo_NtrId_on_io4
lu4_12_n_NdiffIo_notOn_io4 = lu4_12_n_Ndiff_nonXmt3 NOT lu4_12_n_NdiffIo_all_on_io4
lu4_12_n_PdiffIo_notOn_io4 = lu4_12_n_Pdiff_nonXmt4 NOT lu4_12_n_PdiffIo_all_on_io4
lu4_12_n_PdiffNonXmt_io4 = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT (lu4_12_m_Pdiff_xmt4 OR lu4_12_n_PdiffIo_all_on_io4)
lu4_12_n_Nwell_io4 = INTERACT (INTERACT lu4_12_n_Nwell_nonXmt4 lu4_12_n_PdiffNonXmt_io4) lu4_12_n_NdiffIoSz_on_io4
"r_140_lu.4.12n" {
@ lu.4.12n: 16.75 min. spacing of Ndiff on net "io4" & Nwell with Pdiff not on net "io4" in an At-Risk Nwell
EXTERNAL lu4_12_n_NdiffIo_all_on_io4 lu4_12_n_Nwell_io4 < 16.75 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_m_NdiffIo_on_io_prb = NET lu4_12_m_Ndiff_nonXmt3 "io_prb"
lu4_12_m_NdiffIo_NtrId_on_io_prb = NET NSDsigPadNtr "io_prb"
lu4_12_m_NdiffIo_all_on_io_prb = lu4_12_m_NdiffIo_on_io_prb OR lu4_12_m_NdiffIo_NtrId_on_io_prb
lu4_12_m_NdiffIoSz_on_io_prb = SIZE lu4_12_m_NdiffIo_all_on_io_prb BY 33
lu4_12_m_PdiffIo_on_io_prb = NET lu4_12_m_Pdiff_nonXmt4Final "io_prb"
lu4_12_m_PdiffIo_NtrId_on_io_prb = NET PSDsigPadNtr "io_prb"
lu4_12_m_PdiffIo_all_on_io_prb = lu4_12_m_PdiffIo_on_io_prb OR lu4_12_m_PdiffIo_NtrId_on_io_prb
lu4_12_m_NdiffIo_notOn_io_prb = lu4_12_m_Ndiff_nonXmt3 NOT lu4_12_m_NdiffIo_all_on_io_prb
lu4_12_m_PdiffIo_notOn_io_prb = lu4_12_m_Pdiff_nonXmt4Final NOT lu4_12_m_PdiffIo_all_on_io_prb
lu4_12_m_xmtPdiffIo_notOn_io_prb = lu4_12_m_PdiffIo_notOn_io_prb COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_PdiffIo_all_on_io_prb))
lu4_12_m_finalPdiffIo_notOn_io_prb = INTERACT (lu4_12_m_PdiffIo_notOn_io_prb NOT (lu4_12_m_PdiffIo_notOn_io_prb WITH EDGE lu4_12_m_xmtPdiffIo_notOn_io_prb)) lu4_12_m_NdiffIoSz_on_io_prb
"r_141_lu.4.12m" {
@ lu.4.12m: 33 min. spacing of Ndiff on net "io_prb" & Pdiff not on net "io_prb" in an At-Risk Nwell
EXTERNAL lu4_12_m_NdiffIo_all_on_io_prb lu4_12_m_finalPdiffIo_notOn_io_prb < 33.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_n_NdiffIo_on_io_prb = NET lu4_12_n_Ndiff_nonXmt3 "io_prb"
lu4_12_n_NdiffIo_NtrId_on_io_prb = NET NSDsigPadNtr "io_prb"
lu4_12_n_NdiffIo_all_on_io_prb = lu4_12_n_NdiffIo_on_io_prb OR lu4_12_n_NdiffIo_NtrId_on_io_prb
lu4_12_n_NdiffIoSz_on_io_prb = SIZE lu4_12_n_NdiffIo_all_on_io_prb BY 16.75
lu4_12_n_PdiffIo_on_io_prb = NET lu4_12_n_Pdiff_nonXmt4 "io_prb"
lu4_12_n_PdiffIo_NtrId_on_io_prb = NET PSDsigPadNtr "io_prb"
lu4_12_n_PdiffIo_all_on_io_prb = lu4_12_n_PdiffIo_on_io_prb OR lu4_12_n_PdiffIo_NtrId_on_io_prb
lu4_12_n_NdiffIo_notOn_io_prb = lu4_12_n_Ndiff_nonXmt3 NOT lu4_12_n_NdiffIo_all_on_io_prb
lu4_12_n_PdiffIo_notOn_io_prb = lu4_12_n_Pdiff_nonXmt4 NOT lu4_12_n_PdiffIo_all_on_io_prb
lu4_12_n_PdiffNonXmt_io_prb = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT (lu4_12_m_Pdiff_xmt4 OR lu4_12_n_PdiffIo_all_on_io_prb)
lu4_12_n_Nwell_io_prb = INTERACT (INTERACT lu4_12_n_Nwell_nonXmt4 lu4_12_n_PdiffNonXmt_io_prb) lu4_12_n_NdiffIoSz_on_io_prb
"r_142_lu.4.12n" {
@ lu.4.12n: 16.75 min. spacing of Ndiff on net "io_prb" & Nwell with Pdiff not on net "io_prb" in an At-Risk Nwell
EXTERNAL lu4_12_n_NdiffIo_all_on_io_prb lu4_12_n_Nwell_io_prb < 16.75 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_m_NdiffIo_on_pad5v = NET lu4_12_m_Ndiff_nonXmt3 "pad5v"
lu4_12_m_NdiffIo_NtrId_on_pad5v = NET NSDsigPadNtr "pad5v"
lu4_12_m_NdiffIo_all_on_pad5v = lu4_12_m_NdiffIo_on_pad5v OR lu4_12_m_NdiffIo_NtrId_on_pad5v
lu4_12_m_NdiffIoSz_on_pad5v = SIZE lu4_12_m_NdiffIo_all_on_pad5v BY 33
lu4_12_m_PdiffIo_on_pad5v = NET lu4_12_m_Pdiff_nonXmt4Final "pad5v"
lu4_12_m_PdiffIo_NtrId_on_pad5v = NET PSDsigPadNtr "pad5v"
lu4_12_m_PdiffIo_all_on_pad5v = lu4_12_m_PdiffIo_on_pad5v OR lu4_12_m_PdiffIo_NtrId_on_pad5v
lu4_12_m_NdiffIo_notOn_pad5v = lu4_12_m_Ndiff_nonXmt3 NOT lu4_12_m_NdiffIo_all_on_pad5v
lu4_12_m_PdiffIo_notOn_pad5v = lu4_12_m_Pdiff_nonXmt4Final NOT lu4_12_m_PdiffIo_all_on_pad5v
lu4_12_m_xmtPdiffIo_notOn_pad5v = lu4_12_m_PdiffIo_notOn_pad5v COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_PdiffIo_all_on_pad5v))
lu4_12_m_finalPdiffIo_notOn_pad5v = INTERACT (lu4_12_m_PdiffIo_notOn_pad5v NOT (lu4_12_m_PdiffIo_notOn_pad5v WITH EDGE lu4_12_m_xmtPdiffIo_notOn_pad5v)) lu4_12_m_NdiffIoSz_on_pad5v
"r_143_lu.4.12m" {
@ lu.4.12m: 33 min. spacing of Ndiff on net "pad5v" & Pdiff not on net "pad5v" in an At-Risk Nwell
EXTERNAL lu4_12_m_NdiffIo_all_on_pad5v lu4_12_m_finalPdiffIo_notOn_pad5v < 33.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_n_NdiffIo_on_pad5v = NET lu4_12_n_Ndiff_nonXmt3 "pad5v"
lu4_12_n_NdiffIo_NtrId_on_pad5v = NET NSDsigPadNtr "pad5v"
lu4_12_n_NdiffIo_all_on_pad5v = lu4_12_n_NdiffIo_on_pad5v OR lu4_12_n_NdiffIo_NtrId_on_pad5v
lu4_12_n_NdiffIoSz_on_pad5v = SIZE lu4_12_n_NdiffIo_all_on_pad5v BY 16.75
lu4_12_n_PdiffIo_on_pad5v = NET lu4_12_n_Pdiff_nonXmt4 "pad5v"
lu4_12_n_PdiffIo_NtrId_on_pad5v = NET PSDsigPadNtr "pad5v"
lu4_12_n_PdiffIo_all_on_pad5v = lu4_12_n_PdiffIo_on_pad5v OR lu4_12_n_PdiffIo_NtrId_on_pad5v
lu4_12_n_NdiffIo_notOn_pad5v = lu4_12_n_Ndiff_nonXmt3 NOT lu4_12_n_NdiffIo_all_on_pad5v
lu4_12_n_PdiffIo_notOn_pad5v = lu4_12_n_Pdiff_nonXmt4 NOT lu4_12_n_PdiffIo_all_on_pad5v
lu4_12_n_PdiffNonXmt_pad5v = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT (lu4_12_m_Pdiff_xmt4 OR lu4_12_n_PdiffIo_all_on_pad5v)
lu4_12_n_Nwell_pad5v = INTERACT (INTERACT lu4_12_n_Nwell_nonXmt4 lu4_12_n_PdiffNonXmt_pad5v) lu4_12_n_NdiffIoSz_on_pad5v
"r_144_lu.4.12n" {
@ lu.4.12n: 16.75 min. spacing of Ndiff on net "pad5v" & Nwell with Pdiff not on net "pad5v" in an At-Risk Nwell
EXTERNAL lu4_12_n_NdiffIo_all_on_pad5v lu4_12_n_Nwell_pad5v < 16.75 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_m_NdiffIo_on_io_pad = NET lu4_12_m_Ndiff_nonXmt3 "io_pad"
lu4_12_m_NdiffIo_NtrId_on_io_pad = NET NSDsigPadNtr "io_pad"
lu4_12_m_NdiffIo_all_on_io_pad = lu4_12_m_NdiffIo_on_io_pad OR lu4_12_m_NdiffIo_NtrId_on_io_pad
lu4_12_m_NdiffIoSz_on_io_pad = SIZE lu4_12_m_NdiffIo_all_on_io_pad BY 33
lu4_12_m_PdiffIo_on_io_pad = NET lu4_12_m_Pdiff_nonXmt4Final "io_pad"
lu4_12_m_PdiffIo_NtrId_on_io_pad = NET PSDsigPadNtr "io_pad"
lu4_12_m_PdiffIo_all_on_io_pad = lu4_12_m_PdiffIo_on_io_pad OR lu4_12_m_PdiffIo_NtrId_on_io_pad
lu4_12_m_NdiffIo_notOn_io_pad = lu4_12_m_Ndiff_nonXmt3 NOT lu4_12_m_NdiffIo_all_on_io_pad
lu4_12_m_PdiffIo_notOn_io_pad = lu4_12_m_Pdiff_nonXmt4Final NOT lu4_12_m_PdiffIo_all_on_io_pad
lu4_12_m_xmtPdiffIo_notOn_io_pad = lu4_12_m_PdiffIo_notOn_io_pad COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_PdiffIo_all_on_io_pad))
lu4_12_m_finalPdiffIo_notOn_io_pad = INTERACT (lu4_12_m_PdiffIo_notOn_io_pad NOT (lu4_12_m_PdiffIo_notOn_io_pad WITH EDGE lu4_12_m_xmtPdiffIo_notOn_io_pad)) lu4_12_m_NdiffIoSz_on_io_pad
"r_145_lu.4.12m" {
@ lu.4.12m: 33 min. spacing of Ndiff on net "io_pad" & Pdiff not on net "io_pad" in an At-Risk Nwell
EXTERNAL lu4_12_m_NdiffIo_all_on_io_pad lu4_12_m_finalPdiffIo_notOn_io_pad < 33.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_n_NdiffIo_on_io_pad = NET lu4_12_n_Ndiff_nonXmt3 "io_pad"
lu4_12_n_NdiffIo_NtrId_on_io_pad = NET NSDsigPadNtr "io_pad"
lu4_12_n_NdiffIo_all_on_io_pad = lu4_12_n_NdiffIo_on_io_pad OR lu4_12_n_NdiffIo_NtrId_on_io_pad
lu4_12_n_NdiffIoSz_on_io_pad = SIZE lu4_12_n_NdiffIo_all_on_io_pad BY 16.75
lu4_12_n_PdiffIo_on_io_pad = NET lu4_12_n_Pdiff_nonXmt4 "io_pad"
lu4_12_n_PdiffIo_NtrId_on_io_pad = NET PSDsigPadNtr "io_pad"
lu4_12_n_PdiffIo_all_on_io_pad = lu4_12_n_PdiffIo_on_io_pad OR lu4_12_n_PdiffIo_NtrId_on_io_pad
lu4_12_n_NdiffIo_notOn_io_pad = lu4_12_n_Ndiff_nonXmt3 NOT lu4_12_n_NdiffIo_all_on_io_pad
lu4_12_n_PdiffIo_notOn_io_pad = lu4_12_n_Pdiff_nonXmt4 NOT lu4_12_n_PdiffIo_all_on_io_pad
lu4_12_n_PdiffNonXmt_io_pad = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT (lu4_12_m_Pdiff_xmt4 OR lu4_12_n_PdiffIo_all_on_io_pad)
lu4_12_n_Nwell_io_pad = INTERACT (INTERACT lu4_12_n_Nwell_nonXmt4 lu4_12_n_PdiffNonXmt_io_pad) lu4_12_n_NdiffIoSz_on_io_pad
"r_146_lu.4.12n" {
@ lu.4.12n: 16.75 min. spacing of Ndiff on net "io_pad" & Nwell with Pdiff not on net "io_pad" in an At-Risk Nwell
EXTERNAL lu4_12_n_NdiffIo_all_on_io_pad lu4_12_n_Nwell_io_pad < 16.75 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_m_NdiffIo_on_pad = NET lu4_12_m_Ndiff_nonXmt3 "pad"
lu4_12_m_NdiffIo_NtrId_on_pad = NET NSDsigPadNtr "pad"
lu4_12_m_NdiffIo_all_on_pad = lu4_12_m_NdiffIo_on_pad OR lu4_12_m_NdiffIo_NtrId_on_pad
lu4_12_m_NdiffIoSz_on_pad = SIZE lu4_12_m_NdiffIo_all_on_pad BY 33
lu4_12_m_PdiffIo_on_pad = NET lu4_12_m_Pdiff_nonXmt4Final "pad"
lu4_12_m_PdiffIo_NtrId_on_pad = NET PSDsigPadNtr "pad"
lu4_12_m_PdiffIo_all_on_pad = lu4_12_m_PdiffIo_on_pad OR lu4_12_m_PdiffIo_NtrId_on_pad
lu4_12_m_NdiffIo_notOn_pad = lu4_12_m_Ndiff_nonXmt3 NOT lu4_12_m_NdiffIo_all_on_pad
lu4_12_m_PdiffIo_notOn_pad = lu4_12_m_Pdiff_nonXmt4Final NOT lu4_12_m_PdiffIo_all_on_pad
lu4_12_m_xmtPdiffIo_notOn_pad = lu4_12_m_PdiffIo_notOn_pad COINCIDENT OUTSIDE EDGE (gate WITH EDGE (gate COINCIDENT OUTSIDE EDGE lu4_12_m_PdiffIo_all_on_pad))
lu4_12_m_finalPdiffIo_notOn_pad = INTERACT (lu4_12_m_PdiffIo_notOn_pad NOT (lu4_12_m_PdiffIo_notOn_pad WITH EDGE lu4_12_m_xmtPdiffIo_notOn_pad)) lu4_12_m_NdiffIoSz_on_pad
"r_147_lu.4.12m" {
@ lu.4.12m: 33 min. spacing of Ndiff on net "pad" & Pdiff not on net "pad" in an At-Risk Nwell
EXTERNAL lu4_12_m_NdiffIo_all_on_pad lu4_12_m_finalPdiffIo_notOn_pad < 33.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lu4_12_n_NdiffIo_on_pad = NET lu4_12_n_Ndiff_nonXmt3 "pad"
lu4_12_n_NdiffIo_NtrId_on_pad = NET NSDsigPadNtr "pad"
lu4_12_n_NdiffIo_all_on_pad = lu4_12_n_NdiffIo_on_pad OR lu4_12_n_NdiffIo_NtrId_on_pad
lu4_12_n_NdiffIoSz_on_pad = SIZE lu4_12_n_NdiffIo_all_on_pad BY 16.75
lu4_12_n_PdiffIo_on_pad = NET lu4_12_n_Pdiff_nonXmt4 "pad"
lu4_12_n_PdiffIo_NtrId_on_pad = NET PSDsigPadNtr "pad"
lu4_12_n_PdiffIo_all_on_pad = lu4_12_n_PdiffIo_on_pad OR lu4_12_n_PdiffIo_NtrId_on_pad
lu4_12_n_NdiffIo_notOn_pad = lu4_12_n_Ndiff_nonXmt3 NOT lu4_12_n_NdiffIo_all_on_pad
lu4_12_n_PdiffIo_notOn_pad = lu4_12_n_Pdiff_nonXmt4 NOT lu4_12_n_PdiffIo_all_on_pad
lu4_12_n_PdiffNonXmt_pad = LU5_pDiffExtVcc_inAtRiskNonVccNwell NOT (lu4_12_m_Pdiff_xmt4 OR lu4_12_n_PdiffIo_all_on_pad)
lu4_12_n_Nwell_pad = INTERACT (INTERACT lu4_12_n_Nwell_nonXmt4 lu4_12_n_PdiffNonXmt_pad) lu4_12_n_NdiffIoSz_on_pad
"r_148_lu.4.12n" {
@ lu.4.12n: 16.75 min. spacing of Ndiff on net "pad" & Nwell with Pdiff not on net "pad" in an At-Risk Nwell
EXTERNAL lu4_12_n_NdiffIo_all_on_pad lu4_12_n_Nwell_pad < 16.75 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
/// CALderiveCellPinsFromTables: Deriving pin(s) "vpwr_out" from table "Table 3" from cells table(s) nil
/// CALderiveCellPin: "vpwr_out" pin
/// Pins for cell mtdr_io_reg_mockup
q0mtdr_io_reg_mockupArea = EXTENT CELL "mtdr_io_reg_mockup" ORIGINAL
/// Pin layer met2_pin - text (Met2pt Met2tt)
q0Met2pt = EXPAND TEXT "vpwr_out" Met2pt BY 0.001
q0Met2tt = EXPAND TEXT "vpwr_out" Met2tt BY 0.001
q0met2_pin = q0Met2pt OR q0Met2tt
q1met2_pin = INSIDE CELL met2_pin "mtdr_io_reg_mockup" PRIMARY ONLY
q2met2_pin = INTERACT q1met2_pin q0met2_pin
q0mtdr_io_reg_mockup_q0reg_mtdr_io_reg_mockup_met2 = q2met2_pin AND q0mtdr_io_reg_mockupArea
/// Generate output layers
q0reg_mtdr_io_reg_mockup_met2 = COPY q0mtdr_io_reg_mockup_q0reg_mtdr_io_reg_mockup_met2
/// CALderiveCellPin: done with "vpwr_out" pin
q1reg_mtdr_io_reg_mockup_met2 = COPY q0reg_mtdr_io_reg_mockup_met2
reg_mtdr_io_reg_mockup_met2 = Met2 AND q1reg_mtdr_io_reg_mockup_met2
/// CALderiveCellPinsFromTables: Done deriving pin(s) "vpwr_out" from table "Table 3" from cells table(s) nil
/// CALderiveCellPinsFromTables: Deriving pin(s) "vpwr_io" from table "Table 3" from cells table(s) nil
/// CALderiveCellPin: "vpwr_io" pin
/// Pins for cell s8tee_reg_top
q0s8tee_reg_topArea = EXTENT CELL "s8tee_reg_top" ORIGINAL
/// Pin layer met2_pin - text (Met2pt Met2tt)
q1Met2pt = EXPAND TEXT "vpwr_io" Met2pt BY 0.001
q1Met2tt = EXPAND TEXT "vpwr_io" Met2tt BY 0.001
q3met2_pin = q1Met2pt OR q1Met2tt
q4met2_pin = INSIDE CELL met2_pin "s8tee_reg_top" PRIMARY ONLY
q5met2_pin = INTERACT q4met2_pin q3met2_pin
q0s8tee_reg_top_q0reg_s8tee_reg_top_met2 = q5met2_pin AND q0s8tee_reg_topArea
/// Generate output layers
q0reg_s8tee_reg_top_met2 = COPY q0s8tee_reg_top_q0reg_s8tee_reg_top_met2
/// CALderiveCellPin: done with "vpwr_io" pin
q1reg_s8tee_reg_top_met2 = COPY q0reg_s8tee_reg_top_met2
reg_s8tee_reg_top_met2 = Met2 AND q1reg_s8tee_reg_top_met2
/// CALderiveCellPinsFromTables: Done deriving pin(s) "vpwr_io" from table "Table 3" from cells table(s) nil
"k_40_reg_mtdr_io_reg_mockup_met2" {
@ keep: reg_mtdr_io_reg_mockup_met2 - reg_mtdr_io_reg_mockup_met2
COPY reg_mtdr_io_reg_mockup_met2
}
"k_41_reg_s8tee_reg_top_met2" {
@ keep: reg_s8tee_reg_top_met2 - reg_s8tee_reg_top_met2
COPY reg_s8tee_reg_top_met2
}
/// CALconnectZone started - zoneName was "zone_18"
/// CALconnectZone done. zoneName is now zone_19
/// CALconnectZone started - zoneName was "zone_19"
CONNECT Met2 reg_mtdr_io_reg_mockup_met2
CONNECT Met2 reg_s8tee_reg_top_met2
/// CALconnectZone done. zoneName is now zone_20
NTAPnotSealDonutNotLU4_NTAPspRes = NOT INTERACT NTAPnotSealDonut LU4_NTAPspRes
NTAPnotSealDonutNotLU4_NTAPspNtr = NOT INTERACT NTAPnotSealDonut LU4_NTAPspNtr
inner_ptap_DGR_dnwell = inner_ptap_DGR AND dnwell
inner_ptap_DGR_nodnwell = inner_ptap_DGR NOT inner_ptap_DGR_dnwell
second_ntap_DGR_dnwell = second_ntap_DGR AND dnwell
second_ntap_DGR_nodnwell = second_ntap_DGR NOT second_ntap_DGR_dnwell
LU4_PTAPspRes_PW = INTERACT LU4_PTAPspRes dnwell
LU4_PTAPspNtr_PW = INTERACT LU4_PTAPspNtr dnwell
PWPTAPnotSealDonutNotLU4_PWPTAPspRes = NOT INTERACT PTAPnotSealDonut LU4_PTAPspRes_PW
PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = NOT INTERACT PTAPnotSealDonut LU4_PTAPspNtr_PW
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_forNTAP second:lu4_secondRingN_forNTAP third:nil
/// Inner ring derivation
q0lu4_innerRingP_forNTAP = COPY LU4_NTAPspRes
q124PTAPnotSealDonut = DONUT PTAPnotSealDonut < 2
q125PTAPnotSealDonut = COPY q124PTAPnotSealDonut
q127PTAPnotSealDonut = (HOLES q125PTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingP_forNTAP
q126PTAPnotSealDonut = COPY q127PTAPnotSealDonut
q129PTAPnotSealDonut = TOUCH q125PTAPnotSealDonut q126PTAPnotSealDonut
/// Second ring derivation
q0NTAPnotSealDonutNotLU4_NTAPspRes = NOT INTERACT NTAPnotSealDonutNotLU4_NTAPspRes q129PTAPnotSealDonut
q1NTAPnotSealDonutNotLU4_NTAPspRes = DONUT q0NTAPnotSealDonutNotLU4_NTAPspRes < 2
q5NTAPnotSealDonutNotLU4_NTAPspRes = COPY q1NTAPnotSealDonutNotLU4_NTAPspRes
q128PTAPnotSealDonut = q126PTAPnotSealDonut NOT ENCLOSE q1NTAPnotSealDonutNotLU4_NTAPspRes
q130PTAPnotSealDonut = TOUCH q129PTAPnotSealDonut q128PTAPnotSealDonut
q3NTAPnotSealDonutNotLU4_NTAPspRes = (HOLES q5NTAPnotSealDonutNotLU4_NTAPspRes) ENCLOSE q130PTAPnotSealDonut
q4NTAPnotSealDonutNotLU4_NTAPspRes = ((q3NTAPnotSealDonutNotLU4_NTAPspRes NOT q5NTAPnotSealDonutNotLU4_NTAPspRes) NOT q130PTAPnotSealDonut) NOT q128PTAPnotSealDonut
q6NTAPnotSealDonutNotLU4_NTAPspRes = TOUCH q4NTAPnotSealDonutNotLU4_NTAPspRes q130PTAPnotSealDonut
q14NTAPnotSealDonutNotLU4_NTAPspRes = TOUCH q5NTAPnotSealDonutNotLU4_NTAPspRes q6NTAPnotSealDonutNotLU4_NTAPspRes
q2NTAPnotSealDonutNotLU4_NTAPspRes = HOLES q14NTAPnotSealDonutNotLU4_NTAPspRes INNER
q13NTAPnotSealDonutNotLU4_NTAPspRes = TOUCH q14NTAPnotSealDonutNotLU4_NTAPspRes (q2NTAPnotSealDonutNotLU4_NTAPspRes ENCLOSE q130PTAPnotSealDonut < 2)
lu4_innerRingP_forNTAP = q130PTAPnotSealDonut INSIDE (HOLES q13NTAPnotSealDonutNotLU4_NTAPspRes)
lu4_secondRingN_forNTAP = COPY q13NTAPnotSealDonutNotLU4_NTAPspRes
lu4_PinnerRegion_forNTAP = TOUCH q128PTAPnotSealDonut lu4_innerRingP_forNTAP
lu4_PinnerToSecReg_forNTAP = TOUCH q6NTAPnotSealDonutNotLU4_NTAPspRes lu4_innerRingP_forNTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_forNSD second:lu4_secondRingN_forNSD third:nil
/// Inner ring derivation
q0lu4_innerRingP_forNSD = COPY LU4_NSRCDRNspRes
q0inner_ptap_DGR = DONUT inner_ptap_DGR
q1inner_ptap_DGR = COPY q0inner_ptap_DGR
q3inner_ptap_DGR = (HOLES q1inner_ptap_DGR INNER) ENCLOSE q0lu4_innerRingP_forNSD
q2inner_ptap_DGR = COPY q3inner_ptap_DGR
q5inner_ptap_DGR = TOUCH q1inner_ptap_DGR q2inner_ptap_DGR
/// Second ring derivation
q0second_ntap_DGR = NOT INTERACT second_ntap_DGR q5inner_ptap_DGR
q1second_ntap_DGR = DONUT q0second_ntap_DGR
q5second_ntap_DGR = COPY q1second_ntap_DGR
q4inner_ptap_DGR = q2inner_ptap_DGR NOT ENCLOSE q1second_ntap_DGR
q6inner_ptap_DGR = TOUCH q5inner_ptap_DGR q4inner_ptap_DGR
q3second_ntap_DGR = (HOLES q5second_ntap_DGR) ENCLOSE q6inner_ptap_DGR
q4second_ntap_DGR = ((q3second_ntap_DGR NOT q5second_ntap_DGR) NOT q6inner_ptap_DGR) NOT q4inner_ptap_DGR
q6second_ntap_DGR = TOUCH q4second_ntap_DGR q6inner_ptap_DGR
q14second_ntap_DGR = TOUCH q5second_ntap_DGR q6second_ntap_DGR
q2second_ntap_DGR = HOLES q14second_ntap_DGR INNER
q13second_ntap_DGR = TOUCH q14second_ntap_DGR (q2second_ntap_DGR ENCLOSE q6inner_ptap_DGR)
lu4_innerRingP_forNSD = q6inner_ptap_DGR INSIDE (HOLES q13second_ntap_DGR)
lu4_secondRingN_forNSD = COPY q13second_ntap_DGR
lu4_PinnerRegion_forNSD = TOUCH q4inner_ptap_DGR lu4_innerRingP_forNSD
lu4_PinnerToSecReg_forNSD = TOUCH q6second_ntap_DGR lu4_innerRingP_forNSD
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_forNSD_nodnwell second:lu4_secondRingN_forNSD_nodnwell third:nil
/// Inner ring derivation
q0lu4_innerRingP_forNSD_nodnwell = COPY LU4_NSRCDRNspRes_psub
q0inner_ptap_DGR_nodnwell = DONUT inner_ptap_DGR_nodnwell
q1inner_ptap_DGR_nodnwell = COPY q0inner_ptap_DGR_nodnwell
q3inner_ptap_DGR_nodnwell = (HOLES q1inner_ptap_DGR_nodnwell INNER) ENCLOSE q0lu4_innerRingP_forNSD_nodnwell
q2inner_ptap_DGR_nodnwell = COPY q3inner_ptap_DGR_nodnwell
q5inner_ptap_DGR_nodnwell = TOUCH q1inner_ptap_DGR_nodnwell q2inner_ptap_DGR_nodnwell
/// Second ring derivation
q15second_ntap_DGR = NOT INTERACT second_ntap_DGR q5inner_ptap_DGR_nodnwell
q16second_ntap_DGR = DONUT q15second_ntap_DGR
q20second_ntap_DGR = COPY q16second_ntap_DGR
q4inner_ptap_DGR_nodnwell = q2inner_ptap_DGR_nodnwell NOT ENCLOSE q16second_ntap_DGR
q6inner_ptap_DGR_nodnwell = TOUCH q5inner_ptap_DGR_nodnwell q4inner_ptap_DGR_nodnwell
q18second_ntap_DGR = (HOLES q20second_ntap_DGR) ENCLOSE q6inner_ptap_DGR_nodnwell
q19second_ntap_DGR = ((q18second_ntap_DGR NOT q20second_ntap_DGR) NOT q6inner_ptap_DGR_nodnwell) NOT q4inner_ptap_DGR_nodnwell
q21second_ntap_DGR = TOUCH q19second_ntap_DGR q6inner_ptap_DGR_nodnwell
q29second_ntap_DGR = TOUCH q20second_ntap_DGR q21second_ntap_DGR
q17second_ntap_DGR = HOLES q29second_ntap_DGR INNER
q28second_ntap_DGR = TOUCH q29second_ntap_DGR (q17second_ntap_DGR ENCLOSE q6inner_ptap_DGR_nodnwell)
lu4_innerRingP_forNSD_nodnwell = q6inner_ptap_DGR_nodnwell INSIDE (HOLES q28second_ntap_DGR)
lu4_secondRingN_forNSD_nodnwell = COPY q28second_ntap_DGR
lu4_PinnerRegion_forNSD_nodnwell = TOUCH q4inner_ptap_DGR_nodnwell lu4_innerRingP_forNSD_nodnwell
lu4_PinnerToSecReg_forNSD_nodnwell = TOUCH q21second_ntap_DGR lu4_innerRingP_forNSD_nodnwell
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_forNSD_dnwell second:lu4_secondRingN_forNSD_dnwell third:nil
/// Inner ring derivation
q0lu4_innerRingP_forNSD_dnwell = COPY LU4_NSRCDRNspRes_pwell
q0inner_ptap_DGR_dnwell = DONUT inner_ptap_DGR_dnwell
q1inner_ptap_DGR_dnwell = COPY q0inner_ptap_DGR_dnwell
q3inner_ptap_DGR_dnwell = (HOLES q1inner_ptap_DGR_dnwell INNER) ENCLOSE q0lu4_innerRingP_forNSD_dnwell
q2inner_ptap_DGR_dnwell = COPY q3inner_ptap_DGR_dnwell
q5inner_ptap_DGR_dnwell = TOUCH q1inner_ptap_DGR_dnwell q2inner_ptap_DGR_dnwell
/// Second ring derivation
q30second_ntap_DGR = NOT INTERACT second_ntap_DGR q5inner_ptap_DGR_dnwell
q31second_ntap_DGR = DONUT q30second_ntap_DGR
q35second_ntap_DGR = COPY q31second_ntap_DGR
q4inner_ptap_DGR_dnwell = q2inner_ptap_DGR_dnwell NOT ENCLOSE q31second_ntap_DGR
q6inner_ptap_DGR_dnwell = TOUCH q5inner_ptap_DGR_dnwell q4inner_ptap_DGR_dnwell
q33second_ntap_DGR = (HOLES q35second_ntap_DGR) ENCLOSE q6inner_ptap_DGR_dnwell
q34second_ntap_DGR = ((q33second_ntap_DGR NOT q35second_ntap_DGR) NOT q6inner_ptap_DGR_dnwell) NOT q4inner_ptap_DGR_dnwell
q36second_ntap_DGR = TOUCH q34second_ntap_DGR q6inner_ptap_DGR_dnwell
q44second_ntap_DGR = TOUCH q35second_ntap_DGR q36second_ntap_DGR
q32second_ntap_DGR = HOLES q44second_ntap_DGR INNER
q43second_ntap_DGR = TOUCH q44second_ntap_DGR (q32second_ntap_DGR ENCLOSE q6inner_ptap_DGR_dnwell)
lu4_innerRingP_forNSD_dnwell = q6inner_ptap_DGR_dnwell INSIDE (HOLES q43second_ntap_DGR)
lu4_secondRingN_forNSD_dnwell = COPY q43second_ntap_DGR
lu4_PinnerRegion_forNSD_dnwell = TOUCH q4inner_ptap_DGR_dnwell lu4_innerRingP_forNSD_dnwell
lu4_PinnerToSecReg_forNSD_dnwell = TOUCH q36second_ntap_DGR lu4_innerRingP_forNSD_dnwell
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_forPSD second:lu4_secondRingP_forPSD third:nil
/// Inner ring derivation
q0lu4_innerRingN_forPSD = COPY LU4_PSRCDRNspRes
q0inner_ntap_DGR = DONUT inner_ntap_DGR
q1inner_ntap_DGR = COPY q0inner_ntap_DGR
q3inner_ntap_DGR = (HOLES q1inner_ntap_DGR INNER) ENCLOSE q0lu4_innerRingN_forPSD
q2inner_ntap_DGR = COPY q3inner_ntap_DGR
q5inner_ntap_DGR = TOUCH q1inner_ntap_DGR q2inner_ntap_DGR
/// Second ring derivation
q0second_ptap_DGR = NOT INTERACT second_ptap_DGR q5inner_ntap_DGR
q1second_ptap_DGR = DONUT q0second_ptap_DGR
q5second_ptap_DGR = COPY q1second_ptap_DGR
q4inner_ntap_DGR = q2inner_ntap_DGR NOT ENCLOSE q1second_ptap_DGR
q6inner_ntap_DGR = TOUCH q5inner_ntap_DGR q4inner_ntap_DGR
q3second_ptap_DGR = (HOLES q5second_ptap_DGR) ENCLOSE q6inner_ntap_DGR
q4second_ptap_DGR = ((q3second_ptap_DGR NOT q5second_ptap_DGR) NOT q6inner_ntap_DGR) NOT q4inner_ntap_DGR
q6second_ptap_DGR = TOUCH q4second_ptap_DGR q6inner_ntap_DGR
q14second_ptap_DGR = TOUCH q5second_ptap_DGR q6second_ptap_DGR
q2second_ptap_DGR = HOLES q14second_ptap_DGR INNER
q13second_ptap_DGR = TOUCH q14second_ptap_DGR (q2second_ptap_DGR ENCLOSE q6inner_ntap_DGR)
lu4_innerRingN_forPSD = q6inner_ntap_DGR INSIDE (HOLES q13second_ptap_DGR)
lu4_secondRingP_forPSD = COPY q13second_ptap_DGR
lu4_NinnerRegion_forPSD = TOUCH q4inner_ntap_DGR lu4_innerRingN_forPSD
lu4_NinnerToSecReg_forPSD = TOUCH q6second_ptap_DGR lu4_innerRingN_forPSD
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_forPTAP second:lu4_secondRingP_forPTAP third:nil
/// Inner ring derivation
q0lu4_innerRingN_forPTAP = COPY LU4_PTAPspRes_PW
q138NTAPnotSealDonut = DONUT NTAPnotSealDonut < 2
q139NTAPnotSealDonut = COPY q138NTAPnotSealDonut
q141NTAPnotSealDonut = (HOLES q139NTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingN_forPTAP
q140NTAPnotSealDonut = COPY q141NTAPnotSealDonut
q143NTAPnotSealDonut = TOUCH q139NTAPnotSealDonut q140NTAPnotSealDonut
/// Second ring derivation
q0PWPTAPnotSealDonutNotLU4_PWPTAPspRes = NOT INTERACT PWPTAPnotSealDonutNotLU4_PWPTAPspRes q143NTAPnotSealDonut
q1PWPTAPnotSealDonutNotLU4_PWPTAPspRes = DONUT q0PWPTAPnotSealDonutNotLU4_PWPTAPspRes
q5PWPTAPnotSealDonutNotLU4_PWPTAPspRes = COPY q1PWPTAPnotSealDonutNotLU4_PWPTAPspRes
q142NTAPnotSealDonut = q140NTAPnotSealDonut NOT ENCLOSE q1PWPTAPnotSealDonutNotLU4_PWPTAPspRes
q144NTAPnotSealDonut = TOUCH q143NTAPnotSealDonut q142NTAPnotSealDonut
q3PWPTAPnotSealDonutNotLU4_PWPTAPspRes = (HOLES q5PWPTAPnotSealDonutNotLU4_PWPTAPspRes) ENCLOSE q144NTAPnotSealDonut
q4PWPTAPnotSealDonutNotLU4_PWPTAPspRes = ((q3PWPTAPnotSealDonutNotLU4_PWPTAPspRes NOT q5PWPTAPnotSealDonutNotLU4_PWPTAPspRes) NOT q144NTAPnotSealDonut) NOT q142NTAPnotSealDonut
q6PWPTAPnotSealDonutNotLU4_PWPTAPspRes = TOUCH q4PWPTAPnotSealDonutNotLU4_PWPTAPspRes q144NTAPnotSealDonut
q14PWPTAPnotSealDonutNotLU4_PWPTAPspRes = TOUCH q5PWPTAPnotSealDonutNotLU4_PWPTAPspRes q6PWPTAPnotSealDonutNotLU4_PWPTAPspRes
q2PWPTAPnotSealDonutNotLU4_PWPTAPspRes = HOLES q14PWPTAPnotSealDonutNotLU4_PWPTAPspRes INNER
q13PWPTAPnotSealDonutNotLU4_PWPTAPspRes = TOUCH q14PWPTAPnotSealDonutNotLU4_PWPTAPspRes (q2PWPTAPnotSealDonutNotLU4_PWPTAPspRes ENCLOSE q144NTAPnotSealDonut < 2)
lu4_innerRingN_forPTAP = q144NTAPnotSealDonut INSIDE (HOLES q13PWPTAPnotSealDonutNotLU4_PWPTAPspRes)
lu4_secondRingP_forPTAP = COPY q13PWPTAPnotSealDonutNotLU4_PWPTAPspRes
lu4_NinnerRegion_forPTAP = TOUCH q142NTAPnotSealDonut lu4_innerRingN_forPTAP
lu4_NinnerToSecReg_forPTAP = TOUCH q6PWPTAPnotSealDonutNotLU4_PWPTAPspRes lu4_innerRingN_forPTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_Ntr_forNTAP second:lu4_secondRingN_Ntr_forNTAP third:nil
/// Inner ring derivation
q0lu4_innerRingP_Ntr_forNTAP = COPY LU4_NTAPspNtr
q131PTAPnotSealDonut = DONUT PTAPnotSealDonut < 2
q132PTAPnotSealDonut = COPY q131PTAPnotSealDonut
q134PTAPnotSealDonut = (HOLES q132PTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingP_Ntr_forNTAP
q133PTAPnotSealDonut = COPY q134PTAPnotSealDonut
q136PTAPnotSealDonut = TOUCH q132PTAPnotSealDonut q133PTAPnotSealDonut
/// Second ring derivation
q0NTAPnotSealDonutNotLU4_NTAPspNtr = NOT INTERACT NTAPnotSealDonutNotLU4_NTAPspNtr q136PTAPnotSealDonut
q1NTAPnotSealDonutNotLU4_NTAPspNtr = DONUT q0NTAPnotSealDonutNotLU4_NTAPspNtr < 2
q5NTAPnotSealDonutNotLU4_NTAPspNtr = COPY q1NTAPnotSealDonutNotLU4_NTAPspNtr
q135PTAPnotSealDonut = q133PTAPnotSealDonut NOT ENCLOSE q1NTAPnotSealDonutNotLU4_NTAPspNtr
q137PTAPnotSealDonut = TOUCH q136PTAPnotSealDonut q135PTAPnotSealDonut
q3NTAPnotSealDonutNotLU4_NTAPspNtr = (HOLES q5NTAPnotSealDonutNotLU4_NTAPspNtr) ENCLOSE q137PTAPnotSealDonut
q4NTAPnotSealDonutNotLU4_NTAPspNtr = ((q3NTAPnotSealDonutNotLU4_NTAPspNtr NOT q5NTAPnotSealDonutNotLU4_NTAPspNtr) NOT q137PTAPnotSealDonut) NOT q135PTAPnotSealDonut
q6NTAPnotSealDonutNotLU4_NTAPspNtr = TOUCH q4NTAPnotSealDonutNotLU4_NTAPspNtr q137PTAPnotSealDonut
q14NTAPnotSealDonutNotLU4_NTAPspNtr = TOUCH q5NTAPnotSealDonutNotLU4_NTAPspNtr q6NTAPnotSealDonutNotLU4_NTAPspNtr
q2NTAPnotSealDonutNotLU4_NTAPspNtr = HOLES q14NTAPnotSealDonutNotLU4_NTAPspNtr INNER
q13NTAPnotSealDonutNotLU4_NTAPspNtr = TOUCH q14NTAPnotSealDonutNotLU4_NTAPspNtr (q2NTAPnotSealDonutNotLU4_NTAPspNtr ENCLOSE q137PTAPnotSealDonut < 2)
lu4_innerRingP_Ntr_forNTAP = q137PTAPnotSealDonut INSIDE (HOLES q13NTAPnotSealDonutNotLU4_NTAPspNtr)
lu4_secondRingN_Ntr_forNTAP = COPY q13NTAPnotSealDonutNotLU4_NTAPspNtr
lu4_PinnerRegion_Ntr_forNTAP = TOUCH q135PTAPnotSealDonut lu4_innerRingP_Ntr_forNTAP
lu4_PinnerToSecReg_Ntr_forNTAP = TOUCH q6NTAPnotSealDonutNotLU4_NTAPspNtr lu4_innerRingP_Ntr_forNTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingP_Ntr_forNSD second:lu4_secondRingN_Ntr_forNSD third:nil
/// Inner ring derivation
q0lu4_innerRingP_Ntr_forNSD = COPY LU4_NSRCDRNspNtr
q7inner_ptap_DGR = DONUT inner_ptap_DGR < 2
q8inner_ptap_DGR = COPY q7inner_ptap_DGR
q10inner_ptap_DGR = (HOLES q8inner_ptap_DGR INNER) ENCLOSE q0lu4_innerRingP_Ntr_forNSD
q9inner_ptap_DGR = COPY q10inner_ptap_DGR
q12inner_ptap_DGR = TOUCH q8inner_ptap_DGR q9inner_ptap_DGR
/// Second ring derivation
q45second_ntap_DGR = NOT INTERACT second_ntap_DGR q12inner_ptap_DGR
q46second_ntap_DGR = DONUT q45second_ntap_DGR < 2
q50second_ntap_DGR = COPY q46second_ntap_DGR
q11inner_ptap_DGR = q9inner_ptap_DGR NOT ENCLOSE q46second_ntap_DGR
q13inner_ptap_DGR = TOUCH q12inner_ptap_DGR q11inner_ptap_DGR
q48second_ntap_DGR = (HOLES q50second_ntap_DGR) ENCLOSE q13inner_ptap_DGR
q49second_ntap_DGR = ((q48second_ntap_DGR NOT q50second_ntap_DGR) NOT q13inner_ptap_DGR) NOT q11inner_ptap_DGR
q51second_ntap_DGR = TOUCH q49second_ntap_DGR q13inner_ptap_DGR
q59second_ntap_DGR = TOUCH q50second_ntap_DGR q51second_ntap_DGR
q47second_ntap_DGR = HOLES q59second_ntap_DGR INNER
q58second_ntap_DGR = TOUCH q59second_ntap_DGR (q47second_ntap_DGR ENCLOSE q13inner_ptap_DGR < 2)
lu4_innerRingP_Ntr_forNSD = q13inner_ptap_DGR INSIDE (HOLES q58second_ntap_DGR)
lu4_secondRingN_Ntr_forNSD = COPY q58second_ntap_DGR
lu4_PinnerRegion_Ntr_forNSD = TOUCH q11inner_ptap_DGR lu4_innerRingP_Ntr_forNSD
lu4_PinnerToSecReg_Ntr_forNSD = TOUCH q51second_ntap_DGR lu4_innerRingP_Ntr_forNSD
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_Ntr_forPTAP second:lu4_secondRingP_Ntr_forPTAP third:nil
/// Inner ring derivation
q0lu4_innerRingN_Ntr_forPTAP = COPY LU4_PTAPspNtr_PW
q145NTAPnotSealDonut = DONUT NTAPnotSealDonut < 2
q146NTAPnotSealDonut = COPY q145NTAPnotSealDonut
q148NTAPnotSealDonut = (HOLES q146NTAPnotSealDonut INNER) ENCLOSE q0lu4_innerRingN_Ntr_forPTAP
q147NTAPnotSealDonut = COPY q148NTAPnotSealDonut
q150NTAPnotSealDonut = TOUCH q146NTAPnotSealDonut q147NTAPnotSealDonut
/// Second ring derivation
q0PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = NOT INTERACT PWPTAPnotSealDonutNotLU4_PWPTAPspNtr q150NTAPnotSealDonut
q1PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = DONUT q0PWPTAPnotSealDonutNotLU4_PWPTAPspNtr < 2
q5PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = COPY q1PWPTAPnotSealDonutNotLU4_PWPTAPspNtr
q149NTAPnotSealDonut = q147NTAPnotSealDonut NOT ENCLOSE q1PWPTAPnotSealDonutNotLU4_PWPTAPspNtr
q151NTAPnotSealDonut = TOUCH q150NTAPnotSealDonut q149NTAPnotSealDonut
q3PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = (HOLES q5PWPTAPnotSealDonutNotLU4_PWPTAPspNtr) ENCLOSE q151NTAPnotSealDonut
q4PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = ((q3PWPTAPnotSealDonutNotLU4_PWPTAPspNtr NOT q5PWPTAPnotSealDonutNotLU4_PWPTAPspNtr) NOT q151NTAPnotSealDonut) NOT q149NTAPnotSealDonut
q6PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = TOUCH q4PWPTAPnotSealDonutNotLU4_PWPTAPspNtr q151NTAPnotSealDonut
q14PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = TOUCH q5PWPTAPnotSealDonutNotLU4_PWPTAPspNtr q6PWPTAPnotSealDonutNotLU4_PWPTAPspNtr
q2PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = HOLES q14PWPTAPnotSealDonutNotLU4_PWPTAPspNtr INNER
q13PWPTAPnotSealDonutNotLU4_PWPTAPspNtr = TOUCH q14PWPTAPnotSealDonutNotLU4_PWPTAPspNtr (q2PWPTAPnotSealDonutNotLU4_PWPTAPspNtr ENCLOSE q151NTAPnotSealDonut < 2)
lu4_innerRingN_Ntr_forPTAP = q151NTAPnotSealDonut INSIDE (HOLES q13PWPTAPnotSealDonutNotLU4_PWPTAPspNtr)
lu4_secondRingP_Ntr_forPTAP = COPY q13PWPTAPnotSealDonutNotLU4_PWPTAPspNtr
lu4_NinnerRegion_Ntr_forPTAP = TOUCH q149NTAPnotSealDonut lu4_innerRingN_Ntr_forPTAP
lu4_NinnerToSecReg_Ntr_forPTAP = TOUCH q6PWPTAPnotSealDonutNotLU4_PWPTAPspNtr lu4_innerRingN_Ntr_forPTAP
/// CALderiveGuardRings complete
/// CALderiveGuardRings: Deriving guard ring inner:lu4_innerRingN_Ntr_forPSD second:lu4_secondRingP_Ntr_forPSD third:nil
/// Inner ring derivation
q0lu4_innerRingN_Ntr_forPSD = COPY LU4_PSRCDRNspNtr
q7inner_ntap_DGR = DONUT inner_ntap_DGR < 2
q8inner_ntap_DGR = COPY q7inner_ntap_DGR
q10inner_ntap_DGR = (HOLES q8inner_ntap_DGR INNER) ENCLOSE q0lu4_innerRingN_Ntr_forPSD
q9inner_ntap_DGR = COPY q10inner_ntap_DGR
q12inner_ntap_DGR = TOUCH q8inner_ntap_DGR q9inner_ntap_DGR
/// Second ring derivation
q15second_ptap_DGR = NOT INTERACT second_ptap_DGR q12inner_ntap_DGR
q16second_ptap_DGR = DONUT q15second_ptap_DGR < 2
q20second_ptap_DGR = COPY q16second_ptap_DGR
q11inner_ntap_DGR = q9inner_ntap_DGR NOT ENCLOSE q16second_ptap_DGR
q13inner_ntap_DGR = TOUCH q12inner_ntap_DGR q11inner_ntap_DGR
q18second_ptap_DGR = (HOLES q20second_ptap_DGR) ENCLOSE q13inner_ntap_DGR
q19second_ptap_DGR = ((q18second_ptap_DGR NOT q20second_ptap_DGR) NOT q13inner_ntap_DGR) NOT q11inner_ntap_DGR
q21second_ptap_DGR = TOUCH q19second_ptap_DGR q13inner_ntap_DGR
q29second_ptap_DGR = TOUCH q20second_ptap_DGR q21second_ptap_DGR
q17second_ptap_DGR = HOLES q29second_ptap_DGR INNER
q28second_ptap_DGR = TOUCH q29second_ptap_DGR (q17second_ptap_DGR ENCLOSE q13inner_ntap_DGR < 2)
lu4_innerRingN_Ntr_forPSD = q13inner_ntap_DGR INSIDE (HOLES q28second_ptap_DGR)
lu4_secondRingP_Ntr_forPSD = COPY q28second_ptap_DGR
lu4_NinnerRegion_Ntr_forPSD = TOUCH q11inner_ntap_DGR lu4_innerRingN_Ntr_forPSD
lu4_NinnerToSecReg_Ntr_forPSD = TOUCH q21second_ptap_DGR lu4_innerRingN_Ntr_forPSD
/// CALderiveGuardRings complete
bad_nsigPadDiff_psubTmp = LU4_NSRCDRNspRes_psub NOT lu4_PinnerRegion_forNSD_nodnwell
bad_nsigPadDiff_pwellTmp = LU4_NSRCDRNspRes_pwell NOT lu4_PinnerRegion_forNSD_dnwell
bad_nsigPadTapTmp = LU4_NTAPspRes NOT lu4_PinnerRegion_forNTAP
misplaced_nsigPadDiff_psub = LU4_NSRCDRNspRes_psub AND inner_hole_ntap_DGR
misplaced_nsigPadDiff_pwell = LU4_NSRCDRNspRes_pwell AND inner_hole_ntap_DGR
misplaced_nsigPadTap = LU4_NTAPspRes AND inner_hole_ntap_DGR
bad_nsigPadDiff_psub = bad_nsigPadDiff_psubTmp NOT (LU4_s8esdg4_cells OR misplaced_nsigPadDiff_psub)
bad_nsigPadDiff_pwell = bad_nsigPadDiff_pwellTmp NOT (LU4_s8esdg4_cells OR misplaced_nsigPadDiff_pwell)
bad_nsigPadTap = bad_nsigPadTapTmp NOT (LU4_s8esdg4_cells OR misplaced_nsigPadTap)
"r_149_lu.4.2" {
@ lu.4.2: Double guard rings are required around signal pad n+ diffusion in psub
COPY bad_nsigPadDiff_psub
}
"r_150_lu.4.2" {
@ lu.4.2: Double guard rings are required around signal pad n+ diffusion in pwell
COPY bad_nsigPadDiff_pwell
}
"r_151_lu.4.2" {
@ lu.4.2: Double guard rings are required around signal pad n+ tap in Nwell
COPY bad_nsigPadTap
}
bad_psigPadDiff = LU4_PSRCDRNspRes NOT (LU4_s8esdg4_cells OR lu4_NinnerRegion_forPSD)
misplaced_psigPadDiff = (LU4_PSRCDRNspRes AND inner_hole_ptap_DGR) NOT lu_4_3_1_exempt
bad_psigPadTap = LU4_PTAPspRes_PW NOT (LU4_s8esdg4_cells OR lu4_NinnerRegion_forPTAP)
"r_152_lu.4.3" {
@ lu.4.3: Double guard rings are required around signal pad p+ diffusion
COPY bad_psigPadDiff
}
"r_153_lu.4.3" {
@ lu.4.3: Double guard rings are required around signal pad p+ tap in pwell
COPY bad_psigPadTap
}
lu_4_3_1_exemptCells = (EXTENT CELL "s8_esd_localdiode_lv" ORIGINAL) OR (EXTENT CELL "s8_esd_localdiode_hv" ORIGINAL)
lu_4_3_1_exempt = lu_4_3_1_exemptCells OR
(LU4_nwellSameNet OR nonVccNwell)
lu4_innerRingN_forPSD_notExempt = lu4_innerRingN_forPSD NOT lu_4_3_1_exempt
lu4_secondRingP_forPSD_notExempt = lu4_secondRingP_forPSD NOT lu_4_3_1_exempt
lu4_innerRingN_forPSD_notExempt_sPwrConn = NET AREA RATIO lu4_innerRingN_forPSD_notExempt switched_intPower_met1 > 0
lu4_innerRingN_forPSD_notExempt_Chk = lu4_innerRingN_forPSD_notExempt NOT lu4_innerRingN_forPSD_notExempt_sPwrConn
lu4_innerRingN_forPTAP_sPwrConn = NET AREA RATIO lu4_innerRingN_forPTAP switched_intPower_met1 > 0
lu4_innerRingN_forPTAP_Chk = lu4_innerRingN_forPTAP NOT lu4_innerRingN_forPTAP_sPwrConn
"r_154_lu.4.3.1" {
@ lu.4.3.1: Guard rings around signal pad p+ diffusion are in interchanged order
COPY misplaced_psigPadDiff
}
"r_155_lu.4.3.1" {
@ lu.4.3.1: lu4_innerRingN_forPSD_notExempt_Chk must connect to vccNets or switched_power nets
NOT NET lu4_innerRingN_forPSD_notExempt_Chk "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
}
"r_156_lu.4.3.1" {
@ lu.4.3.1: lu4_secondRingP_forPSD_notExempt must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET lu4_secondRingP_forPSD_notExempt "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
"r_157_lu.4.3.1" {
@ lu.4.3.1: lu4_innerRingN_forPTAP_Chk must connect to vccNets or switched_power nets
NOT NET lu4_innerRingN_forPTAP_Chk "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
}
"r_158_lu.4.3.1" {
@ lu.4.3.1: lu4_secondRingP_forPTAP must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET lu4_secondRingP_forPTAP "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
"r_159_lu.4.2.1" {
@ lu.4.2.1: Guard rings around signal pad n+ diffusion in psub are in interchanged order
COPY misplaced_nsigPadDiff_psub
}
"r_160_lu.4.2.1" {
@ lu.4.2.1: Guard rings around signal pad n+ diffusion in pwell are in interchanged order
COPY misplaced_nsigPadDiff_pwell
}
"r_161_lu.4.2.1" {
@ lu.4.2.1: Guard rings around signal pad n+ tap are in interchanged order
COPY misplaced_nsigPadTap
}
"r_162_lu.4.2.1" {
@ lu.4.2.1: P-tap inner guardring around signal pad N tap must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET lu4_innerRingP_forNTAP "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
lu4_secondRingN_forNTAP_sPwrConn = NET AREA RATIO lu4_secondRingN_forNTAP switched_intPower_met1 > 0
lu4_secondRingN_forNTAP_Chk = lu4_secondRingN_forNTAP NOT lu4_secondRingN_forNTAP_sPwrConn
/// CALconnectZone started - zoneName was "zone_20"
CONNECT PolyNoRes polyResEsdLib
CONNECT LU4_NSRCDRNspRes_pwell NSRCDRN
CONNECT lu4_secondRingN_forNTAP_Chk NTAP
/// CALconnectZone done. zoneName is now zone_21
"r_163_lu.4.2.1" {
@ lu.4.2.1: lu4_secondRingN_forNTAP_Chk must connect to externally connected non-regulated vccNets
NOT NET lu4_secondRingN_forNTAP_Chk "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
}
LU4_NSRCDRNspResPwell_thruEsdLibRes = NET LU4_NSRCDRNspRes_pwell "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
LU4_NSRCDRNspResPwellXmtB = LU4_NSRCDRNspResPwell_thruEsdLibRes NOT ioNSD
lu4_innerRingP_forNSD_dnwellXmtB = TOUCH lu4_innerRingP_forNSD_dnwell (INTERACT lu4_PinnerRegion_forNSD_dnwell LU4_NSRCDRNspResPwellXmtB)
LU4_NSRCDRNspResPwellSRCDRN_all = NSRCDRN AND (INTERACT NDIFF LU4_NSRCDRNspResPwellXmtB)
lu4_innerRingP_forNSD_dnwellXmtB_con = STAMP lu4_innerRingP_forNSD_dnwellXmtB BY PTAP
LU4_innerRingP_forNSD_dnwellXmtB_2 = NET AREA RATIO lu4_innerRingP_forNSD_dnwellXmtB_con LU4_NSRCDRNspResPwellSRCDRN_all > 0
lu4_innerRingP_forNSD_dnwellXmtB_2_chk = lu4_innerRingP_forNSD_dnwellXmtB NOT LU4_innerRingP_forNSD_dnwellXmtB_2
lu4_innerRingP_forNSD_dnwellnotXmtB = lu4_innerRingP_forNSD_dnwell NOT lu4_innerRingP_forNSD_dnwellXmtB
/// CALconnectZone started - zoneName was "zone_21"
CONNECT LU4_NSRCDRNspRes_pwell NSRCDRN
CONNECT lu4_innerRingP_forNSD_dnwellnotXmtB isoSubPTap
CONNECT lu4_innerRingP_forNSD_dnwellXmtB_2_chk isoSubPTap
CONNECT lu4_innerRingP_forNSD_nodnwell PTAP
CONNECT lu4_secondRingN_forNSD_dnwell NTAP
CONNECT lu4_secondRingN_forNSD_nodnwell NTAP
/// CALconnectZone done. zoneName is now zone_22
"r_164_lu.4.2.1" {
@ lu.4.2.1: P-tap inner guardring in psub around signal pad Ndiff in psub must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET lu4_innerRingP_forNSD_nodnwell "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
lu4_innerRingP_forNSDPwellXmtB_1 = NET AREA RATIO lu4_innerRingP_forNSD_dnwellnotXmtB LU4_NSRCDRNspRes_pwell > 0
lu4_innerRingP_forNSDPwellNonXmt = lu4_innerRingP_forNSD_dnwell NOT (lu4_innerRingP_forNSDPwellXmtB_1 OR lu4_innerRingP_forNSD_dnwellXmtB)
lu4_secRingN_forNSD_nodnwl_sPwrConn = NET AREA RATIO lu4_secondRingN_forNSD_nodnwell switched_intPower_met1 > 0
lu4_secRingN_forNSD_nodnwl_Chk = lu4_secondRingN_forNSD_nodnwell NOT lu4_secRingN_forNSD_nodnwl_sPwrConn
lu4_secRingN_forNSD_dnwell_sPwrConn = NET AREA RATIO lu4_secondRingN_forNSD_dnwell switched_intPower_met1 > 0
lu4_secRingN_forNSD_dnwell_Chk = lu4_secondRingN_forNSD_dnwell NOT lu4_secRingN_forNSD_dnwell_sPwrConn
/// CALconnectZone started - zoneName was "zone_22"
CONNECT lu4_innerRingP_forNSDPwellNonXmt isoSubPTap
CONNECT lu4_secRingN_forNSD_nodnwl_Chk NTAP
CONNECT lu4_secRingN_forNSD_dnwell_Chk NTAP
/// CALconnectZone done. zoneName is now zone_23
lu4_innerRingP_forNSDPwellNonXmt_notVss = NOT NET lu4_innerRingP_forNSDPwellNonXmt "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
lu4_innerRingP_forNSDNonXmt_notVss_Pwell = NOT INTERACT (INTERACT isoPwell lu4_innerRingP_forNSDPwellNonXmt_notVss) vssNSD
lu4_innerRingP_forNSDPwellXmtB_3_tmp = lu4_innerRingP_forNSDPwellNonXmt AND lu4_innerRingP_forNSDNonXmt_notVss_Pwell
/// CALconnectZone started - zoneName was "zone_23"
CONNECT lu4_innerRingP_forNSDPwellXmtB_3_tmp PTAP
/// CALconnectZone done. zoneName is now zone_24
lu4_innerRingP_forNSDPwellXmtB_3 = (NET AREA RATIO lu4_innerRingP_forNSDPwellXmtB_3_tmp NSRCDRN > 0) OR (NET AREA RATIO lu4_innerRingP_forNSDPwellXmtB_3_tmp PSRCDRN > 0)
lu4_innerRingP_forNSDPwellChk = lu4_innerRingP_forNSD_dnwell NOT (lu4_innerRingP_forNSDPwellXmtB_1 OR
(lu4_innerRingP_forNSD_dnwellXmtB OR lu4_innerRingP_forNSDPwellXmtB_3))
lu4_innerRingP_forNSDPwellChk_Exempt = EXTENT CELL "s8iom0s8_top_tp2" "s8usbpdv2_20sbu_sw_ls_unit" ORIGINAL
lu4_innerRingP_forNSDPwellChk_nonExempt = lu4_innerRingP_forNSDPwellChk NOT lu4_innerRingP_forNSDPwellChk_Exempt
/// CALconnectZone started - zoneName was "zone_24"
CONNECT lu4_innerRingP_forNSDPwellChk_nonExempt isoSubPTap
/// CALconnectZone done. zoneName is now zone_25
"r_165_lu.4.2.1" {
@ lu.4.2.1: P-tap inner guardring in pwell around signal pad Ndiff in pwell must connect to ("vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio")
NOT NET lu4_innerRingP_forNSDPwellChk_nonExempt "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
"r_166_lu.4.2.1" {
@ lu.4.2.1: lu4_innerRingP_forNSD_dnwellXmtB_2_chk must connect to vccNets, vss nets
NOT NET lu4_innerRingP_forNSD_dnwellXmtB_2_chk "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2" "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
}
"r_167_lu.4.2.1" {
@ lu.4.2.1: lu4_secRingN_forNSD_nodnwl_Chk must connect to externally connected non-regulated vccNets
NOT NET lu4_secRingN_forNSD_nodnwl_Chk "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
}
"r_168_lu.4.2.1" {
@ lu.4.2.1: lu4_secRingN_forNSD_dnwell_Chk must connect to externally connected non-regulated vccNets
NOT NET lu4_secRingN_forNSD_dnwell_Chk "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio"
}
LU4_nwellIOconn = NET nwell "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
LU4_dnwellConn = STAMP dnwANDnwell by nwell
LU4_dnwellIoXmpt = INSIDE CELL dnwelldg "s8usbpd_esd_cdm_uhv" "s8usbpd_csa_top" "s8usbpd_ngdo_top" "s8usbpd_esd_21v_vbus_iec" "s8usbpdv2_20vconn_sw_300ma_ocp_switch2" "s8usbpdv2_esd_21v_hbm" "s8rf_n20vhv1_aup" "s8usbpdv2_csa_esd_hbm_21v_10x4" "s8usbpdv2_csa_top" "s8usbpd_esd_shv_iec" "s8usbpd_esd_shv_sbu_iec" "s8usbpdv2_esd_shv_iec_sbu" "s8usbpd_pgdo_pu_top" "s8usbpd_pgdo_top" "s8usbpd_ea_top" "s8usbpdv2_20sbu_sw_ovp_ngate" "s8usbpdv2_20vconn_sw_300ma_ovp_ngate"
dnwellIo = (NET AREA RATIO LU4_dnwellConn LU4_nwellIOconn > 0) NOT LU4_dnwellIoXmpt
"r_169_lu.4.2.1a" {
@ lu.4.2.1a: IO pad connected deep nwell is not allowed
COPY dnwellIo
}
lu4_4_exemptRing = INSIDE CELL tap "s8ppscio_sio_pudrvr_reg_pu" "p3ag_gpio_amx" "p3ag_gpio_ag" "s8psoc3io_sio_pudrvr_reg_pu" "s8iom0s8_sio_pudrvr_reg_pu"
lu4_innerRingN_forPSD_nonExempt = lu4_innerRingN_forPSD NOT lu4_4_exemptRing
lu4_4_innerPNSDLicon1 = licon1 AND lu4_innerRingP_forNSD
lu4_4_innerPNSDLi1 = (INTERACT Li1 lu4_4_innerPNSDLicon1) AND lu4_innerRingP_forNSD
lu4_4_innerPNSDMcon = mcon AND lu4_4_innerPNSDLi1
lu4_4_innerPNSDMet1 = (INTERACT metal1 lu4_4_innerPNSDMcon) AND lu4_innerRingP_forNSD
q2lu4_innerRingP_forNSD = lu4_innerRingP_forNSD OUTSIDE lu4_4_innerPNSDLi1
q3lu4_innerRingP_forNSD = NOT DONUT (lu4_innerRingP_forNSD AND lu4_4_innerPNSDLi1)
q1lu4_innerRingP_forNSD = q2lu4_innerRingP_forNSD OR q3lu4_innerRingP_forNSD
"r_170_lu.4.4" {
@ lu.4.4: lu4_innerRingP_forNSD requires a continuous Li1 strapping ring
q4lu4_innerRingP_forNSD = COPY q1lu4_innerRingP_forNSD
COPY q4lu4_innerRingP_forNSD
}
lu4_4_innerPNTAPLicon1 = licon1 AND lu4_innerRingP_forNTAP
lu4_4_innerPNTAPLi1 = (INTERACT Li1 lu4_4_innerPNTAPLicon1) AND lu4_innerRingP_forNTAP
lu4_4_innerPNTAPMcon = mcon AND lu4_4_innerPNTAPLi1
lu4_4_innerPNTAPMet1 = (INTERACT metal1 lu4_4_innerPNTAPMcon) AND lu4_innerRingP_forNTAP
q2lu4_innerRingP_forNTAP = lu4_innerRingP_forNTAP OUTSIDE lu4_4_innerPNTAPLi1
q3lu4_innerRingP_forNTAP = NOT DONUT (lu4_innerRingP_forNTAP AND lu4_4_innerPNTAPLi1)
q1lu4_innerRingP_forNTAP = q2lu4_innerRingP_forNTAP OR q3lu4_innerRingP_forNTAP
"r_171_lu.4.4" {
@ lu.4.4: P-tap inner guardring around signal pad N tap requires a continuous Li1 strapping ring
q4lu4_innerRingP_forNTAP = COPY q1lu4_innerRingP_forNTAP
COPY q4lu4_innerRingP_forNTAP
}
lu4_4_secondNNSDLicon1 = licon1 AND lu4_secondRingN_forNSD
lu4_4_secondNNSDLi1 = (INTERACT Li1 lu4_4_secondNNSDLicon1) AND lu4_secondRingN_forNSD
lu4_4_secondNNSDMcon = mcon AND lu4_4_secondNNSDLi1
lu4_4_secondNNSDMet1 = (INTERACT metal1 lu4_4_secondNNSDMcon) AND lu4_secondRingN_forNSD
q1lu4_secondRingN_forNSD = lu4_secondRingN_forNSD OUTSIDE lu4_4_secondNNSDLi1
q2lu4_secondRingN_forNSD = NOT DONUT (lu4_secondRingN_forNSD AND lu4_4_secondNNSDLi1)
q0lu4_secondRingN_forNSD = q1lu4_secondRingN_forNSD OR q2lu4_secondRingN_forNSD
"r_172_lu.4.4" {
@ lu.4.4: lu4_secondRingN_forNSD requires a continuous Li1 strapping ring
q3lu4_secondRingN_forNSD = COPY q0lu4_secondRingN_forNSD
COPY q3lu4_secondRingN_forNSD
}
lu4_4_secondNNTAPLicon1 = licon1 AND lu4_secondRingN_forNTAP
lu4_4_secondNNTAPLi1 = (INTERACT Li1 lu4_4_secondNNTAPLicon1) AND lu4_secondRingN_forNTAP
lu4_4_secondNNTAPMcon = mcon AND lu4_4_secondNNTAPLi1
lu4_4_secondNNTAPMet1 = (INTERACT metal1 lu4_4_secondNNTAPMcon) AND lu4_secondRingN_forNTAP
q1lu4_secondRingN_forNTAP = lu4_secondRingN_forNTAP OUTSIDE lu4_4_secondNNTAPLi1
q2lu4_secondRingN_forNTAP = NOT DONUT (lu4_secondRingN_forNTAP AND lu4_4_secondNNTAPLi1)
q0lu4_secondRingN_forNTAP = q1lu4_secondRingN_forNTAP OR q2lu4_secondRingN_forNTAP
"r_173_lu.4.4" {
@ lu.4.4: N-tap second guardring around signal pad N tap requires a continuous Li1 strapping ring
q3lu4_secondRingN_forNTAP = COPY q0lu4_secondRingN_forNTAP
COPY q3lu4_secondRingN_forNTAP
}
lu4_4_innerNPSDLicon1 = licon1 AND lu4_innerRingN_forPSD_nonExempt
lu4_4_innerNPSDLi1 = (INTERACT Li1 lu4_4_innerNPSDLicon1) AND lu4_innerRingN_forPSD_nonExempt
lu4_4_innerNPSDMcon = mcon AND lu4_4_innerNPSDLi1
lu4_4_innerNPSDMet1 = (INTERACT metal1 lu4_4_innerNPSDMcon) AND lu4_innerRingN_forPSD_nonExempt
q1lu4_innerRingN_forPSD_nonExempt = lu4_innerRingN_forPSD_nonExempt OUTSIDE lu4_4_innerNPSDLi1
q2lu4_innerRingN_forPSD_nonExempt = NOT DONUT (lu4_innerRingN_forPSD_nonExempt AND lu4_4_innerNPSDLi1)
q0lu4_innerRingN_forPSD_nonExempt = q1lu4_innerRingN_forPSD_nonExempt OR q2lu4_innerRingN_forPSD_nonExempt
"r_174_lu.4.4" {
@ lu.4.4: lu4_innerRingN_forPSD_nonExempt requires a continuous Li1 strapping ring
q3lu4_innerRingN_forPSD_nonExempt = COPY q0lu4_innerRingN_forPSD_nonExempt
COPY q3lu4_innerRingN_forPSD_nonExempt
}
lu4_4_secondPPSDLicon1 = licon1 AND lu4_secondRingP_forPSD
lu4_4_secondPPSDLi1 = (INTERACT Li1 lu4_4_secondPPSDLicon1) AND lu4_secondRingP_forPSD
lu4_4_secondPPSDMcon = mcon AND lu4_4_secondPPSDLi1
lu4_4_secondPPSDMet1 = (INTERACT metal1 lu4_4_secondPPSDMcon) AND lu4_secondRingP_forPSD
q1lu4_secondRingP_forPSD = lu4_secondRingP_forPSD OUTSIDE lu4_4_secondPPSDLi1
q2lu4_secondRingP_forPSD = NOT DONUT (lu4_secondRingP_forPSD AND lu4_4_secondPPSDLi1)
q0lu4_secondRingP_forPSD = q1lu4_secondRingP_forPSD OR q2lu4_secondRingP_forPSD
"r_175_lu.4.4" {
@ lu.4.4: P-tap second guardring around signal pad P diffusion requires a continuous Li1 strapping ring
q3lu4_secondRingP_forPSD = COPY q0lu4_secondRingP_forPSD
COPY q3lu4_secondRingP_forPSD
}
lu4_4_innerNPTAPLicon1 = licon1 AND lu4_innerRingN_forPTAP
lu4_4_innerNPTAPLi1 = (INTERACT Li1 lu4_4_innerNPTAPLicon1) AND lu4_innerRingN_forPTAP
lu4_4_innerNPTAPMcon = mcon AND lu4_4_innerNPTAPLi1
lu4_4_innerNPTAPMet1 = (INTERACT metal1 lu4_4_innerNPTAPMcon) AND lu4_innerRingN_forPTAP
q2lu4_innerRingN_forPTAP = lu4_innerRingN_forPTAP OUTSIDE lu4_4_innerNPTAPLi1
q3lu4_innerRingN_forPTAP = NOT DONUT (lu4_innerRingN_forPTAP AND lu4_4_innerNPTAPLi1)
q1lu4_innerRingN_forPTAP = q2lu4_innerRingN_forPTAP OR q3lu4_innerRingN_forPTAP
"r_176_lu.4.4" {
@ lu.4.4: lu4_innerRingN_forPTAP requires a continuous Li1 strapping ring
q4lu4_innerRingN_forPTAP = COPY q1lu4_innerRingN_forPTAP
COPY q4lu4_innerRingN_forPTAP
}
lu4_4_secondPPTAPLicon1 = licon1 AND lu4_secondRingP_forPTAP
lu4_4_secondPPTAPLi1 = (INTERACT Li1 lu4_4_secondPPTAPLicon1) AND lu4_secondRingP_forPTAP
lu4_4_secondPPTAPMcon = mcon AND lu4_4_secondPPTAPLi1
lu4_4_secondPPTAPMet1 = (INTERACT metal1 lu4_4_secondPPTAPMcon) AND lu4_secondRingP_forPTAP
q1lu4_secondRingP_forPTAP = lu4_secondRingP_forPTAP OUTSIDE lu4_4_secondPPTAPLi1
q2lu4_secondRingP_forPTAP = NOT DONUT (lu4_secondRingP_forPTAP AND lu4_4_secondPPTAPLi1)
q0lu4_secondRingP_forPTAP = q1lu4_secondRingP_forPTAP OR q2lu4_secondRingP_forPTAP
"r_177_lu.4.4" {
@ lu.4.4: lu4_secondRingP_forPTAP requires a continuous Li1 strapping ring
q3lu4_secondRingP_forPTAP = COPY q0lu4_secondRingP_forPTAP
COPY q3lu4_secondRingP_forPTAP
}
/// CALminStrappingWidth: checking rule lu.4.6 on layer lu4_secondRingN_Ntr_forNSD
q0Licon1Nfom = Licon1Nfom AND lu4_secondRingN_Ntr_forNSD
q1Licon1Nfom = INTERACT Li1 q0Licon1Nfom
q0Li1 = q1Licon1Nfom AND lu4_secondRingN_Ntr_forNSD
q1Li1 = q1Licon1Nfom AND (SIZE lu4_secondRingN_Ntr_forNSD BY 0.85)
q2Li1 = WITH WIDTH q1Li1 < 0.85
q3Li1 = INTERACT q2Li1 (q2Li1 AND lu4_secondRingN_Ntr_forNSD)
"r_178_lu.4.6" {
@ lu.4.6: 0.85 min strap width of Li1 on lu4_secondRingN_Ntr_forNSD
q4Li1 = COPY q3Li1
COPY q4Li1
}
q0Mcon = Mcon AND q0Li1
q1Mcon = INTERACT Met1 q0Mcon
q0Met1 = q1Mcon AND lu4_secondRingN_Ntr_forNSD
q1Met1 = q1Mcon AND (SIZE lu4_secondRingN_Ntr_forNSD BY 0.65)
q2Met1 = WITH WIDTH q1Met1 < 0.65
q3Met1 = INTERACT q2Met1 (q2Met1 AND q0Li1)
"r_179_lu.4.6" {
@ lu.4.6: 0.65 min strap width of Met1 on lu4_secondRingN_Ntr_forNSD
q4Met1 = COPY q3Met1
COPY q4Met1
}
/// CALminStrappingWidth: done checking rule lu.4.6 on layer lu4_secondRingN_Ntr_forNSD
/// CALminStrappingWidth: checking rule lu.4.6 on layer lu4_secondRingN_Ntr_forNTAP
q2Licon1Nfom = Licon1Nfom AND lu4_secondRingN_Ntr_forNTAP
q3Licon1Nfom = INTERACT Li1 q2Licon1Nfom
q5Li1 = q3Licon1Nfom AND lu4_secondRingN_Ntr_forNTAP
q6Li1 = q3Licon1Nfom AND (SIZE lu4_secondRingN_Ntr_forNTAP BY 0.85)
q7Li1 = WITH WIDTH q6Li1 < 0.85
q8Li1 = INTERACT q7Li1 (q7Li1 AND lu4_secondRingN_Ntr_forNTAP)
"r_180_lu.4.6" {
@ lu.4.6: 0.85 min strap width of Li1 on lu4_secondRingN_Ntr_forNTAP
q9Li1 = COPY q8Li1
COPY q9Li1
}
q2Mcon = Mcon AND q5Li1
q3Mcon = INTERACT Met1 q2Mcon
q5Met1 = q3Mcon AND lu4_secondRingN_Ntr_forNTAP
q6Met1 = q3Mcon AND (SIZE lu4_secondRingN_Ntr_forNTAP BY 0.65)
q7Met1 = WITH WIDTH q6Met1 < 0.65
q8Met1 = INTERACT q7Met1 (q7Met1 AND q5Li1)
"r_181_lu.4.6" {
@ lu.4.6: 0.65 min strap width of Met1 on lu4_secondRingN_Ntr_forNTAP
q9Met1 = COPY q8Met1
COPY q9Met1
}
/// CALminStrappingWidth: done checking rule lu.4.6 on layer lu4_secondRingN_Ntr_forNTAP
/// CALminStrappingWidth: checking rule lu.4.6 on layer lu4_secondRingP_Ntr_forPSD
q0Licon1Pfom = Licon1Pfom AND lu4_secondRingP_Ntr_forPSD
q1Licon1Pfom = INTERACT Li1 q0Licon1Pfom
q10Li1 = q1Licon1Pfom AND lu4_secondRingP_Ntr_forPSD
q11Li1 = q1Licon1Pfom AND (SIZE lu4_secondRingP_Ntr_forPSD BY 0.85)
q12Li1 = WITH WIDTH q11Li1 < 0.85
q13Li1 = INTERACT q12Li1 (q12Li1 AND lu4_secondRingP_Ntr_forPSD)
"r_182_lu.4.6" {
@ lu.4.6: 0.85 min strap width of Li1 on lu4_secondRingP_Ntr_forPSD
q14Li1 = COPY q13Li1
COPY q14Li1
}
q4Mcon = Mcon AND q10Li1
q5Mcon = INTERACT Met1 q4Mcon
q10Met1 = q5Mcon AND lu4_secondRingP_Ntr_forPSD
q11Met1 = q5Mcon AND (SIZE lu4_secondRingP_Ntr_forPSD BY 0.65)
q12Met1 = WITH WIDTH q11Met1 < 0.65
q13Met1 = INTERACT q12Met1 (q12Met1 AND q10Li1)
"r_183_lu.4.6" {
@ lu.4.6: 0.65 min strap width of Met1 on lu4_secondRingP_Ntr_forPSD
q14Met1 = COPY q13Met1
COPY q14Met1
}
/// CALminStrappingWidth: done checking rule lu.4.6 on layer lu4_secondRingP_Ntr_forPSD
/// CALminStrappingWidth: checking rule lu.4.6 on layer lu4_secondRingP_Ntr_forPTAP
q2Licon1Pfom = Licon1Pfom AND lu4_secondRingP_Ntr_forPTAP
q3Licon1Pfom = INTERACT Li1 q2Licon1Pfom
q15Li1 = q3Licon1Pfom AND lu4_secondRingP_Ntr_forPTAP
q16Li1 = q3Licon1Pfom AND (SIZE lu4_secondRingP_Ntr_forPTAP BY 0.85)
q17Li1 = WITH WIDTH q16Li1 < 0.85
q18Li1 = INTERACT q17Li1 (q17Li1 AND lu4_secondRingP_Ntr_forPTAP)
"r_184_lu.4.6" {
@ lu.4.6: 0.85 min strap width of Li1 on lu4_secondRingP_Ntr_forPTAP
q19Li1 = COPY q18Li1
COPY q19Li1
}
q6Mcon = Mcon AND q15Li1
q7Mcon = INTERACT Met1 q6Mcon
q15Met1 = q7Mcon AND lu4_secondRingP_Ntr_forPTAP
q16Met1 = q7Mcon AND (SIZE lu4_secondRingP_Ntr_forPTAP BY 0.65)
q17Met1 = WITH WIDTH q16Met1 < 0.65
q18Met1 = INTERACT q17Met1 (q17Met1 AND q15Li1)
"r_185_lu.4.6" {
@ lu.4.6: 0.65 min strap width of Met1 on lu4_secondRingP_Ntr_forPTAP
q19Met1 = COPY q18Met1
COPY q19Met1
}
/// CALminStrappingWidth: done checking rule lu.4.6 on layer lu4_secondRingP_Ntr_forPTAP
lu4_6_1_exempt = INSIDE CELL tap "s8_esd_signal_40_sym_hv_2k_dnwl_aup1_b"
lu4_innerRingP_Ntr_forNSD_nonExempt = lu4_innerRingP_Ntr_forNSD NOT lu4_6_1_exempt
/// CALminStrappingWidth: checking rule lu.4.6.1 on layer lu4_innerRingP_Ntr_forNSD_nonExempt
q4Licon1Pfom = Licon1Pfom AND lu4_innerRingP_Ntr_forNSD_nonExempt
q5Licon1Pfom = INTERACT Li1 q4Licon1Pfom
q20Li1 = q5Licon1Pfom AND lu4_innerRingP_Ntr_forNSD_nonExempt
q21Li1 = q5Licon1Pfom AND (SIZE lu4_innerRingP_Ntr_forNSD_nonExempt BY 0.85)
q22Li1 = WITH WIDTH q21Li1 < 0.85
q23Li1 = INTERACT q22Li1 (q22Li1 AND lu4_innerRingP_Ntr_forNSD_nonExempt)
"r_186_lu.4.6.1" {
@ lu.4.6.1: 0.85 min strap width of Li1 on lu4_innerRingP_Ntr_forNSD_nonExempt
q24Li1 = COPY q23Li1
COPY q24Li1
}
q8Mcon = Mcon AND q20Li1
q9Mcon = INTERACT Met1 q8Mcon
q20Met1 = q9Mcon AND lu4_innerRingP_Ntr_forNSD_nonExempt
q21Met1 = q9Mcon AND (SIZE lu4_innerRingP_Ntr_forNSD_nonExempt BY 0.65)
q22Met1 = WITH WIDTH q21Met1 < 0.65
q23Met1 = INTERACT q22Met1 (q22Met1 AND q20Li1)
"r_187_lu.4.6.1" {
@ lu.4.6.1: 0.65 min strap width of Met1 on lu4_innerRingP_Ntr_forNSD_nonExempt
q24Met1 = COPY q23Met1
COPY q24Met1
}
/// CALminStrappingWidth: done checking rule lu.4.6.1 on layer lu4_innerRingP_Ntr_forNSD_nonExempt
/// CALminStrappingWidth: checking rule lu.4.6.1 on layer lu4_innerRingP_Ntr_forNTAP
q6Licon1Pfom = Licon1Pfom AND lu4_innerRingP_Ntr_forNTAP
q7Licon1Pfom = INTERACT Li1 q6Licon1Pfom
q25Li1 = q7Licon1Pfom AND lu4_innerRingP_Ntr_forNTAP
q26Li1 = q7Licon1Pfom AND (SIZE lu4_innerRingP_Ntr_forNTAP BY 0.85)
q27Li1 = WITH WIDTH q26Li1 < 0.85
q28Li1 = INTERACT q27Li1 (q27Li1 AND lu4_innerRingP_Ntr_forNTAP)
"r_188_lu.4.6.1" {
@ lu.4.6.1: 0.85 min strap width of Li1 on lu4_innerRingP_Ntr_forNTAP
q29Li1 = COPY q28Li1
COPY q29Li1
}
q10Mcon = Mcon AND q25Li1
q11Mcon = INTERACT Met1 q10Mcon
q25Met1 = q11Mcon AND lu4_innerRingP_Ntr_forNTAP
q26Met1 = q11Mcon AND (SIZE lu4_innerRingP_Ntr_forNTAP BY 0.65)
q27Met1 = WITH WIDTH q26Met1 < 0.65
q28Met1 = INTERACT q27Met1 (q27Met1 AND q25Li1)
"r_189_lu.4.6.1" {
@ lu.4.6.1: 0.65 min strap width of Met1 on lu4_innerRingP_Ntr_forNTAP
q29Met1 = COPY q28Met1
COPY q29Met1
}
/// CALminStrappingWidth: done checking rule lu.4.6.1 on layer lu4_innerRingP_Ntr_forNTAP
/// CALminStrappingWidth: checking rule lu.4.6.1 on layer lu4_innerRingN_Ntr_forPSD
q4Licon1Nfom = Licon1Nfom AND lu4_innerRingN_Ntr_forPSD
q5Licon1Nfom = INTERACT Li1 q4Licon1Nfom
q30Li1 = q5Licon1Nfom AND lu4_innerRingN_Ntr_forPSD
q31Li1 = q5Licon1Nfom AND (SIZE lu4_innerRingN_Ntr_forPSD BY 0.85)
q32Li1 = WITH WIDTH q31Li1 < 0.85
q33Li1 = INTERACT q32Li1 (q32Li1 AND lu4_innerRingN_Ntr_forPSD)
"r_190_lu.4.6.1" {
@ lu.4.6.1: 0.85 min strap width of Li1 on lu4_innerRingN_Ntr_forPSD
q34Li1 = COPY q33Li1
COPY q34Li1
}
q12Mcon = Mcon AND q30Li1
q13Mcon = INTERACT Met1 q12Mcon
q30Met1 = q13Mcon AND lu4_innerRingN_Ntr_forPSD
q31Met1 = q13Mcon AND (SIZE lu4_innerRingN_Ntr_forPSD BY 0.65)
q32Met1 = WITH WIDTH q31Met1 < 0.65
q33Met1 = INTERACT q32Met1 (q32Met1 AND q30Li1)
"r_191_lu.4.6.1" {
@ lu.4.6.1: 0.65 min strap width of Met1 on lu4_innerRingN_Ntr_forPSD
q34Met1 = COPY q33Met1
COPY q34Met1
}
/// CALminStrappingWidth: done checking rule lu.4.6.1 on layer lu4_innerRingN_Ntr_forPSD
/// CALminStrappingWidth: checking rule lu.4.6.1 on layer lu4_innerRingN_Ntr_forPTAP
q6Licon1Nfom = Licon1Nfom AND lu4_innerRingN_Ntr_forPTAP
q7Licon1Nfom = INTERACT Li1 q6Licon1Nfom
q35Li1 = q7Licon1Nfom AND lu4_innerRingN_Ntr_forPTAP
q36Li1 = q7Licon1Nfom AND (SIZE lu4_innerRingN_Ntr_forPTAP BY 0.85)
q37Li1 = WITH WIDTH q36Li1 < 0.85
q38Li1 = INTERACT q37Li1 (q37Li1 AND lu4_innerRingN_Ntr_forPTAP)
"r_192_lu.4.6.1" {
@ lu.4.6.1: 0.85 min strap width of Li1 on lu4_innerRingN_Ntr_forPTAP
q39Li1 = COPY q38Li1
COPY q39Li1
}
q14Mcon = Mcon AND q35Li1
q15Mcon = INTERACT Met1 q14Mcon
q35Met1 = q15Mcon AND lu4_innerRingN_Ntr_forPTAP
q36Met1 = q15Mcon AND (SIZE lu4_innerRingN_Ntr_forPTAP BY 0.65)
q37Met1 = WITH WIDTH q36Met1 < 0.65
q38Met1 = INTERACT q37Met1 (q37Met1 AND q35Li1)
"r_193_lu.4.6.1" {
@ lu.4.6.1: 0.65 min strap width of Met1 on lu4_innerRingN_Ntr_forPTAP
q39Met1 = COPY q38Met1
COPY q39Met1
}
/// CALminStrappingWidth: done checking rule lu.4.6.1 on layer lu4_innerRingN_Ntr_forPTAP
lu4_7_secondNVccRing = lu4_secondRingN_Ntr_forNTAP OR lu4_secondRingN_Ntr_forNSD
lu4_7_secondPVssRing = lu4_secondRingP_Ntr_forPTAP OR lu4_secondRingP_Ntr_forPSD
/// CALconnectZone started - zoneName was "zone_25"
CONNECT NTAP lu4_7_secondNVccRing
CONNECT PTAP lu4_7_secondPVssRing
/// CALconnectZone done. zoneName is now zone_26
lu4_7_pad_met1 = COPY padCellMet1
lu4_7_pad_met2 = COPY padCellMet2
lu4_7_pad_met3 = COPY padCellMet3
lu4_7_pad_met4 = COPY padCellMet4
lu4_7_pad_met5 = COPY padCellMet5
/// CALderivePath called
lu4_7_secondNVccRings_chk = COPY lu4_7_secondNVccRing
lu4_7_secondPVssRings_chk = COPY lu4_7_secondPVssRing
/// CALderiveLayersConnectedToShape called for shapes (lu4_7_secondPVssRing lu4_7_secondNVccRing)
q0Via4 = NET AREA RATIO Via4 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q0Via3 = NET AREA RATIO Via3 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q0Via2 = NET AREA RATIO Via2 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q0Via = NET AREA RATIO Via OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q16Mcon = NET AREA RATIO Mcon OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q8Licon1Pfom = NET AREA RATIO Licon1Pfom OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q8Licon1Nfom = NET AREA RATIO Licon1Nfom OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q0Met5 = NET AREA RATIO Met5 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q0Met4 = NET AREA RATIO Met4 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q0Met3 = NET AREA RATIO Met3 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q0Met2 = NET AREA RATIO Met2 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q40Met1 = NET AREA RATIO Met1 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
q40Li1 = NET AREA RATIO Li1 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
lu4_7_topMet_pad = NET AREA RATIO pad OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
lu4_7_switched_intPower_met1 = NET AREA RATIO switched_intPower_met1 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
lu4_7_reg_s8tee_reg_top_met2 = NET AREA RATIO reg_s8tee_reg_top_met2 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
lu4_7_reg_mtdr_io_reg_mockup_met2 = NET AREA RATIO reg_mtdr_io_reg_mockup_met2 OVER lu4_7_secondPVssRing lu4_7_secondNVccRing > 0
/// CALderiveLayersConnectedToShape done for shapes (lu4_7_secondPVssRing lu4_7_secondNVccRing)
lu4_7_li1 = WITH WIDTH q40Li1 >= 3.0
lu4_7_met1 = WITH WIDTH q40Met1 >= 3.0
lu4_7_met2 = WITH WIDTH q0Met2 >= 3.0
lu4_7_met3 = WITH WIDTH q0Met3 >= 3.0
lu4_7_met4 = WITH WIDTH q0Met4 >= 3.0
lu4_7_met5 = WITH WIDTH q0Met5 >= 3.0
q0lu4_8_licon1N = q40Li1 AND lu4_7_secondNVccRings_chk
q1lu4_8_licon1N = SIZE q8Licon1Nfom BY 1 INSIDE OF q0lu4_8_licon1N STEP 0.12
lu4_8_ary_licon1N = INTERACT q1lu4_8_licon1N q8Licon1Nfom >= 6.0
lu4_8_licon1N = q8Licon1Nfom AND lu4_8_ary_licon1N
q0lu4_8_licon1P = q40Li1 AND lu4_7_secondPVssRings_chk
q1lu4_8_licon1P = SIZE q8Licon1Pfom BY 1 INSIDE OF q0lu4_8_licon1P STEP 0.12
lu4_8_ary_licon1P = INTERACT q1lu4_8_licon1P q8Licon1Pfom >= 6.0
lu4_8_licon1P = q8Licon1Pfom AND lu4_8_ary_licon1P
q0lu4_8_mcon = q40Met1 AND q40Li1
q1lu4_8_mcon = SIZE q16Mcon BY 1 INSIDE OF q0lu4_8_mcon STEP 0.095
lu4_8_ary_mcon = INTERACT q1lu4_8_mcon q16Mcon >= 6.0
lu4_8_mcon = q16Mcon AND lu4_8_ary_mcon
q0lu4_8_via = q0Met2 AND q40Met1
q1lu4_8_via = SIZE q0Via BY 1 INSIDE OF q0lu4_8_via STEP 0.095
lu4_8_ary_via = INTERACT q1lu4_8_via q0Via >= 6.0
lu4_8_via = q0Via AND lu4_8_ary_via
q0lu4_8_via2 = q0Met3 AND q0Met2
q1lu4_8_via2 = SIZE q0Via2 BY 1 INSIDE OF q0lu4_8_via2 STEP 0.095
lu4_8_ary_via2 = INTERACT q1lu4_8_via2 q0Via2 >= 6.0
lu4_8_via2 = q0Via2 AND lu4_8_ary_via2
q0lu4_8_via3 = q0Met4 AND q0Met3
q1lu4_8_via3 = SIZE q0Via3 BY 1 INSIDE OF q0lu4_8_via3 STEP 0.21
lu4_8_ary_via3 = INTERACT q1lu4_8_via3 q0Via3 >= 6.0
lu4_8_via3 = q0Via3 AND lu4_8_ary_via3
q0lu4_8_via4 = q0Met5 AND q0Met4
q1lu4_8_via4 = SIZE q0Via4 BY 1 INSIDE OF q0lu4_8_via4 STEP 0.21
lu4_8_ary_via4 = INTERACT q1lu4_8_via4 q0Via4 >= 6.0
lu4_8_via4 = q0Via4 AND lu4_8_ary_via4
/// CALconnectZone started - zoneName was "zone_26"
CONNECT lu4_7_met1 lu4_7_li1 BY lu4_8_mcon
CONNECT lu4_7_met2 lu4_7_met1 BY lu4_8_via
CONNECT lu4_7_met3 lu4_7_met2 BY lu4_8_via2
CONNECT lu4_7_switched_intPower_met1 lu4_7_met1
CONNECT lu4_7_met4 lu4_7_met3 BY lu4_8_via3
CONNECT lu4_7_met5 lu4_7_met4 BY lu4_8_via4
CONNECT lu4_7_topMet_pad lu4_7_met5
CONNECT lu4_7_met2 lu4_7_reg_mtdr_io_reg_mockup_met2
CONNECT lu4_7_met2 lu4_7_reg_s8tee_reg_top_met2
CONNECT lu4_8_ary_licon1N lu4_8_ary_licon1P
CONNECT lu4_8_ary_licon1N lu4_8_ary_mcon
CONNECT lu4_8_ary_licon1P lu4_8_ary_mcon
CONNECT lu4_8_ary_mcon lu4_8_ary_via
CONNECT lu4_8_ary_via lu4_8_ary_via2
CONNECT lu4_8_ary_via2 lu4_8_ary_via3
CONNECT lu4_8_ary_via3 lu4_8_ary_via4
CONNECT lu4_7_pad_met1 lu4_7_met1
CONNECT lu4_7_pad_met2 lu4_7_met2
CONNECT lu4_7_pad_met3 lu4_7_met3
CONNECT lu4_7_pad_met4 lu4_7_met4
CONNECT lu4_7_pad_met5 lu4_7_met5
CONNECT lu4_7_pad_met2 lu4_7_pad_met1 BY lu4_8_via
CONNECT lu4_7_pad_met3 lu4_7_pad_met2 BY lu4_8_via2
CONNECT lu4_7_pad_met4 lu4_7_pad_met3 BY lu4_8_via3
CONNECT lu4_7_pad_met5 lu4_7_pad_met4 BY lu4_8_via4
CONNECT lu4_7_li1 lu4_8_ary_licon1N
CONNECT lu4_7_secondNVccRings_chk lu4_8_ary_licon1N
CONNECT lu4_8_licon1N lu4_8_ary_licon1N
CONNECT lu4_7_li1 lu4_8_ary_licon1P
CONNECT lu4_7_secondPVssRings_chk lu4_8_ary_licon1P
CONNECT lu4_8_licon1P lu4_8_ary_licon1P
CONNECT lu4_7_met1 lu4_8_ary_mcon
CONNECT lu4_7_li1 lu4_8_ary_mcon
CONNECT lu4_8_mcon lu4_8_ary_mcon
CONNECT lu4_7_met2 lu4_8_ary_via
CONNECT lu4_7_met1 lu4_8_ary_via
CONNECT lu4_8_via lu4_8_ary_via
CONNECT lu4_7_met3 lu4_8_ary_via2
CONNECT lu4_7_met2 lu4_8_ary_via2
CONNECT lu4_8_via2 lu4_8_ary_via2
CONNECT lu4_7_met4 lu4_8_ary_via3
CONNECT lu4_7_met3 lu4_8_ary_via3
CONNECT lu4_8_via3 lu4_8_ary_via3
CONNECT lu4_7_met5 lu4_8_ary_via4
CONNECT lu4_7_met4 lu4_8_ary_via4
CONNECT lu4_8_via4 lu4_8_ary_via4
/// CALconnectZone done. zoneName is now zone_26
/// CALderivePath done
/// CALmustHavePathTo: checking from lu4_7_secondPVssRings_chk to (lu4_7_topMet_pad)
q0lu4_7_secondPVssRings_chk = NET AREA RATIO lu4_7_secondPVssRings_chk OVER lu4_7_topMet_pad == 0
"r_194_lu.4.7/8.ptap" {
@ lu.4.7/8.ptap: p-tap outer guardring must be connected to vss pad/psuedo-pad(block_level) using the correct path width and contact count
@ Li1 with minimum of 3.0 micron width
@ Met1 with minimum of 3.0 micron width
@ Met2 with minimum of 3.0 micron width
@ Met3 with minimum of 3.0 micron width
@ Met4 with minimum of 3.0 micron width
@ Met5 with minimum of 3.0 micron width
@ Minimum 6.0 Licon1Nfom connecting lu4_7_secondNVccRing to Li1
@ Li1 connecting to wide lu4_7_secondNVccRing within 2 microns of Licon1Nfom
@ Minimum 6.0 Licon1Pfom connecting lu4_7_secondPVssRing to Li1
@ Li1 connecting to wide lu4_7_secondPVssRing within 2 microns of Licon1Pfom
@ Minimum 6.0 Mcon connecting Li1 to Met1
@ Met1 connecting to wide Li1 within 2 microns of Mcon
@ Minimum 6.0 Via connecting Met1 to Met2
@ Met2 connecting to wide Met1 within 2 microns of Via
@ Minimum 6.0 Via2 connecting Met2 to Met3
@ Met3 connecting to wide Met2 within 2 microns of Via2
@ Minimum 6.0 Via3 connecting Met3 to Met4
@ Met4 connecting to wide Met3 within 2 microns of Via3
@ Minimum 6.0 Via4 connecting Met4 to Met5
@ Met5 connecting to wide Met4 within 2 microns of Via4
@ Layers involved in this check can be found in lu.4.7_8.ptap.db
q1lu4_7_secondPVssRings_chk = COPY q0lu4_7_secondPVssRings_chk
COPY q1lu4_7_secondPVssRings_chk
NET AREA RATIO lu4_8_ary_licon1N OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_8_ary_licon1N
NET AREA RATIO lu4_8_ary_licon1P OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_8_ary_licon1P
NET AREA RATIO lu4_8_ary_mcon OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_8_ary_mcon
NET AREA RATIO lu4_8_ary_via OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_8_ary_via
NET AREA RATIO lu4_8_ary_via2 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_8_ary_via2
NET AREA RATIO lu4_7_li1 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_li1
NET AREA RATIO lu4_7_met1 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_met1
NET AREA RATIO lu4_7_met2 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_met2
NET AREA RATIO lu4_7_met3 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_met3
NET AREA RATIO lu4_7_pad_met1 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_pad_met1
NET AREA RATIO lu4_7_pad_met2 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_pad_met2
NET AREA RATIO lu4_7_pad_met3 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_pad_met3
NET AREA RATIO lu4_8_ary_via3 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_8_ary_via3
NET AREA RATIO lu4_7_met4 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_met4
NET AREA RATIO lu4_7_pad_met4 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_pad_met4
NET AREA RATIO lu4_8_ary_via4 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_8_ary_via4
NET AREA RATIO lu4_7_met5 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_met5
NET AREA RATIO lu4_7_pad_met5 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_pad_met5
NET AREA RATIO lu4_7_reg_mtdr_io_reg_mockup_met2 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_reg_mtdr_io_reg_mockup_met2
NET AREA RATIO lu4_7_reg_s8tee_reg_top_met2 OVER q1lu4_7_secondPVssRings_chk > 0 RDB ONLY "lu.4.7_8.ptap.db" BY LAYER lu4_7_reg_s8tee_reg_top_met2
}
/// CALmustHavePathTo: done checking from lu4_7_secondPVssRings_chk to (lu4_7_topMet_pad)
/// CALmustHavePathTo: checking from lu4_7_secondNVccRings_chk to (lu4_7_reg_mtdr_io_reg_mockup_met2 lu4_7_reg_s8tee_reg_top_met2 lu4_7_switched_intPower_met1 lu4_7_topMet_pad)
q0lu4_7_secondNVccRings_chk = NET AREA RATIO lu4_7_secondNVccRings_chk OVER lu4_7_reg_mtdr_io_reg_mockup_met2 lu4_7_reg_s8tee_reg_top_met2 lu4_7_switched_intPower_met1 lu4_7_topMet_pad == 0
"r_195_lu.4.7/8.ntap" {
@ lu.4.7/8.ntap: n-tap outer guardring must be connected to vcc pad/psuedo-pad(block_level) or a switched_power net using the correct path width and contact count
@ Li1 with minimum of 3.0 micron width
@ Met1 with minimum of 3.0 micron width
@ Met2 with minimum of 3.0 micron width
@ Met3 with minimum of 3.0 micron width
@ Met4 with minimum of 3.0 micron width
@ Met5 with minimum of 3.0 micron width
@ Minimum 6.0 Licon1Nfom connecting lu4_7_secondNVccRing to Li1
@ Li1 connecting to wide lu4_7_secondNVccRing within 2 microns of Licon1Nfom
@ Minimum 6.0 Licon1Pfom connecting lu4_7_secondPVssRing to Li1
@ Li1 connecting to wide lu4_7_secondPVssRing within 2 microns of Licon1Pfom
@ Minimum 6.0 Mcon connecting Li1 to Met1
@ Met1 connecting to wide Li1 within 2 microns of Mcon
@ Minimum 6.0 Via connecting Met1 to Met2
@ Met2 connecting to wide Met1 within 2 microns of Via
@ Minimum 6.0 Via2 connecting Met2 to Met3
@ Met3 connecting to wide Met2 within 2 microns of Via2
@ Minimum 6.0 Via3 connecting Met3 to Met4
@ Met4 connecting to wide Met3 within 2 microns of Via3
@ Minimum 6.0 Via4 connecting Met4 to Met5
@ Met5 connecting to wide Met4 within 2 microns of Via4
@ Layers involved in this check can be found in lu.4.7_8.ntap.db
q1lu4_7_secondNVccRings_chk = COPY q0lu4_7_secondNVccRings_chk
COPY q1lu4_7_secondNVccRings_chk
NET AREA RATIO lu4_8_ary_licon1N OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_8_ary_licon1N
NET AREA RATIO lu4_8_ary_licon1P OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_8_ary_licon1P
NET AREA RATIO lu4_8_ary_mcon OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_8_ary_mcon
NET AREA RATIO lu4_8_ary_via OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_8_ary_via
NET AREA RATIO lu4_8_ary_via2 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_8_ary_via2
NET AREA RATIO lu4_7_li1 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_li1
NET AREA RATIO lu4_7_met1 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_met1
NET AREA RATIO lu4_7_met2 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_met2
NET AREA RATIO lu4_7_met3 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_met3
NET AREA RATIO lu4_7_pad_met1 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_pad_met1
NET AREA RATIO lu4_7_pad_met2 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_pad_met2
NET AREA RATIO lu4_7_pad_met3 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_pad_met3
NET AREA RATIO lu4_8_ary_via3 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_8_ary_via3
NET AREA RATIO lu4_7_met4 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_met4
NET AREA RATIO lu4_7_pad_met4 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_pad_met4
NET AREA RATIO lu4_8_ary_via4 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_8_ary_via4
NET AREA RATIO lu4_7_met5 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_met5
NET AREA RATIO lu4_7_pad_met5 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_pad_met5
NET AREA RATIO lu4_7_reg_mtdr_io_reg_mockup_met2 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_reg_mtdr_io_reg_mockup_met2
NET AREA RATIO lu4_7_reg_s8tee_reg_top_met2 OVER q1lu4_7_secondNVccRings_chk > 0 RDB ONLY "lu.4.7_8.ntap.db" BY LAYER lu4_7_reg_s8tee_reg_top_met2
}
/// CALmustHavePathTo: done checking from lu4_7_secondNVccRings_chk to (lu4_7_reg_mtdr_io_reg_mockup_met2 lu4_7_reg_s8tee_reg_top_met2 lu4_7_switched_intPower_met1 lu4_7_topMet_pad)
LU4_9_NouterRingnarrow = WITH WIDTH (lu4_secondRingN_Ntr_forNSD OR lu4_secondRingN_Ntr_forNTAP) < 0.85
LU4_9_PouterRingnarrow = WITH WIDTH (lu4_secondRingP_Ntr_forPSD OR lu4_secondRingP_Ntr_forPTAP) < 0.85
"r_196_lu.4.9" {
@ lu.4.9: 0.85 um min width of outer guardring tap
COPY LU4_9_NouterRingnarrow
}
"r_197_lu.4.9" {
@ lu.4.9: 0.85 um min width of outer guardring tap
COPY LU4_9_PouterRingnarrow
}
lu4_13_exempt = EXTENT CELL "s8p3ana_upper_region_nopumps" "s8tkm0s8_mux6_no0" ORIGINAL
"r_198_lu.4.13" {
@ lu.4.13: PMOS devices are not allowed in outer Ntap guardring around signal pad N+ diffusion
((INTERACT PDIFF gate) AND (INTERACT nwell (lu4_secondRingN_forNSD OR lu4_secondRingN_forNTAP))) NOT lu4_13_exempt
((INTERACT PDIFF gate) AND (INTERACT nwell (INTERACT (lu4_secondRingN_forNSD OR lu4_secondRingN_forNTAP) dnwelldg))) NOT lu4_13_exempt
(INTERACT PDIFF gate) AND ((lu4_PinnerToSecReg_forNSD OR lu4_PinnerToSecReg_forNTAP) NOT (INTERACT nwell (INTERACT dnwelldg (lu4_secondRingN_forNTAP OR lu4_secondRingN_forNSD))))
(INTERACT PDIFF gate) AND ((lu4_PinnerToSecReg_forNSD OR lu4_PinnerToSecReg_forNTAP) NOT (INTERACT nwell (lu4_secondRingN_forNTAP OR lu4_secondRingN_forNSD)))
}
"r_199_lu.4.14" {
@ lu.4.14: Diffusion resistors are not allowed within guardrings around signal pad diffusions
NOT INTERACT ((lu4_PinnerRegion_forNSD OR lu4_PinnerRegion_forNTAP) AND diffres) LU4_NSRCDRNspRes
(lu4_PinnerToSecReg_forNSD OR lu4_PinnerToSecReg_forNTAP) AND diffres
((INTERACT nwell (lu4_secondRingN_forNSD OR lu4_secondRingN_forNTAP)) NOT (lu4_PinnerToSecReg_forNSD OR lu4_PinnerToSecReg_forNTAP)) AND diffres
NOT INTERACT ((lu4_NinnerRegion_forPSD OR lu4_NinnerRegion_forPTAP) AND diffres) LU4_PSRCDRNspRes
(lu4_NinnerToSecReg_forPSD OR lu4_NinnerToSecReg_forPTAP) AND diffres
}
/// CALconnectZone started - zoneName was "zone_26"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT NSRCDRN ndiff_esdRes
CONNECT PSRCDRN pdiff_esdRes
CONNECT NSRCDRN ndiff_res
CONNECT PSRCDRN pdiff_res
CONNECT isolatedSubNoPWR pwell_res
CONNECT Met1 Met1EsdResnoVD
CONNECT Met2 Met2EsdResnoVD
CONNECT Met3 Met3EsdResnoVD
CONNECT Met4 Met4EsdResnoVD
CONNECT Met5 Met5EsdResnoVD
CONNECT PolyNoRes poly_resNoEsd
CONNECT PolyNoRes poly_esdRes
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_27
ioNsrcDrnShrtRes = NSDsigPad OR (NET NSRCDRN "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad")
ioPsrcDrnShrtRes = NSDsigPad OR (NET PSRCDRN "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad")
"k_42_ioNsrcDrnShrtRes" {
@ keep: ioNsrcDrnShrtRes - ioNsrcDrnShrtRes
COPY ioNsrcDrnShrtRes
}
"k_43_ioPsrcDrnShrtRes" {
@ keep: ioPsrcDrnShrtRes - ioPsrcDrnShrtRes
COPY ioPsrcDrnShrtRes
}
esdIpRes_blocks_res = (INSIDE CELL polyres "s8_esd_res75only" "s8_esd_res75only_small" "s8_esd_res75only_noshorts" "s8_esd_res75only_noshorts_nometal" "s8_esd_res250" "s8_esd_res250only" "s8_esd_res250only_small") NOT (xmtResPoly OR
(Poly_leaker OR Poly_bias))
nonEsdLibPolyEsdResistor = poly_esdRes NOT esdIpRes_blocks_res
"k_44_esdIpRes_blocks_res" {
@ keep: esdIpRes_blocks_res - esdIpRes_blocks_res
COPY esdIpRes_blocks_res
}
"k_45_poly_resNoEsd" {
@ keep: poly_resNoEsd - poly_resNoEsd
COPY poly_resNoEsd
}
/// CALconnectZone started - zoneName was "zone_27"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT nonEsdLibPolyEsdResistor PolyNoRes
CONNECT nonEsdLibPolyEsdResistor poly_resNoEsd
CONNECT Li1 nonEsdLibPolyEsdResistor BY Licon1ply
CONNECT PolyNoRes poly_resNoEsd
CONNECT NSRCDRN ndiff_esdRes
CONNECT PSRCDRN pdiff_esdRes
CONNECT NSRCDRN ndiff_res
CONNECT PSRCDRN pdiff_res
CONNECT isolatedSubNoPWR pwell_res
CONNECT Met1 Met1EsdResnoVD
CONNECT Met2 Met2EsdResnoVD
CONNECT Met3 Met3EsdResnoVD
CONNECT Met4 Met4EsdResnoVD
CONNECT Met5 Met5EsdResnoVD
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_28
/// CALconnectZone started - zoneName was "zone_28"
CONNECT esdIpRes_blocks_res PolyNoRes
/// CALconnectZone done. zoneName is now zone_29
/// CALconnectZone started - zoneName was "zone_29"
DISCONNECT
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT Met1 Met1EsdResnoVD
CONNECT Met2 Met2EsdResnoVD
CONNECT Met3 Met3EsdResnoVD
CONNECT Met4 Met4EsdResnoVD
CONNECT Met5 Met5EsdResnoVD
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_30
noLi1JumperM1 = WITH TEXT met1 "resistive_met1_ok" textlabel
li1ConVccVss_xmt = WITH TEXT li1 "resistive_li1_ok" textlabel
tapLiconXmt = WITH TEXT tap "resistive_tap_ok" textlabel
noLi1Jumper = WITH TEXT Li1 "li_jumper_ok" textlabel
li1_xmt1 = RECTANGLE li1 ASPECT <= 4
li1_xmt2 = AREA li1 <= 0.25
li1_noXmt = li1 NOT (li1_xmt1 OR
(li1_xmt2 OR noLi1Jumper))
met1ConVcc_checkSPwr = NET AREA RATIO met1 switched_intPower_met1 > 0
liAndMconVcc_spwr = li1ConVccSPwr AND mcon
met1VccConLi1NoVia_spwr = NOT INTERACT (INTERACT met1 floatContactStackVcc_spwr) via
met1VccMultMcon_spwr = INTERACT met1VccConLi1NoVia_spwr liAndMconVcc_spwr >= 1
met1VccMcon_spwr = met1VccMultMcon_spwr AND mcon
met1VccLi_spwr = INTERACT li1 met1VccMcon_spwr
met1VccDangle_spwr = INTERACT met1VccMultMcon_spwr met1VccLi_spwr == 1
contStackVcc_spwr = INTERACT (li1ConVccSPwr AND met1ConVccSPwr) (liAndMconVcc_spwr AND met1ConVccSPwr)
contStackVcc_check_spwr = INTERACT (li1ConVccSPwr AND met1ConVcc_checkSPwr) (liAndMconVcc_spwr AND met1ConVcc_checkSPwr)
floatContactStackVcc_spwr = (NOT INTERACT contStackVcc_spwr noLi1JumperM1) NOT contStackVcc_check_spwr
li1JumpVccAll_spwr = INTERACT (INTERACT li1 (NOT INTERACT floatcontactStackVcc_spwr met1VccDangle_spwr)) contStackVcc_check_spwr
li1JumpAll_spwr = COPY li1JumpVccAll_spwr
li1JumpVcc_spwr = floatContactStackVcc_spwr AND (INTERACT li1_noXmt li1JumpVccAll_spwr)
"s_0_res.1a" {
@ res.1a: li jumper connecting to switched_power text label
COPY li1JumpVcc_spwr
}
met1ConVss_check = NET met1 "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
met1ConVcc_check = NET met1 "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
liAndMconVss = li1ConVss AND mcon
liAndMconVcc = li1ConVcc AND mcon
met1VccConLi1NoVia = NOT INTERACT (INTERACT met1 floatContactStackVcc) via
met1VssConLi1NoVia = NOT INTERACT (INTERACT met1 floatContactStackVss) via
met1VssMultMcon = INTERACT met1VssConLi1NoVia liAndMconVss >= 1
met1VssMcon = met1VssMultMcon AND mcon
met1VssLi = INTERACT li1 met1VssMcon
met1VssDangle = INTERACT met1VssMultMcon met1VssLi == 1
met1VccMultMcon = INTERACT met1VccConLi1NoVia liAndMconVcc >= 1
met1VccMcon = met1VccMultMcon AND mcon
met1VccLi = INTERACT li1 met1VccMcon
met1VccDangle = INTERACT met1VccMultMcon met1VccLi == 1
contStackVss = INTERACT (li1ConVss AND met1ConVss) (liAndMconVss AND met1ConVss)
contStackVcc = INTERACT (li1ConVcc AND met1ConVcc) (liAndMconVcc AND met1ConVcc)
contStackVss_check = INTERACT (li1ConVss AND met1ConVss_check) (liAndMconVss AND met1ConVss_check)
contStackVcc_check = INTERACT (li1ConVcc AND met1ConVcc_check) (liAndMconVcc AND met1ConVcc_check)
floatContactStackVss = (NOT INTERACT contStackVss noLi1JumperM1) NOT contStackVss_check
floatContactStackVcc = (NOT INTERACT contStackVcc noLi1JumperM1) NOT contStackVcc_check
li1JumpVssAll = INTERACT (INTERACT li1 (NOT INTERACT floatContactStackVss met1VssDangle)) contStackVss_check
li1JumpVccAll = INTERACT (INTERACT li1 (NOT INTERACT floatcontactStackVcc met1VccDangle)) contStackVcc_check
li1JumpAll = li1JumpVssAll OR li1JumpVccAll
li1JumpVss = floatContactStackVss AND (INTERACT li1_noXmt li1JumpVssAll)
li1JumpVcc = floatContactStackVcc AND (INTERACT li1_noXmt li1JumpVccAll)
"r_200_X.25" {
@ X.25: li jumper connecting to VCC
COPY li1JumpVcc
}
"r_201_X.25" {
@ X.25: li jumper connecting to VSS
COPY li1JumpVss
}
sigPadDiffNSDcut = CUT NSRCDRN sigPadDiff
sigPadDiffPSDcut = CUT PSRCDRN sigPadDiff
sigPadDiffNTAPcut = CUT NTAP sigPadDiff
sigPadDiffPTAPcut = CUT PTAP sigPadDiff
sigPadWellNWcut = CUT nwell sigPadWell
sigPadMetNtrNSDcut = CUT NSRCDRN sigPadMetNtr
sigPadMetNtrPSDcut = CUT PSRCDRN sigPadMetNtr
sigPadMetNtrNTAPcut = CUT NTAP sigPadMetNtr
sigPadMetNtrPTAPcut = CUT PTAP sigPadMetNtr
sigPadMetNtrNWcut = CUT (nwell AND sigPadWell) sigPadMetNtr
IOnoSigPadNSD_err = (sealHole AND ioNSDnet) NOT NSDsigPad
IOnoSigPadPSD_err = (sealHole AND ioPSDnet) NOT PSDsigPad
IOnoSigPadNTAP_err = (sealHole AND ioNTAPnet) NOT NTAPsigPad
IOnoSigPadPTAP_err = (sealHole AND ioPTAPnet) NOT PTAPsigPad
IOnoSigPadNW_err = (sealHole AND lu4_ioNwellNet) NOT nwellSigPadNTR
"r_202_lu.12.1a" {
@ lu.12.1a: areaid.sigPadDiff cannot straddle NSRCDRN
COPY SigPadDiffNSDcut
}
"r_203_lu.12.1a" {
@ lu.12.1a: areaid.sigPadDiff cannot straddle PSRCDRN
COPY SigPadDiffPSDcut
}
"r_204_lu.12.1a" {
@ lu.12.1a: areaid.sigPadDiff cannot straddle NTAP
COPY SigPadDiffNTAPcut
}
"r_205_lu.12.1a" {
@ lu.12.1a: areaid.sigPadDiff cannot straddle PTAP
COPY SigPadDiffPTAPcut
}
"r_206_lu.12.1b" {
@ lu.12.1b: areaid.sigPadWell cannot straddle nwell
COPY SigPadWellNWcut
}
"r_207_lu.12.1c" {
@ lu.12.1c: areaid.sigPadMetNtr cannot straddle NSRCDRN
COPY SigPadMetNtrNSDcut
}
"r_208_lu.12.1c" {
@ lu.12.1c: areaid.sigPadMetNtr cannot straddle PSRCDRN
COPY SigPadMetNtrPSDcut
}
"r_209_lu.12.1c" {
@ lu.12.1c: areaid.sigPadMetNtr cannot straddle NTAP
COPY SigPadMetNtrNTAPcut
}
"r_210_lu.12.1c" {
@ lu.12.1c: areaid.sigPadMetNtr cannot straddle PTAP
COPY SigPadMetNtrPTAPcut
}
"r_211_lu.12.1c" {
@ lu.12.1c: areaid.sigPadMetNtr cannot straddle nwell inside areaid.sigPadWell
COPY SigPadMetNtrNWcut
}
"s_1_lu.12.2a" {
@ lu.12.2a: nsrcdrn connected to signal pad (ioNets) not inside areaid.sigPadDiff
COPY IOnoSigPadNSD_err
}
"s_2_lu.12.2a" {
@ lu.12.2a: psrcdrn connected to signal pad (ioNets) not inside areaid.sigPadDiff
COPY IOnoSigPadPSD_err
}
"s_3_lu.12.2a" {
@ lu.12.2a: n+tap connected to signal pad (ioNets) not inside areaid.sigPadDiff
COPY IOnoSigPadNTAP_err
}
"s_4_lu.12.2a" {
@ lu.12.2a: p+tap connected to signal pad (ioNets) not inside areaid.sigPadDiff
COPY IOnoSigPadPTAP_err
}
"s_5_lu.12.2b" {
@ lu.12.2b: nwell connected to signal pad (ioNets) not inside areaid.sigPadWell
COPY IOnoSigPadNW_err
}
Li1Met1 = li1 AND
(met1 AND mcon)
/// CALconnectZone started - zoneName was "zone_30"
DISCONNECT
CONNECT nwell NTAP
CONNECT Li1Met1 PTAP BY Licon1Pfom
CONNECT Li1Met1 NTAP BY Licon1Nfom
CONNECT Li1Met1 PSRCDRN BY Licon1Pfom
CONNECT Li1Met1 NSRCDRN BY Licon1Nfom
CONNECT Li1Met1 PolyNoRes BY Licon1ply
CONNECT PolyNoRes gate
CONNECT Met1 Li1Met1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT NSRCDRN shv_ndiff_esdRes
CONNECT PSRCDRN shv_pdiff_esdRes
CONNECT NSRCDRN shv_ndiff_res
CONNECT PSRCDRN shv_pdiff_res
CONNECT PolyNoRes shv_poly_esdRes
CONNECT PolyNoRes shv_poly_res
CONNECT Met1 Met1EsdRes_no1KOhm
CONNECT Met2 Met2EsdRes_no1KOhm
CONNECT Met3 Met3EsdRes_no1KOhm
CONNECT isolatedSubNoPWR shv_pwell_res
CONNECT Met4 Met4EsdRes_no1kOhm
CONNECT Met5 Met5EsdRes_no1KOhm
CONNECT paddg Met5
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl paddg BY pmm
CONNECT rdl pad BY pmm
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_31
nwellVss = NET nwell "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
dnwConnNW = STAMP dnwANDnwell by nwell
dnwVss = NET AREA RATIO (dnwConnNW AND dnwSHVsrcDrn) nwellVss > 0
ioShvNwell = INTERACT nwell shvNTAPio
vccIsoPW = INTERACT isoPwell vccPTAP
shvIsoPW = INTERACT isoPwell shvPTAP
lu13_vssNSD = INTERACT (NET NSRCDRN "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio") (INTERACT met1 (met1 AND
(li1 AND mcon)))
lu13_ptapConMet = PTAP AND (INTERACT met1 (met1 AND
(li1 AND mcon)))
CONNECT lu13_ptapConMet PTAP
CONNECT substrateLocal lu13_ptapConMet
vssNSDlocalPtap = lu13_vssNSD AND (NSRCDRN AND substrateLocal CONNECTED)
vssNSDnoLocPtap = lu13_vssNSD NOT vssNSDlocalPtap
shvClamps = EXTENT CELL "s8defet_s8esd20clamp_7200um_IEC_noRpoly_M5_stress_free_A" "s8defet_s8esd20clamp_2400um_HBM_32V_noRpoly_M3_stress_free_A" "s8defet_s8esd20clamp_2400um_HBM_32V_noRpoly_M3_stress_free_B" "s8defet_s8esd20clamp_1200um_HBM_32V_noRpoly_M3_stress_free_A" "s8defet_s8esd20clamp_1200um_HBM_21V_noRpoly_M3_stress_free" "s8defet_s8esd20clamp_2400um_HBM_21V_noRpoly_M3_stress_free_A" "s8defet_s8esd20clamp_2400um_HBM_21V_noRpoly_M3_stress_free_B" "s8defet_ndiode_dnwpw_3p0_nw_0p05_W20um_CDM" ORIGINAL
"r_212_lu.13.1" {
@ lu.13.1: Grounded deep nwell is not allowed
COPY dnwVss
}
"r_213_lu.13.2" {
@ lu.13.2: 70 min. spacing of ioShvNwell & vcc p-src/drn
EXTERNAL ioShvNwell vccPSD < 70.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_214_lu.13.2" {
@ lu.13.2: 70 min. spacing of ioShvNwell & vccPTAP
EXTERNAL ioShvNwell vccPTAP < 70.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_215_lu.13.2" {
@ lu.13.2: 70 min. spacing of ioShvNwell & vccIsoPW
EXTERNAL ioShvNwell vccIsoPW < 70.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_216_lu.13.3a" {
@ lu.13.3a: 100 min. spacing of shvIsoPw & vssNSDlocalPtap
EXTERNAL shvIsoPw vssNSDlocalPtap < 100.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_217_lu.13.3b" {
@ lu.13.3b: 150 min. spacing of shvIsoPw & vssNSDnolocPtap
EXTERNAL shvIsoPw vssNSDnolocPtap < 150.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_218_lu.13.4" {
@ lu.13.4: 70 min. spacing of shvClamps & io p-src/drn
EXTERNAL shvClamps ioPSD < 70.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_219_lu.13.4" {
@ lu.13.4: 70 min. spacing of shvClamps & io n-src/drn
EXTERNAL shvClamps ioNSD < 70.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_220_lu.13.4" {
@ lu.13.4: 70 min. spacing of shvClamps & io ntap
EXTERNAL shvClamps ioNTAP < 70.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_221_lu.13.4" {
@ lu.13.4: 70 min. spacing of shvClamps & io ptap
EXTERNAL shvClamps ioPTAP < 70.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
ioPWall = INTERACT isoPwell ioPTAP
lu4_12o_xmt = EXTENT CELL "atlas_top" "fpg1_top" "ccg2_top" "ccg4_top" "s8sarmux_top" "s8usbfsm0s8_top" "psoc4a_top" "psoc4al_top" "psoc4ads2_top" "psoc4able_top" "psoc4able256_top" "psoc4able256dma_top" ORIGINAL
lu4_12p_xmt = EXTENT CELL "s8fpafeg1_top" "s8fpafeg1_io_rx_2x1" "s8tnvra_psoc3_osc32a_p3" "m0s8gen4_top" ORIGINAL
ioPSDnetChk = ioPSDnet NOT lu4_12o_xmt
ioPW = ioPWall NOT lu4_12p_xmt
"r_222_lu.4.12o" {
@ lu.4.12o: 27 min. spacing of ioPSDnetChk & lvvccNwell
EXTERNAL ioPSDnetChk lvvccNwell < 27.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_223_lu.4.12p" {
@ lu.4.12p: 40 min. spacing of ioPW & lvvccNwell
EXTERNAL ioPW lvvccNwell < 40.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
PTAPvictim = (WITH TEXT PTAP "victim" textlabel) OR (WITH TEXT PTAP "vic" textlabel)
PTAPaggressor = (WITH TEXT PTAP "aggressor" textlabel) OR (WITH TEXT PTAP "agr" textlabel)
PTAPringVictim = PTAPvictim AND PTAPnotSealDonut
PTAPringAggressor = PTAPaggressor AND PTAPnotSealDonut
allVicAgrPTAPrings = PTAPringVictim OR PTAPringAggressor
victimRegionTmp1 = HOLES PTAPringVictim
aggressorRegionTmp1 = HOLES PTAPringAggressor
victimRegion = (INTERACT PTAPringVictim victimRegionTmp1) OR victimRegionTmp1
aggressorRegion = (INTERACT PTAPringAggressor aggressorRegionTmp1) OR aggressorRegionTmp1
PsubTapNeitherRegion = PTAP NOT (dnwell OR
(allVicAgrPTAPrings OR
(victimRegion OR aggressorRegion)))
PsubTapVictimRegion = (PTAP AND victimRegion) NOT dnwell
PsubTapAggressorRegion = (PTAP AND aggressorRegion) NOT dnwell
mcon_ring = allVicAgrPTAPrings AND mcon
licon1_ring = allVicAgrPTAPrings AND licon1
PTAP_NotDnwell = PTAP NOT dnwell
/// CALconnectZone started - zoneName was "zone_31"
DISCONNECT
CONNECT nwell NTAP
CONNECT nwell ntapPsrcdrnMetConn
CONNECT ESDnWellTap NSRCDRN
CONNECT PTAP inner_ptap_DGR
CONNECT NTAP second_ntap_DGR
CONNECT NTAP inner_ntap_DGR
CONNECT PTAP second_ptap_DGR
CONNECT PTAP PTAPnotSealDonut
CONNECT NTAP NTAPnotSealDonut
CONNECT NTAP ntap_SGR
CONNECT PTAP ptap_SGR
CONNECT Li1 PTAP BY Licon1Pfom
CONNECT Li1 NTAP BY Licon1Nfom
CONNECT Li1 nonPnpNTap BY Licon1Nfom
CONNECT Li1 nonPnpPTap BY Licon1Pfom
CONNECT Li1 PSRCDRN BY Licon1Pfom
CONNECT Li1 NSRCDRN BY Licon1Nfom
CONNECT isolatedSubNoPWR PTAP BY isoSubPTap
CONNECT Li1 PolyNoRes BY Licon1ply
CONNECT Li1 ESDnWellTap BY Licon1Nfom
CONNECT PolyNoRes gate
CONNECT Met1 Li1 BY Mcon
CONNECT Met2 Met1 BY Via
CONNECT Met3 Met2 BY Via2
CONNECT switched_intPower_met1 Met1
CONNECT Met4 Met3 BY Via3
CONNECT Met5 Met4 BY Via4
CONNECT pad Met5
CONNECT rdl pad BY pmm
CONNECT victimRegion PTAP_NotDnwell
CONNECT aggressorRegion PTAP_NotDnwell
CONNECT PTAP PTAP_NotDnwell
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_32
vicRegionRings = PTAPnotSealDonut AND victimRegion
agrRegionRings = PTAPnotSealDonut AND aggressorRegion
PTAPvicRingWithVsubNet = NET PTAP_NotDnwell "vsub_vic_?"
PTAPagrRingWithVsubNet = NET PTAP_NotDnwell "vsub_agr_?"
vicRegionRingsWithoutVsub = (vicRegionRings NOT PTAPvicRingWithVsubNet) NOT dnwell
agrRegionRingsWithoutVsub = (agrRegionRings NOT PTAPagrRingWithVsubNet) NOT dnwell
"r_224_subiso.2" {
@ subiso.2: Tap substrate ring used for aggressor isolation must connect to a net starting with vsub_agr_
COPY agrRegionRingsWithoutVsub
}
"r_225_subiso.3" {
@ subiso.3: Tap substrate ring used for victim isolation must connect to a net starting with vsub_vic_
COPY vicRegionRingsWithoutVsub
}
PTAPvicOutsideRegion = PTAPvictim NOT victimRegion
PTAPagrOutsideRegion = PTAPaggressor NOT aggressorRegion
"r_226_subiso.4" {
@ subiso.4: Victim tagged PTAP found outside of victim region
COPY PTAPvicOutsideRegion
}
"r_227_subiso.4" {
@ subiso.4: Aggressor tagged PTAP found outside of victim region
COPY PTAPagrOutsideRegion
}
badVictimRing = PTAPringVictim AND PTAPringAggressor
"r_228_subiso.5" {
@ subiso.5: victim and aggressor label both present on same tap ring
COPY badVictimRing
}
VicAgrRingsInIsoPsub = allVicAgrPTAPrings AND isoPwell
"r_229_subiso.6" {
@ subiso.6: victim/aggressor rings cannot be in iso pwell
COPY VicAgrRingsInIsoPsub
}
"r_230_subiso.7" {
@ subiso.7: 0.01 min. enclosure of allVicAgrPTAPrings by localSub
q0allVicAgrPTAPringsand = allVicAgrPTAPrings AND localSub
ENCLOSURE q0allVicAgrPTAPringsand localSub < 0.01 MEASURE ALL ABUT < 90 SINGULAR
}
"r_231_subiso.7" {
@ subiso.7: allVicAgrPTAPrings must be enclosed by localSub
allVicAgrPTAPrings NOT localSub
}
"r_232_subiso.8" {
@ subiso.8: 50 min. spacing of victimRegion & aggressorRegion
EXTERNAL victimRegion aggressorRegion < 50.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
"r_233_subiso.8" {
@ subiso.8: victimRegion must not overlap aggressorRegion
victimRegion AND aggressorRegion
}
vicAgrHoles = (HOLES PTAPringVictim) OR (HOLES PTAPringAggressor)
exteriorVicAgrRingEdges = allVicAgrPTAPrings NOT COINCIDENT EDGE vicAgrHoles
expandedCheckRegion = EXPAND EDGE exteriorVicAgrRingEdges INSIDE BY 10 CORNER FILL
badSubiso9PTAP = expandedCheckRegion NOT allVicAgrPTAPrings
"r_234_subiso.9" {
@ subiso.9: expected victim/aggressor substrate tap not present to meet minimum tap ring width of 10.000000
COPY badSubiso9PTAP
}
allVicAgrPTAPrings_licon1 = COPY allVicAgrPTAPrings
allVicAgrPTAPrings_mcon = COPY allVicAgrPTAPrings
q1licon1_ring = licon1_ring AND allVicAgrPTAPrings_licon1
q0licon1_ring = SIZE q1licon1_ring BY 0.425 INSIDE OF allVicAgrPTAPrings_licon1 STEP 0.19
"k_46_q0licon1_ring" {
@ keep: q0licon1_ring - q0licon1_ring
@ Guard ring checked for subiso.10/11 (must be a continuous DONUT)
COPY q0licon1_ring
}
q1allVicAgrPTAPrings_licon1 = NOT DONUT q0licon1_ring
"r_235_subiso.10/11" {
@ subiso.10/11: Guard ring allVicAgrPTAPrings_licon1 must be fully contacted with 0.85 max contact space
@ See the keep layer database for the full guard ring being checked
q2allVicAgrPTAPrings_licon1 = COPY q1allVicAgrPTAPrings_licon1
COPY q2allVicAgrPTAPrings_licon1
}
q1mcon_ring = mcon_ring AND allVicAgrPTAPrings_mcon
q0mcon_ring = SIZE q1mcon_ring BY 0.475 INSIDE OF allVicAgrPTAPrings_mcon STEP 0.19
"k_47_q0mcon_ring" {
@ keep: q0mcon_ring - q0mcon_ring
@ Guard ring checked for subiso.10/11 (must be a continuous DONUT)
COPY q0mcon_ring
}
q1allVicAgrPTAPrings_mcon = NOT DONUT q0mcon_ring
"r_236_subiso.10/11" {
@ subiso.10/11: Guard ring allVicAgrPTAPrings_mcon must be fully contacted with 0.95 max contact space
@ See the keep layer database for the full guard ring being checked
q2allVicAgrPTAPrings_mcon = COPY q1allVicAgrPTAPrings_mcon
COPY q2allVicAgrPTAPrings_mcon
}
PTAPnotRingWithVicAgrTag = (PTAPvictim OR PTAPaggressor) NOT allVicAgrPTAPrings
"r_237_subiso.12" {
@ subiso.12: Non-ring p-tap with victim or aggressor tag
COPY PTAPnotRingWithVicAgrTag
}
invalidVicAgrLocalSub = HOLES (localSub AND (victimRegion OR aggressorRegion))
"r_238_subiso.13" {
@ subiso.13: areaid.substrateCut inside victim/aggressor regions cannot have holes
COPY invalidVicAgrLocalSub
}
expandedSubIsoTextLabels = (EXPAND TEXT "victim" textlabel BY 0.01) OR
((EXPAND TEXT "vic" textlabel BY 0.01) OR
((EXPAND TEXT "aggressor" textlabel BY 0.01) OR (EXPAND TEXT "agr" textlabel BY 0.01)))
badSubIsoTextLabels = NOT INTERACT expandedSubIsoTextLabels PTAP
"r_239_subiso.14" {
@ subiso.14: victim/vic/aggressor/agr labels must only be on p-tap
COPY badSubIsoTextLabels
}
/// CALconnectZone started - zoneName was "zone_32"
CONNECT NSRCDRN lu4_ndiff_esdRes
CONNECT PSRCDRN lu4_pdiff_esdRes
CONNECT NSRCDRN lu4_ndiff_res
CONNECT PSRCDRN lu4_pdiff_res
CONNECT PolyNoRes lu4_poly_esdRes
CONNECT PolyNoRes lu4_poly_res
CONNECT Met1 Met1EsdRes_no100KOhm
CONNECT Met2 Met2EsdRes_no100KOhm
CONNECT Met3 Met3EsdRes_no100KOhm
CONNECT isolatedSubNoPWR lu4_pwell_res
CONNECT Met4 Met4EsdRes_no100KOhm
CONNECT Met5 Met5EsdRes_no100KOhm
CONNECT PsubTapNeitherRegion PTAP
CONNECT PsubTapVictimRegion PTAP
CONNECT PsubTapAggressorRegion PTAP
CONNECT poly_pin PolyNoRes
TEXT LAYER polypt ATTACH polypt poly_pin
CONNECT li1_pin Li1
TEXT LAYER Li1pt ATTACH Li1pt li1_pin
CONNECT met1_pin Met1
TEXT LAYER Met1pt ATTACH Met1pt met1_pin
CONNECT met2_pin Met2
TEXT LAYER Met2pt ATTACH Met2pt met2_pin
CONNECT met3_pin Met3
TEXT LAYER Met3pt ATTACH Met3pt met3_pin
CONNECT met4_pin Met4
TEXT LAYER Met4pt ATTACH Met4pt met4_pin
CONNECT met5_pin Met5
TEXT LAYER Met5pt ATTACH Met5pt met5_pin
CONNECT rdl_pin rdl
TEXT LAYER Rdlpt ATTACH Rdlpt rdl_pin
TEXT LAYER met3tt ATTACH met3tt Met3
TEXT LAYER met2tt ATTACH met2tt Met2
TEXT LAYER met1tt ATTACH met1tt Met1
TEXT LAYER li1tt ATTACH li1tt Li1
TEXT LAYER polytt ATTACH polytt PolyNoRes
TEXT LAYER difftt ATTACH difftt NSRCDRN
TEXT LAYER difftt ATTACH difftt PSRCDRN
TEXT LAYER met4tt ATTACH met4tt Met4
TEXT LAYER met5tt ATTACH met5tt Met5
TEXT LAYER rdltt ATTACH rdltt rdl
/// CALconnectZone done. zoneName is now zone_33
victimConnectedToNeither = NET AREA RATIO PsubTapVictimRegion PsubTapNeitherRegion > 0
victimConnectedToAggressor = NET AREA RATIO PsubTapVictimRegion PsubTapAggressorRegion > 0
victimConnectedToNonVictim = victimConnectedToNeither OR victimConnectedToAggressor
aggressorConnectedToNeither = NET AREA RATIO PsubTapAggressorRegion PsubTapNeitherRegion > 0
aggressorConnectedToVictim = NET AREA RATIO PsubTapAggressorRegion PsubTapVictimRegion > 0
aggressorConnectedToNonAggressor = aggressorConnectedToNeither OR aggressorConnectedToVictim
"r_240_subiso.15" {
@ subiso.15: victim substrate ptap connected to ptap in a non-victim region
COPY victimConnectedToNonVictim
}
"r_241_subiso.16" {
@ subiso.16: aggressor substrate ptap connected to a ptap in a non-aggressor region
COPY aggressorConnectedToNonAggressor
}
/// THIS IS CALIBRE ANTENNA CHECK
DISCONNECT
Ant_short = (tap NOT poly) NOT nwell
SRCDRNTAP = diffTap NOT poly
Ant_diode = SRCDRNTAP NOT Ant_short
Gate_ant = poly AND diffTap
CONNECT poly Gate_ant
ar_poly = NET AREA RATIO poly Gate_ant > 50 [PERIMETER(poly) * 0.180000 / AREA(Gate_ant)] RDB ar_poly.db poly Gate_ant BY LAYER
"r_242_ar.poly.1" {
@ ar_q.poly.1: 50 ratio poly antenna check, see ar_poly.db for ratio value
INTERACT Gate_ant ar_poly
}
CONNECT poly Licon1
ar_licon1 = NET AREA RATIO Licon1 Gate_ant > 3 RDB ar_licon1.db Licon1 Gate_ant BY LAYER
"r_243_ar.licon.1" {
@ ar_q.licon.1: 3 ratio licon1 antenna check, see ar_licon1.db for ratio value
INTERACT Gate_ant (INTERACT poly ar_licon1)
}
CONNECT Li1 poly BY Licon1
CONNECT Li1 SRCDRNTAP BY Licon1
CONNECT Li1 Ant_diode BY Licon1
CONNECT Li1 Ant_short BY Licon1
fgate_1 = NET AREA RATIO Gate_ant Ant_short == 0
ar_Li1 = NET AREA RATIO fgate_1 Li1 Ant_diode > 0.0 [(((PERIMETER(Li1) * 0.100000 / AREA(fgate_1))-75)/450)-(AREA(Ant_diode)*!!AREA(fgate_1))] RDB ar_Li1.db fgate_1 Li1 Ant_diode BY LAYER
"r_244_ar_Li1.1" {
@ ar_q.li.1: 75 ratio li1 antenna check, see ar_Li1.db for diode area required to fix
COPY ar_Li1
}
CONNECT Li1 Mcon
fgate_2 = NET AREA RATIO Gate_ant Ant_short == 0
ar_mcon = NET AREA RATIO fgate_2 mcon ANT_diode > 0.0 [(((AREA(mcon)/AREA(fgate_2))-3)/18)-(AREA(Ant_diode)*!!AREA(fgate_2))] RDB ar_mcon.db fgate_2 mcon ANT_diode BY LAYER
"r_245_ar.mcon.1" {
@ ar_q.mcon.1: 3 ratio Mcon antenna check, see ar_mcon.db for diode area required to fix
COPY ar_mcon
}
CONNECT Met1 Li1 BY mcon
fgate_3 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met1 = NET AREA RATIO fgate_3 Met1 Ant_diode > 0.0 [((((PERIMETER(Met1) * 0.350000 / AREA(fgate_3))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_3))] RDB ar_met1.db fgate_3 Met1 Ant_diode BY LAYER
"r_246_ar.met1.1" {
@ ar_q.met1.1: 400 ratio Met1 antenna check, see ar_met1.db for diode area required to fix
COPY ar_met1
}
CONNECT Met1 Via
fgate_4 = NET AREA RATIO Gate_ant Ant_short == 0
ar_via = NET AREA RATIO fgate_4 Via ANT_diode > 0.0 [(((AREA(Via)/AREA(fgate_4))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_4))] RDB ar_via.db fgate_4 Via ANT_diode BY LAYER
"r_247_ar.via.1" {
@ ar_q.via.1: 6 ratio Via antenna check, see ar_via.db for diode area required to fix
COPY ar_via
}
CONNECT Met2 Met1 BY Via
fgate_5 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met2 = NET AREA RATIO fgate_5 Met2 Ant_diode > 0.0 [((((PERIMETER(Met2) * 0.350000 / AREA(fgate_5))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_5))] RDB ar_met2.db fgate_5 Met2 Ant_diode BY LAYER
"r_248_ar.met2.1" {
@ ar_q.met2.1: 400 ratio Met2 antenna check, see ar_met2.db for diode area required to fix
COPY ar_met2
}
CONNECT Met2 Via2
fgate_6 = NET AREA RATIO Gate_ant Ant_short == 0
ar_via2 = NET AREA RATIO fgate_6 Via2 ANT_diode > 0.0 [(((AREA(Via2)/AREA(fgate_6))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_6))] RDB ar_via2.db fgate_6 Via2 ANT_diode BY LAYER
"r_249_ar.via2.1" {
@ ar_q.via2_q.1: 6 ratio Via2 antenna check, see ar_via2.db for diode area required to fix
COPY ar_via2
}
CONNECT Met3 Met2 BY Via2
fgate_7 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met3 = NET AREA RATIO fgate_7 Met3 Ant_diode > 0.0 [((((PERIMETER(Met3) * 0.800000 /AREA(fgate_7))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_7))] RDB ar_met3.db fgate_7 Met3 Ant_diode BY LAYER
"r_250_ar.met3.1" {
@ ar_q.met3_q.1: 400 ratio Met3 antenna check, see ar_met3.db for diode area required to fix
COPY ar_met3
}
CONNECT Met3 Via3
fgate_8 = NET AREA RATIO Gate_ant Ant_short == 0
ar_via3 = NET AREA RATIO fgate_8 Via3 ANT_diode > 0.0 [(((AREA(Via3)/AREA(fgate_8))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_8))] RDB ar_via3.db fgate_8 Via3 ANT_diode BY LAYER
"r_251_ar.via3.1" {
@ ar_q.via3_q.1: 6 ratio Via3 antenna check, see ar_via3.db for diode area required to fix
COPY ar_via3
}
CONNECT Met4 Met3 BY Via3
fgate_9 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met4 = NET AREA RATIO fgate_9 Met4 Ant_diode > 0.0 [((((PERIMETER(Met4) * 0.800000 /AREA(fgate_9))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_9))] RDB ar_met4.db fgate_9 Met4 Ant_diode BY LAYER
"r_252_ar.met4.1" {
@ ar_q.met4_q.1: 400 ratio Met4 antenna check, see ar_met4.db for diode area required to fix
COPY ar_met4
}
CONNECT Met4 Via4
fgate_10 = NET AREA RATIO Gate_ant Ant_short == 0
ar_via4 = NET AREA RATIO fgate_10 Via4 ANT_diode > 0.0 [(((AREA(Via4)/AREA(fgate_10))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_10))] RDB ar_via4.db fgate_10 Via4 ANT_diode BY LAYER
"r_253_ar.via4.1" {
@ ar_q.via4_q.1: 6 ratio Via4 antenna check, see ar_via4.db for diode area required to fix
COPY ar_via4
}
CONNECT Met5 Met4 BY Via4
fgate_11 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met5 = NET AREA RATIO fgate_11 Met5 Ant_diode > 0.0 [((((PERIMETER(Met5) * 1.200000 /AREA(fgate_11))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_11))] RDB ar_met5.db fgate_11 Met5 Ant_diode BY LAYER
"r_254_ar.met5.1" {
@ ar_q.met5_q.1: 400 ratio Met5 antenna check, see ar_met5.db for diode area required to fix
COPY ar_met5
}
GROUP drcErrors "r_254_ar.met5.1" "r_253_ar.via4.1" "r_252_ar.met4.1" "r_251_ar.via3.1"
"r_250_ar.met3.1" "r_249_ar.via2.1" "r_248_ar.met2.1" "r_247_ar.via.1" "r_246_ar.met1.1"
"r_245_ar.mcon.1" "r_244_ar_Li1.1" "r_243_ar.licon.1" "r_242_ar.poly.1" "r_241_subiso.16"
"r_240_subiso.15" "r_239_subiso.14" "r_238_subiso.13" "r_237_subiso.12" "r_236_subiso.10/11"
"r_235_subiso.10/11" "r_234_subiso.9" "r_233_subiso.8" "r_232_subiso.8" "r_231_subiso.7"
"r_230_subiso.7" "r_229_subiso.6" "r_228_subiso.5" "r_227_subiso.4" "r_226_subiso.4"
"r_225_subiso.3" "r_224_subiso.2" "r_223_lu.4.12p" "r_222_lu.4.12o" "r_221_lu.13.4"
"r_220_lu.13.4" "r_219_lu.13.4" "r_218_lu.13.4" "r_217_lu.13.3b" "r_216_lu.13.3a"
"r_215_lu.13.2" "r_214_lu.13.2" "r_213_lu.13.2" "r_212_lu.13.1" "r_211_lu.12.1c"
"r_210_lu.12.1c" "r_209_lu.12.1c" "r_208_lu.12.1c" "r_207_lu.12.1c" "r_206_lu.12.1b"
"r_205_lu.12.1a" "r_204_lu.12.1a" "r_203_lu.12.1a" "r_202_lu.12.1a" "r_201_X.25"
"r_200_X.25" "r_199_lu.4.14" "r_198_lu.4.13" "r_197_lu.4.9" "r_196_lu.4.9"
"r_195_lu.4.7/8.ntap" "r_194_lu.4.7/8.ptap" "r_193_lu.4.6.1" "r_192_lu.4.6.1" "r_191_lu.4.6.1"
"r_190_lu.4.6.1" "r_189_lu.4.6.1" "r_188_lu.4.6.1" "r_187_lu.4.6.1" "r_186_lu.4.6.1"
"r_185_lu.4.6" "r_184_lu.4.6" "r_183_lu.4.6" "r_182_lu.4.6" "r_181_lu.4.6"
"r_180_lu.4.6" "r_179_lu.4.6" "r_178_lu.4.6" "r_177_lu.4.4" "r_176_lu.4.4"
"r_175_lu.4.4" "r_174_lu.4.4" "r_173_lu.4.4" "r_172_lu.4.4" "r_171_lu.4.4"
"r_170_lu.4.4" "r_169_lu.4.2.1a" "r_168_lu.4.2.1" "r_167_lu.4.2.1" "r_166_lu.4.2.1"
"r_165_lu.4.2.1" "r_164_lu.4.2.1" "r_163_lu.4.2.1" "r_162_lu.4.2.1" "r_161_lu.4.2.1"
"r_160_lu.4.2.1" "r_159_lu.4.2.1" "r_158_lu.4.3.1" "r_157_lu.4.3.1" "r_156_lu.4.3.1"
"r_155_lu.4.3.1" "r_154_lu.4.3.1" "r_153_lu.4.3" "r_152_lu.4.3" "r_151_lu.4.2"
"r_150_lu.4.2" "r_149_lu.4.2" "r_148_lu.4.12n" "r_147_lu.4.12m" "r_146_lu.4.12n"
"r_145_lu.4.12m" "r_144_lu.4.12n" "r_143_lu.4.12m" "r_142_lu.4.12n" "r_141_lu.4.12m"
"r_140_lu.4.12n" "r_139_lu.4.12m" "r_138_lu.4.12n" "r_137_lu.4.12m" "r_136_lu.4.12n"
"r_135_lu.4.12m" "r_134_lu.4.12n" "r_133_lu.4.12m" "r_132_lu.5.2" "r_131_lu.5.2"
"r_130_lu.5.2" "r_129_lu.5.2" "r_128_lu.5.2" "r_127_lu.5.2" "r_126_lu.5.2"
"r_125_lu.5.6" "r_124_lu.5.6" "r_123_lu.5.6" "r_122_lu.5.6" "r_121_lu.5.1b"
"r_120_lu.5.1a" "r_119_lu.5.1a/b" "r_118_lu.5.1a/b" "r_117_lu.5.1a/b" "r_116_lu.5.1a/b"
"r_115_lu.5.6" "r_114_lu.5.1a/b" "r_113_lu.11.3" "r_112_lu.4.2.1b" "r_111_lu.4.1.1h"
"r_110_lu.4.1.1h" "r_109_lu.4.1.1g" "r_108_lu.4.1.1g/c/e" "r_107_lu.4.1.1g" "r_106_lu.4.1.1g/c/e"
"r_105_lu.4.1.1g" "r_104_lu.4.1.1b" "r_103_lu.4.1.1b" "r_102_lu.4.1.1b" "r_101_lu.4.1.1a/c/e"
"r_100_lu.4.1.1a/c/e" "r_99_lu.4.1.1a" "r_98_lu.4.1.1a/c/e" "r_97_lu.4.1.1a" "r_96_lu.4.12k"
"r_95_lu.4.12b" "r_94_lu.4.12l" "r_93_lu.4.12k" "r_92_lu.4.12j" "r_91_lu.4.12i"
"r_90_lu.4.12h" "r_89_lu.4.12g" "r_88_lu.4.12f" "r_87_lu.4.12e" "r_86_lu.4.12d"
"r_85_lu.4.12c" "r_84_lu.4.12b" "r_83_lu.4.12a" "r_82_lu.4.12a" "r_81_lu.4.12a"
"r_80_lu.11.4" "r_79_lu.11.4" "r_78_lu1.5" "r_77_lu1.5" "r_76_lu1.5"
"r_75_lu1.5" "r_74_lu1.5" "r_73_lu1.5" "r_72_lu1.5" "r_71_lu1.5"
"r_70_lu1.5" "r_69_lu1.5" "r_68_lu1.5" "r_67_lu1.5" "r_66_lu1.5"
"r_65_lu1.5" "r_64_lu1.5" "r_63_lu1.5" "r_62_lu1.5" "r_61_lu1.5"
"r_60_lu1.5" "r_59_lu1.5" "r_58_lu1.5" "r_57_lu1.5" "r_56_lu1.5"
"r_55_lu1.5" "r_54_lu1.5" "r_53_lu1.5" "r_52_lu1.5" "r_51_lu1.5"
"r_50_lu1.5" "r_49_lu1.5" "r_48_lu1.5" "r_47_lu1.5" "r_46_lu1.5"
"r_45_lu1.5" "r_44_lu1.5" "r_43_lu1.5" "r_42_lu1.5" "r_41_lu1.5"
"r_40_lu1.5" "r_39_lu1.5" "r_38_lu1.5" "r_37_lu1.5" "r_36_lu1.5"
"r_35_lu1.5" "r_34_lu1.5" "r_33_lu1.5" "r_32_lu1.5" "r_31_lu1.5"
"r_30_lu1.5" "r_29_lu1.5" "r_28_lu1.5" "r_27_lu1.4" "r_26_lu1.4"
"r_25_lu1.3.3b" "r_24_lu1.3.3a" "r_23_lu1.3.2b" "r_22_lu1.3.2a" "r_21_lu1.3.1b"
"r_20_lu1.3.1a" "r_19_lu1.3.3b" "r_18_lu1.3.3a" "r_17_lu1.3.2b" "r_16_lu1.3.2a"
"r_15_lu1.3.1b" "r_14_lu1.3.1a" "r_13_lu1.2.3b" "r_12_lu1.2.3a" "r_11_lu1.2.2b"
"r_10_lu1.2.2a" "r_9_lu1.2.1b" "r_8_lu1.2.1a" "r_7_lu1.2.3b" "r_6_lu1.2.3a"
"r_5_lu1.2.2b" "r_4_lu1.2.2a" "r_3_lu1.2.1b" "r_2_lu1.2.1a" "r_1_lu.5.7b"
"r_0_lu.5.7a"
GROUP keepLayers "k_47_q0mcon_ring" "k_46_q0licon1_ring" "k_45_poly_resNoEsd" "k_44_esdIpRes_blocks_res"
"k_43_ioPsrcDrnShrtRes" "k_42_ioNsrcDrnShrtRes" "k_41_reg_s8tee_reg_top_met2" "k_40_reg_mtdr_io_reg_mockup_met2" "k_39_q0lu5_2_nonPnpNTapLicon1"
"k_38_q0lu5_2_nonPnpPTapLicon1" "k_37_q0lu5_1_secondNLicon1" "k_36_q0lu5_1_innerPLicon1" "k_35_bad_pDiffVcc_and_nWellNonVcc_3p3V" "k_34_bad_pDiffVcc_and_nWellNonVcc_Norm"
"k_33_LU5_AtRiskNonVccNwellNonExempt" "k_32_LU5_ExemptARNonVccNwell_2" "k_31_LU5_ExemptARNonVccNwell_4" "k_30_LU5_ExemptARNonVccNwell_3" "k_29_LU5_ioNSDOrNwellSz"
"k_28_LU5_ExemptARNonVccNwell_1" "k_27_LU5_nonExemptARNonVccNwell" "k_26_LU5_nonExemptPdiff" "k_25_LU5_pDiffVccOrIo_conn_nwellNonVcc" "k_24_third_ntap_TGR"
"k_23_PsecondToThirdReg_TGR" "k_22_PinnerToSecondReg_TGR" "k_21_inner_hole_ntap_TGR" "k_20_second_ptap_TGR" "k_19_inner_ntap_TGR"
"k_18_third_ptap_TGR" "k_17_NsecondToThirdReg_TGR" "k_16_NinnerToSecondReg_TGR" "k_15_inner_hole_ptap_TGR" "k_14_second_ntap_TGR"
"k_13_inner_ptap_TGR" "k_12_second_ptap_DGR" "k_11_NinnerToSecondReg_DGR" "k_10_inner_hole_ntap_DGR" "k_9_inner_ntap_DGR"
"k_8_second_ntap_DGR" "k_7_PinnerToSecondReg_DGR" "k_6_inner_hole_ptap_DGR" "k_5_inner_ptap_DGR" "k_4_hole_ntap_SGR"
"k_3_ntap_SGR" "k_2_hole_ptap_SGR" "k_1_ptap_SGR" "k_0_s8_esd_xmt"
GROUP drcRecommended "s_5_lu.12.2b" "s_4_lu.12.2a" "s_3_lu.12.2a" "s_2_lu.12.2a"
"s_1_lu.12.2a" "s_0_res.1a"
/// To remove this when there are no rules checked,
/// pass ?dontCheckUnregisteredRules t to (CALdone)
GROUP unRegisteredErrors "?"
/// To remove this when there are no rules checked,
/// pass ?dontCheckUnregisteredRules t to (CALdone)
DRC SELECT CHECK unRegisteredErrors
DRC SELECT CHECK drcErrors
DRC SELECT CHECK keepLayers
DRC CHECK MAP keepLayers
ASCII "keepLayer.db"
MAXIMUM RESULTS ALL
DRC SELECT CHECK drcRecommended
DRC CHECK MAP drcRecommended
ASCII "drcRecommended.db"
MAXIMUM RESULTS 20000
/// --BEGIN LATCHUP RCX TABLE--
/// vpwr
/// vpwr1
/// vpwr3
/// vpwr_prb
/// vccio
/// vgnd
/// vgnd1
/// vgnd3
/// vgnd_prb
/// vgnd_pad
/// vssio
/// --END LATCHUP RCX TABLE--