| // $Id$ |
| // $Source$ |
| // |
| // Author: Sam Vuntangboon (vun) |
| // Copyright (c) 2018 SkyWater Technology. |
| // |
| // DESCRIPTION |
| /// $Id: extLvsRules_s8_5lm |
| // |
| // Revision History |
| /// Edits April 26, 2018 |
| /// Combined lvsRuls and extLvsRules file |
| /// PEX switch added; in control file: #DEFINE PEX / #UNDEFINE PEX |
| /// MOS parameters implements with MACROs |
| /// All scale factors removed |
| // vun 02/14/20 major update to V2.0.0 |
| |
| /// Tolerance for round-off errors on skew edges |
| DRC TOLERANCE FACTOR 0.001 |
| |
| // Use these to convert lengths to microns, areas to microns^2 |
| |
| VARIABLE L_scale 1e6 |
| VARIABLE L_scale2 1e12 |
| VARIABLE L_square 1e12 |
| |
| /// Begin layer definitions |
| |
| // ;ss added pmm, ubm, bump |
| // note, ubm not actually used |
| |
| LAYER nwell 1000 |
| LAYER MAP 64 DATATYPE 20 1000 // nwell drawing |
| |
| LAYER tunm 1001 |
| LAYER MAP 80 DATATYPE 20 1001 // tunm drawing |
| |
| LAYER diff 1002 |
| LAYER MAP 65 DATATYPE 20 1002 // diff drawing |
| |
| LAYER tap 1003 |
| LAYER MAP 65 DATATYPE 44 1003 // tap drawing |
| |
| LAYER poly 1004 |
| LAYER MAP 66 DATATYPE 20 1004 // poly drawing |
| |
| LAYER lvtn 1005 |
| LAYER MAP 125 DATATYPE 44 1005 // lvtn drawing |
| |
| LAYER hvtp 1006 |
| LAYER MAP 78 DATATYPE 44 1006 // hvtp drawing |
| |
| LAYER npc 1007 |
| LAYER MAP 95 DATATYPE 20 1007 // npc drawing |
| |
| LAYER nsdm 1008 |
| LAYER MAP 93 DATATYPE 44 1008 // nsdm drawing |
| |
| LAYER psdm 1009 |
| LAYER MAP 94 DATATYPE 20 1009 // psdm drawing |
| |
| LAYER mcon 1010 |
| LAYER MAP 67 DATATYPE 44 1010 // mcon drawing |
| |
| LAYER met1 1011 |
| LAYER MAP 68 DATATYPE 20 1011 // met1 drawing |
| |
| LAYER via 1012 |
| LAYER MAP 68 DATATYPE 44 1012 // via drawing |
| |
| LAYER met2 1013 |
| LAYER MAP 69 DATATYPE 20 1013 // met2 drawing |
| |
| LAYER via2 1014 |
| LAYER MAP 69 DATATYPE 44 1014 // via2 drawing |
| |
| LAYER met3 1015 |
| LAYER MAP 70 DATATYPE 20 1015 // met3 drawing |
| |
| LAYER via3 1016 |
| LAYER MAP 70 DATATYPE 44 1016 // via3 drawing |
| |
| LAYER met4 1017 |
| LAYER MAP 71 DATATYPE 20 1017 // met4 drawing |
| |
| LAYER via4 1018 |
| LAYER MAP 71 DATATYPE 44 1018 // via4 drawing |
| |
| LAYER met5 1019 |
| LAYER MAP 72 DATATYPE 20 1019 // met5 drawing |
| |
| LAYER pad 1020 |
| LAYER MAP 76 DATATYPE 20 1020 // pad drawing |
| |
| LAYER licon1 1021 |
| LAYER MAP 66 DATATYPE 44 1021 // licon1 drawing |
| |
| LAYER li1 1022 |
| LAYER MAP 67 DATATYPE 20 1022 // li1 drawing |
| |
| LAYER pnp 1023 |
| LAYER MAP 82 DATATYPE 44 1023 // pnp drawing |
| |
| LAYER npn 1024 |
| LAYER MAP 82 DATATYPE 20 1024 // npn drawing |
| |
| LAYER hvi 1025 |
| LAYER MAP 75 DATATYPE 20 1025 // hvi drawing |
| |
| LAYER ldntm 1026 |
| LAYER MAP 11 DATATYPE 44 1026 // ldntm drawing |
| |
| LAYER capacitor 1027 |
| LAYER MAP 82 DATATYPE 64 1027 // capacitor drawing |
| |
| LAYER ncm 1028 |
| LAYER MAP 92 DATATYPE 44 1028 // ncm drawing |
| |
| LAYER rdl 1029 |
| LAYER MAP 74 DATATYPE 20 1029 // rdl drawing |
| |
| LAYER rpm 1030 |
| LAYER MAP 86 DATATYPE 20 1030 // rpm drawing |
| |
| LAYER inductor 1031 |
| LAYER MAP 82 DATATYPE 24 1031 // inductor drawing |
| |
| LAYER pmm 1032 |
| LAYER MAP 85 DATATYPE 44 1032 // pmm drawing |
| |
| LAYER ubm 1033 |
| LAYER MAP 127 DATATYPE 21 1033 // ubm drawing |
| |
| LAYER bump 1034 |
| LAYER MAP 127 DATATYPE 22 1034 // bump drawing |
| |
| LAYER cviam 1035 |
| LAYER MAP 105 DATATYPE 20 1035 // cviam drawing |
| |
| LAYER cmm1 1036 |
| LAYER MAP 62 DATATYPE 20 1036 // cmm1 drawing |
| |
| LAYER cmm2 1037 |
| LAYER MAP 105 DATATYPE 44 1037 // cmm2 drawing |
| |
| LAYER cmm3 1038 |
| LAYER MAP 107 DATATYPE 20 1038 // cmm3 drawing |
| |
| LAYER metop1 1039 |
| LAYER MAP 70 DATATYPE 32 1039 // met3 option1 |
| |
| LAYER metop2 1040 |
| LAYER MAP 70 DATATYPE 33 1040 // met3 option2 |
| |
| LAYER metop3 1041 |
| LAYER MAP 70 DATATYPE 34 1041 // met3 option3 |
| |
| LAYER metop4 1042 |
| LAYER MAP 70 DATATYPE 35 1042 // met3 option4 |
| |
| LAYER metop5 1043 |
| LAYER MAP 70 DATATYPE 36 1043 // met3 option5 |
| |
| LAYER metop6 1044 |
| LAYER MAP 70 DATATYPE 37 1044 // met3 option6 |
| |
| LAYER metop7 1045 |
| LAYER MAP 70 DATATYPE 38 1045 // met3 option7 |
| |
| LAYER metop8 1046 |
| LAYER MAP 70 DATATYPE 39 1046 // met3 option8 |
| |
| LAYER diffTap 1002 1003 |
| // 1002 -> diff drawing |
| // 1003 -> tap drawing |
| |
| LAYER dnwelldg 1047 |
| LAYER MAP 64 DATATYPE 18 1047 // dnwell drawing |
| |
| LAYER DiodeID 1048 |
| LAYER MAP 81 DATATYPE 23 1048 // areaid diode |
| |
| LAYER ESDID 1049 |
| LAYER MAP 81 DATATYPE 19 1049 // areaid esd |
| |
| LAYER ENID 1050 |
| LAYER MAP 81 DATATYPE 57 1050 // areaid extendedDrain |
| |
| LAYER COREID 1051 |
| LAYER MAP 81 DATATYPE 2 1051 // areaid core |
| |
| LAYER SEALID 1052 |
| LAYER MAP 81 DATATYPE 1 1052 // areaid seal |
| |
| LAYER FRAMEID 1053 |
| LAYER MAP 81 DATATYPE 3 1053 // areaid frame |
| |
| LAYER LVID 1054 |
| LAYER MAP 81 DATATYPE 60 1054 // areaid lvNative |
| |
| LAYER STDCID 1055 |
| LAYER MAP 81 DATATYPE 4 1055 // areaid standardc |
| |
| LAYER localSub 1056 |
| LAYER MAP 81 DATATYPE 53 1056 // areaid substrateCut |
| |
| LAYER PHdiodeID 1057 |
| LAYER MAP 81 DATATYPE 81 1057 // areaid photo |
| |
| LAYER capdraw 1027 |
| // 1027 -> capacitor drawing |
| |
| LAYER polyGate 1058 |
| LAYER MAP 66 DATATYPE 9 1058 // poly gate |
| |
| LAYER polyModel 1059 |
| LAYER MAP 66 TEXTTYPE 83 1059 // poly model |
| |
| LAYER diffres 1060 |
| LAYER MAP 65 DATATYPE 13 1060 // diff res |
| |
| LAYER diffcut 1061 |
| LAYER MAP 65 DATATYPE 14 1061 // diff cut |
| |
| LAYER fuse 1062 |
| LAYER MAP 71 DATATYPE 17 1062 // met4 fuse |
| |
| LAYER padCenter 1063 |
| LAYER MAP 81 DATATYPE 20 1063 // padCenter drawing |
| |
| LAYER prune 1064 |
| LAYER MAP 84 DATATYPE 44 1064 // prune drawing |
| |
| LAYER polyres 1065 |
| LAYER MAP 66 DATATYPE 13 1065 // poly res |
| |
| LAYER polycut 1066 |
| LAYER MAP 66 DATATYPE 14 1066 // poly cut |
| |
| LAYER li1res 1067 |
| LAYER MAP 67 DATATYPE 13 1067 // li1 res |
| |
| LAYER li1cut 1068 |
| LAYER MAP 67 DATATYPE 14 1068 // li1 cut |
| |
| LAYER met1cut 1069 |
| LAYER MAP 68 DATATYPE 14 1069 // met1 cut |
| |
| LAYER met2cut 1070 |
| LAYER MAP 69 DATATYPE 14 1070 // met2 cut |
| |
| LAYER met3cut 1071 |
| LAYER MAP 70 DATATYPE 14 1071 // met3 cut |
| |
| LAYER met4cut 1072 |
| LAYER MAP 71 DATATYPE 14 1072 // met4 cut |
| |
| LAYER met5cut 1073 |
| LAYER MAP 72 DATATYPE 14 1073 // met5 cut |
| |
| LAYER rdlcut 1074 |
| LAYER MAP 74 DATATYPE 14 1074 // rdl cut |
| |
| LAYER pwres 1075 |
| LAYER MAP 64 DATATYPE 13 1075 // pwell res |
| |
| LAYER pwcut 1076 |
| LAYER MAP 64 DATATYPE 14 1076 // pwell cut |
| |
| LAYER padtt 1077 1078 |
| LAYER MAP 76 TEXTTYPE 20 1077 // pad drawing |
| LAYER MAP 76 TEXTTYPE 5 1078 // pad label |
| |
| LAYER rdltt 1079 1080 |
| LAYER MAP 74 TEXTTYPE 20 1079 // rdl drawing |
| LAYER MAP 74 TEXTTYPE 5 1080 // rdl label |
| |
| LAYER met5tt 1081 1082 1083 |
| LAYER MAP 72 TEXTTYPE 20 1081 // met5 drawing |
| LAYER MAP 72 TEXTTYPE 5 1082 // met5 label |
| LAYER MAP 72 TEXTTYPE 23 1083 // met5 net |
| |
| LAYER met4tt 1084 1085 1086 |
| LAYER MAP 71 TEXTTYPE 20 1084 // met4 drawing |
| LAYER MAP 71 TEXTTYPE 5 1085 // met4 label |
| LAYER MAP 71 TEXTTYPE 23 1086 // met4 net |
| |
| LAYER met3tt 1087 1088 1089 |
| LAYER MAP 70 TEXTTYPE 20 1087 // met3 drawing |
| LAYER MAP 70 TEXTTYPE 5 1088 // met3 label |
| LAYER MAP 70 TEXTTYPE 23 1089 // met3 net |
| |
| LAYER met2tt 1090 1091 1092 |
| LAYER MAP 69 TEXTTYPE 20 1090 // met2 drawing |
| LAYER MAP 69 TEXTTYPE 5 1091 // met2 label |
| LAYER MAP 69 TEXTTYPE 23 1092 // met2 net |
| |
| LAYER met1tt 1093 1094 1095 |
| LAYER MAP 68 TEXTTYPE 20 1093 // met1 drawing |
| LAYER MAP 68 TEXTTYPE 5 1094 // met1 label |
| LAYER MAP 68 TEXTTYPE 23 1095 // met1 net |
| |
| LAYER li1tt 1096 1097 1098 |
| LAYER MAP 67 TEXTTYPE 20 1096 // li1 drawing |
| LAYER MAP 67 TEXTTYPE 5 1097 // li1 label |
| LAYER MAP 67 TEXTTYPE 23 1098 // li1 net |
| |
| LAYER polytt 1099 1100 1101 |
| LAYER MAP 66 TEXTTYPE 20 1099 // poly drawing |
| LAYER MAP 66 TEXTTYPE 5 1100 // poly label |
| LAYER MAP 66 TEXTTYPE 23 1101 // poly net |
| |
| LAYER difftt 1102 1103 1104 |
| LAYER MAP 65 TEXTTYPE 20 1102 // diff drawing |
| LAYER MAP 65 TEXTTYPE 6 1103 // diff label |
| LAYER MAP 65 TEXTTYPE 23 1104 // diff net |
| |
| LAYER pwelltt 1105 |
| LAYER MAP 64 TEXTTYPE 59 1105 // pwell label |
| |
| LAYER pwellisott 1106 |
| LAYER MAP 44 TEXTTYPE 5 1106 // pwelliso label |
| |
| LAYER nwelltt 1107 1108 1109 |
| LAYER MAP 64 TEXTTYPE 20 1107 // nwell drawing |
| LAYER MAP 64 TEXTTYPE 5 1108 // nwell label |
| LAYER MAP 84 TEXTTYPE 23 1109 // nwell net |
| |
| LAYER textdraw 1110 |
| LAYER MAP 83 TEXTTYPE 44 1110 // text drawing |
| |
| LAYER pwell_pin 1111 |
| LAYER MAP 122 DATATYPE 16 1111 // pwell pin |
| |
| LAYER pwelliso_pin 1112 |
| LAYER MAP 44 DATATYPE 16 1112 // pwelliso pin |
| |
| LAYER nwell_pin 1113 |
| LAYER MAP 64 DATATYPE 16 1113 // nwell pin |
| |
| LAYER diff_pin 1114 |
| LAYER MAP 65 DATATYPE 16 1114 // diff pin |
| |
| LAYER poly_pin 1115 |
| LAYER MAP 66 DATATYPE 16 1115 // poly pin |
| |
| LAYER li1_pin 1116 |
| LAYER MAP 67 DATATYPE 16 1116 // li1 pin |
| |
| LAYER met1_pin 1117 |
| LAYER MAP 68 DATATYPE 16 1117 // met1 pin |
| |
| LAYER met2_pin 1118 |
| LAYER MAP 69 DATATYPE 16 1118 // met2 pin |
| |
| LAYER met3_pin 1119 |
| LAYER MAP 70 DATATYPE 16 1119 // met3 pin |
| |
| LAYER met4_pin 1120 |
| LAYER MAP 71 DATATYPE 16 1120 // met4 pin |
| |
| LAYER met5_pin 1121 |
| LAYER MAP 72 DATATYPE 16 1121 // met5 pin |
| |
| LAYER rdl_pin 1122 |
| LAYER MAP 74 DATATYPE 16 1122 // rdl pin |
| |
| LAYER pad_pin 1123 |
| LAYER MAP 76 DATATYPE 16 1123 // pad pin |
| |
| LAYER pwellpt 1124 |
| LAYER MAP 122 TEXTTYPE 16 1124 // pwell pin |
| LAYER MAP 122 TEXTTYPE 0 1124 // pwell pin |
| |
| LAYER pwellisopt 1125 |
| LAYER MAP 44 TEXTTYPE 16 1125 // pwelliso pin |
| LAYER MAP 44 TEXTTYPE 0 1125 // pwelliso pin |
| |
| LAYER nwellpt 1126 |
| LAYER MAP 64 TEXTTYPE 16 1126 // nwell pin |
| LAYER MAP 64 TEXTTYPE 0 1126 // nwell pin |
| |
| LAYER diffpt 1127 |
| LAYER MAP 65 TEXTTYPE 16 1127 // diff pin |
| LAYER MAP 65 TEXTTYPE 0 1127 // diff pin |
| |
| LAYER polypt 1128 |
| LAYER MAP 66 TEXTTYPE 16 1128 // poly pin |
| LAYER MAP 66 TEXTTYPE 0 1128 // poly pin |
| |
| LAYER li1pt 1129 |
| LAYER MAP 67 TEXTTYPE 16 1129 // li1 pin |
| LAYER MAP 67 TEXTTYPE 0 1129 // li1 pin |
| |
| LAYER met1pt 1130 |
| LAYER MAP 68 TEXTTYPE 16 1130 // met1 pin |
| LAYER MAP 68 TEXTTYPE 0 1130 // met1 pin |
| |
| LAYER met2pt 1131 |
| LAYER MAP 69 TEXTTYPE 16 1131 // met2 pin |
| LAYER MAP 69 TEXTTYPE 0 1131 // met2 pin |
| |
| LAYER met3pt 1132 |
| LAYER MAP 70 TEXTTYPE 16 1132 // met3 pin |
| LAYER MAP 70 TEXTTYPE 0 1132 // met3 pin |
| |
| LAYER met4pt 1133 |
| LAYER MAP 71 TEXTTYPE 16 1133 // met4 pin |
| LAYER MAP 71 TEXTTYPE 0 1133 // met4 pin |
| |
| LAYER met5pt 1134 |
| LAYER MAP 72 TEXTTYPE 16 1134 // met5 pin |
| LAYER MAP 72 TEXTTYPE 0 1134 // met5 pin |
| |
| LAYER rdlpt 1135 |
| LAYER MAP 74 TEXTTYPE 16 1135 // rdl pin |
| LAYER MAP 74 TEXTTYPE 0 1135 // rdl pin |
| |
| LAYER padpt 1136 |
| LAYER MAP 76 TEXTTYPE 16 1136 // pad pin |
| LAYER MAP 76 TEXTTYPE 0 1136 // pad pin |
| |
| LAYER met5probe 1137 |
| LAYER MAP 72 TEXTTYPE 25 1137 // met5 probe |
| |
| LAYER met4probe 1138 |
| LAYER MAP 71 TEXTTYPE 25 1138 // met4 probe |
| |
| LAYER met3probe 1139 |
| LAYER MAP 70 TEXTTYPE 25 1139 // met3 probe |
| |
| LAYER met2probe 1140 |
| LAYER MAP 69 TEXTTYPE 25 1140 // met2 probe |
| |
| LAYER met1probe 1141 |
| LAYER MAP 68 TEXTTYPE 25 1141 // met1 probe |
| |
| LAYER li1probe 1142 |
| LAYER MAP 67 TEXTTYPE 25 1142 // li1 probe |
| |
| LAYER polyprobe 1143 |
| LAYER MAP 66 TEXTTYPE 25 1143 // poly probe |
| |
| LAYER py_short 1144 |
| LAYER MAP 66 DATATYPE 15 1144 // poly short |
| |
| LAYER li_short 1145 |
| LAYER MAP 67 DATATYPE 15 1145 // li1 short |
| |
| LAYER m1_short 1146 |
| LAYER MAP 68 DATATYPE 15 1146 // met1 short |
| |
| LAYER m2_short 1147 |
| LAYER MAP 69 DATATYPE 15 1147 // met2 short |
| |
| LAYER m3_short 1148 |
| LAYER MAP 70 DATATYPE 15 1148 // met3 short |
| |
| LAYER m4_short 1149 |
| LAYER MAP 71 DATATYPE 15 1149 // met4 short |
| |
| LAYER m5_short 1150 |
| LAYER MAP 72 DATATYPE 15 1150 // met5 short |
| |
| LAYER rd_short 1151 |
| LAYER MAP 74 DATATYPE 15 1151 // rdl short |
| |
| LAYER fomWaffDrop 1152 |
| LAYER MAP 22 DATATYPE 24 1152 // cfom waffleDrop |
| |
| LAYER moduleCutAREA 1153 |
| LAYER MAP 81 DATATYPE 10 1153 // areaid moduleCut |
| |
| LAYER indLabel 1154 |
| LAYER MAP 82 TEXTTYPE 25 1154 // inductor label |
| |
| LAYER indTerm1 1155 |
| LAYER MAP 82 DATATYPE 26 1155 // inductor term1 |
| |
| LAYER indTerm2 1156 |
| LAYER MAP 82 DATATYPE 27 1156 // inductor term2 |
| |
| LAYER indTerm3 1157 |
| LAYER MAP 82 DATATYPE 28 1157 // inductor term3 |
| |
| LAYER capm 1158 |
| LAYER MAP 89 DATATYPE 44 1158 // capm drawing |
| |
| LAYER cap2m 1159 |
| LAYER MAP 97 DATATYPE 44 1159 // cap2m drawing |
| |
| LAYER urpm 1160 |
| LAYER MAP 79 DATATYPE 20 1160 // urpm drawing |
| |
| LAYER EXTDRAIN20 1161 |
| LAYER MAP 81 DATATYPE 58 1161 // extd20v drawing |
| |
| LAYER pwbm 1162 |
| LAYER MAP 19 DATATYPE 44 1162 // pwbm drawing |
| |
| LAYER pwde 1163 |
| LAYER MAP 124 DATATYPE 20 1163 // pwbm drawing |
| |
| LAYER LOWVTID 1164 |
| LAYER MAP 81 DATATYPE 108 1164 // areaid low_vt drawing |
| |
| LAYER uhvi 1165 |
| LAYER MAP 74 DATATYPE 22 1165 // uhvi drawing |
| |
| LAYER contResID 1166 |
| LAYER MAP 66 DATATYPE 21 1166 // areaid contres drawing |
| /// End layer definitions |
| |
| LAYOUT BASE LAYER diff |
| LAYOUT BASE LAYER tap |
| LAYOUT BASE LAYER poly |
| LAYOUT BASE LAYER pnp |
| LAYOUT BASE LAYER npn |
| LAYOUT BASE LAYER nsdm |
| LAYOUT BASE LAYER psdm |
| LAYOUT BASE LAYER hvi |
| LAYOUT BASE LAYER lvtn |
| LAYOUT BASE LAYER hvtp |
| LAYOUT BASE LAYER npc |
| LAYOUT BASE LAYER DiodeId |
| LAYOUT BASE LAYER ESDID |
| LAYOUT BASE LAYER COREID |
| LAYOUT BASE LAYER ENID |
| LAYOUT BASE LAYER EXTDRAIN20 |
| LAYOUT BASE LAYER polyGate |
| LAYOUT BASE LAYER capdraw |
| LAYOUT BASE LAYER diffres |
| LAYOUT BASE LAYER polyres |
| LAYOUT BASE LAYER li1res |
| LAYOUT BASE LAYER diffcut |
| LAYOUT BASE LAYER polycut |
| LAYOUT BASE LAYER li1cut |
| LAYOUT BASE LAYER met1cut |
| LAYOUT BASE LAYER met2cut |
| LAYOUT BASE LAYER met3cut |
| LAYOUT BASE LAYER met4cut |
| LAYOUT BASE LAYER met5cut |
| LAYOUT BASE LAYER rdlcut |
| LAYOUT BASE LAYER polyprobe |
| LAYOUT BASE LAYER li1probe |
| LAYOUT BASE LAYER met1probe |
| LAYOUT BASE LAYER met2probe |
| LAYOUT BASE LAYER met3probe |
| LAYOUT BASE LAYER met4probe |
| LAYOUT BASE LAYER met5probe |
| LAYOUT BASE LAYER m1_short |
| LAYOUT BASE LAYER m2_short |
| LAYOUT BASE LAYER m3_short |
| LAYOUT BASE LAYER m4_short |
| LAYOUT BASE LAYER m5_short |
| LAYOUT BASE LAYER py_short |
| LAYOUT BASE LAYER li_short |
| LAYOUT BASE LAYER fuse |
| LAYOUT BASE LAYER metop1 |
| LAYOUT BASE LAYER metop2 |
| LAYOUT BASE LAYER metop3 |
| LAYOUT BASE LAYER metop4 |
| LAYOUT BASE LAYER metop5 |
| LAYOUT BASE LAYER metop6 |
| LAYOUT BASE LAYER metop7 |
| LAYOUT BASE LAYER metop8 |
| dnwell = COPY dnwelldg |
| LAYOUT BASE LAYER dnwelldg |
| "k_0_dnwelldg" { |
| @ keep: dnwelldg - dnwelldg |
| @ drawn dnwell |
| COPY dnwelldg |
| } |
| LVS SPICE ALLOW Unquoted Strings YES |
| |
| MET1_waff = COPY 4000 |
| MET2_waff = COPY 4001 |
| MET3_waff = COPY 4002 |
| POLY_waff = COPY 4003 |
| FOM_waff = COPY 4004 |
| substrateExtent = EXTENT |
| q1substrateTmp = localSub NOT (SIZE localSub BY -0.005) |
| //q0substrateTmp = dnwelldg AND nwell |
| q0substrateTmp = dnwell_nonExtDrain AND nwell |
| //substrateIsoOther = substrateExtent NOT ((dnwelldg NOT (SIZE dnwelldg BY -0.01)) OR q0substrateTmp) |
| substrateIsoOther = substrateExtent NOT ((dnwell_nonExtDrain NOT (SIZE dnwell_nonExtDrain BY -0.01)) OR q0substrateTmp) |
| substrateLocal = substrateIsoOther NOT q1substrateTmp |
| substrateTmp = COPY substrateLocal |
| SubstrateTmp1 = substrateTmp NOT npn |
| //add the dnwell with extended drain |
| |
| dnwell_extDrain = dnwelldg AND (INTERACT (OR pwbm (HOLES pwbm)) EXTDRAIN20) |
| dnwell_nonExtDrain = dnwelldg NOT dnwell_extDrain |
| //SubstrateIsoTmp = SIZE (dnwelldg NOT nwell) BY -0.005 |
| SubstrateIsoTmp = SIZE (dnwell_nonExtDrain NOT nwell) BY -0.005 |
| //;; used for parasitic hv dnwell diode to substrate with contact to regular substrate |
| //SubstrateSpecial = SIZE dnwelldg BY 0.005 |
| SubstrateSpecial = SIZE dnwell_nonExtDrain BY 0.005 |
| //SubstrateSpecialCont = SIZE (dnwelldg NOT (SIZE dnwelldg BY -0.005)) BY 0.005 |
| SubstrateSpecialCont = SIZE (dnwell_nonExtDrain NOT (SIZE dnwell_nonExtDrain BY -0.005)) BY 0.005 |
| CONNECT SubstrateSpecial Substrate BY SubstrateSpecialCont |
| //;;used for parasitic hv dnwell diode to substrate with contact to regular substrate |
| dnwell_hv = NOT (dnwelldg AND (INTERACT pwbm (uhvi OR LOWVTID))) nwell |
| SubstrateHVSpecial = SIZE dnwell_hv BY 0.005 |
| SubstrateHVSpecialCont = SIZE (dnwell_hv NOT (SIZE dnwell_hv BY -0.005)) BY 0.005 |
| CONNECT SubstrateHVSpecial Substrate BY SubstrateHVSpecialCont |
| |
| PnpNwell_tmp = nwell AND pnp |
| NpnNwell_tmp = INTERACT nwell npn |
| MosNwell_tmp = nwell NOT (pnp OR npn) |
| MOSDIFF = diff NOT (pnp OR npn) |
| PNPDIFF = diff AND pnp |
| NPNDIFF = diff AND npn |
| MOSDIFFnotPOLY = MOSDIFF NOT poly |
| MOSDIFFandPOLY = MOSDIFF AND poly |
| NMOSDIFFnotPOLY = MOSDIFFnotPOLY NOT nwell |
| NMOSDIFFandHVInotPOLY = NMOSDIFFnotPOLY AND hvi |
| NMOSDIFFnotHVInotPOLY = NMOSDIFFnotPOLY NOT NMOSDIFFandHVInotPOLY |
| PMOSDIFFnotPOLY = MOSDIFFnotPOLY AND nwell |
| PMOSDIFFandHVInotPOLY = PMOSDIFFnotPOLY AND hvi |
| PMOSDIFFnotHVInotPOLY = PMOSDIFFnotPOLY NOT PMOSDIFFandHVInotPOLY |
| NMOSDIFF = MOSDIFF NOT nwell |
| PMOSDIFF = MOSDIFF AND nwell |
| TAPgate = tap AND poly |
| NTAP = tap AND nwell |
| NTAP_pnp = NTAP AND pnp |
| NTAP_npn = INTERACT NTAP npn |
| NTAP_notbjt = NTAP NOT (NTAP_npn OR NTAP_pnp) |
| PTAP = tap NOT nwell |
| PTAP_pnp = PTAP AND pnp |
| PTAP_npn = INTERACT PTAP npn |
| PTAP_defet20 = PTAP AND (SIZE EXTDRAIN20 BY 1.25) |
| //PTAP_notbjt = PTAP NOT (PTAP_npn OR PTAP_pnp) |
| PTAP_notbjt = PTAP NOT (PTAP_npn OR (PTAP_pnp OR PTAP_defet20)) |
| PTAP_pwellres = TOUCH PTAP pwres |
| PTAP_tmp = PTAP_notbjt NOT PTAP_pwellres |
| PTAP_NotDnwell = PTAP_tmp NOT dnwell |
| nDiffRing = DONUT NDIFF_cond |
| nDiffHole = HOLES nDiffRing |
| nWellTap = nwell INSIDE NTAP_notbjt |
| ESDnWellTap = (nDiffHole INSIDE nWellTap) AND ESDID |
| diffESDtap = diff OR ESDnWellTap |
| MOSDIFFTAPESDnotPOLY = ((diff OR ESDnWellTap) NOT poly) AND ESDID |
| MOSDIFFTAPESDandPOLY = ((diff OR ESDnWellTap) AND poly) AND ESDID |
| pDiffHole = HOLES PDIFF_COND |
| nwellHole = HOLES nwell |
| nwellRing = DONUT nwell |
| nWellRingTap = nwellHole INSIDE PTAP_notbjt |
| ESDnWellRingTap = (pDiffHole INSIDE nWellRingTap) AND ESDID |
| pdiffESDtap = pdiff OR ESDnWellRingTap |
| pdiff = diff AND nwell |
| PMOSDIFFTAPESDnotPOLY = (pdiffESDtap NOT poly) AND ESDID |
| PMOSDIFFTAPESDandPOLY = (pdiffESDtap AND poly) AND ESDID |
| blackBoxCells = INSIDE CELL poly "s8rf_pmedlvt_W1p68_L0p15_4F" "s8rf_pmedlvt_W1p68_L0p15_2F" "s8rf_pmedlvt_W0p84_L0p15_2F" "s8rf_pshort_W5p0_L0p15_2F" "s8rf_pshort_W3p0_L0p15_2F" "s8rf_pshort_W1p68_L0p15_4F" "s8rf_pshort_W1p68_L0p15_2F" "s8rf_pshort_W0p84_L0p15_2F" "s8rf_pshort_W5p0_L0p25_M4_b" "s8rf_pshort_W5p0_L0p25_M2_b" "s8rf_pshort_W5p0_L0p18_M4_b" "s8rf_pshort_W5p0_L0p18_M2_b" "s8rf_pshort_W5p0_L0p15_M4_b" "s8rf_pshort_W5p0_L0p15_M2_b" "s8rf_pshort_W3p0_L0p25_M4_b" "s8rf_pshort_W3p0_L0p25_M2_b" "s8rf_pshort_W3p0_L0p18_M4_b" "s8rf_pshort_W3p0_L0p18_M2_b" "s8rf_pshort_W3p0_L0p15_M4_b" "s8rf_pshort_W3p0_L0p15_M2_b" "s8rf_pshort_W1p65_L0p25_M4_b" "s8rf_pshort_W1p65_L0p25_M2_b" "s8rf_pshort_W1p65_L0p18_M4_b" "s8rf_pshort_W1p65_L0p18_M2_b" "s8rf_pshort_W1p65_L0p15_M4_b" "s8rf_pshort_W1p65_L0p15_M2_b" "s8rf_nshort_W5p0_L0p25_M4_b" "s8rf_nshort_W5p0_L0p25_M2_b" "s8rf_nshort_W5p0_L0p18_M4_b" "s8rf_nshort_W5p0_L0p18_M2_b" "s8rf_nshort_W5p0_L0p15_M4_b" "s8rf_nshort_W5p0_L0p15_M2_b" "s8rf_nshort_W3p0_L0p25_M4_b" "s8rf_nshort_W3p0_L0p25_M2_b" "s8rf_nshort_W3p0_L0p18_M4_b" "s8rf_nshort_W3p0_L0p18_M2_b" "s8rf_nshort_W3p0_L0p15_M4_b" "s8rf_nshort_W3p0_L0p15_M2_b" "s8rf_nshort_W1p65_L0p25_M4_b" "s8rf_nshort_W1p65_L0p25_M2_b" "s8rf_nshort_W1p65_L0p18_M4_b" "s8rf_nshort_W1p65_L0p18_M2_b" "s8rf_nshort_W1p65_L0p15_M4_b" "s8rf_nshort_W1p65_L0p15_M2_b" "s8rf_nlowvt_W3p0_L0p15_8F" "s8rf_nlowvt_W3p0_L0p15_4F" "s8rf_nlowvt_W3p0_L0p15_2F" "s8rf_nlowvt_W0p84_L0p15_8F" "s8rf_nlowvt_W0p84_L0p15_4F" "s8rf_nlowvt_W0p84_L0p15_2F" "s8rf_nlowvt_W0p42_L0p15_2F" "s8rf_nlowvt_W5p0_L0p25_M4_b" "s8rf_nlowvt_W5p0_L0p25_M2_b" "s8rf_nlowvt_W5p0_L0p18_M4_b" "s8rf_nlowvt_W5p0_L0p18_M2_b" "s8rf_nlowvt_W5p0_L0p15_M4_b" "s8rf_nlowvt_W5p0_L0p15_M2_b" "s8rf_nlowvt_W3p0_L0p25_M4_b" "s8rf_nlowvt_W3p0_L0p25_M2_b" "s8rf_nlowvt_W3p0_L0p18_M4_b" "s8rf_nlowvt_W3p0_L0p18_M2_b" "s8rf_nlowvt_W3p0_L0p15_M4_b" "s8rf_nlowvt_W3p0_L0p15_M2_b" "s8rf_nlowvt_W1p65_L0p25_M4_b" "s8rf_nlowvt_W1p65_L0p25_M2_b" "s8rf_nlowvt_W1p65_L0p18_M4_b" "s8rf_nlowvt_W1p65_L0p18_M2_b" "s8rf_nlowvt_W1p65_L0p15_M4_b" "s8rf_nlowvt_W1p65_L0p15_M2_b" "s8rf_nhv_W5p0_L0p5_M2_b" "s8rf_nhv_W3p0_L0p5_M2_b" "s8rf_nhv_W7p0_L0p5_M4_b" "s8rf_nhv_W7p0_L0p5_M10_b" "s8rf_nhv_W5p0_L0p5_M4_b" "s8rf_nhv_W5p0_L0p5_M10_b" "s8rf_nhv_W3p0_L0p5_M4_b" "s8rf_nhv_W3p0_L0p5_M10_b" |
| |
| // ;ss added pmm |
| // rdlcon = rdl AND pad AND met5) |
| |
| rdlcon = rdl AND (pad AND (met5 AND pmm)) |
| |
| MET5_rdl = INTERACT MET5_cond rdl |
| derivedGate = MOSDIFFandPOLY OUTSIDE polyGate |
| userGate = MOSDIFFandPOLY AND polyGate |
| //allGate = ((derivedGate OR userGate) NOT ENID) NOT ((moduleCutAREA AND prune) OR vppcapNHVnative) |
| allGate = ((derivedGate OR userGate) NOT (ENID OR EXTDRAIN20)) NOT ((moduleCutAREA AND prune) OR vppcapNHVnative) |
| MOSDIFFnotAllGate = MOSDIFF NOT allGate |
| esdGate = allGate AND ESDID |
| nesd = esdGate NOT nwell |
| nesdHV = INTERACT nesd hvi |
| nhvnativeesd = nesdHV AND lvtn |
| nhvesd = nesdHV NOT nhvnativeesd |
| nshortesd = nesd NOT nesdHV |
| pesd = esdGate AND nwell |
| phvesd = INTERACT pesd hvi |
| pshortesd = pesd NOT phvesd |
| fetGate = allGate NOT esdGate |
| nfet = fetGate NOT nwell |
| pfet = fetGate AND nwell |
| lvtnfet = (INTERACT nfet lvtn) NOT nlvtpass_drc |
| hvinmos = INTERACT nfet hvi |
| hvilvtnfet = lvtnfet AND hvinmos |
| fnpass = WITH TEXT (ldntm AND |
| (nfet AND hvinmos)) "fnpass" polyModel |
| ntvnative = (hvilvtnfet NOT fnpass) AND LVID |
| nhvnative = (hvilvtnfet NOT fnpass) NOT LVID |
| nhvnativeW10 = EXPAND EDGE (LENGTH (nhvnative NOT COINCIDENT EDGE diff) == 10.0) INSIDE BY 0.005 |
| nhvnativeL4 = EXPAND EDGE (LENGTH (nhvnative COINCIDENT EDGE diff) == 4.0) INSIDE BY 0.005 |
| nhvnative10x4 = INTERACT (INTERACT nhvnative nhvnativeW10) nhvnativeL4 |
| nhvnativeNoCap = nhvnative NOT nhvnative10x4 |
| nhv = hvinmos NOT (nhvnative OR |
| (ntvnative OR fnpass)) |
| sonos_e = lvtnfet AND (dnwell AND |
| (tunm AND ldntm)) |
| nlowvt = lvtnfet NOT (hvilvtnfet OR sonos_e) |
| nfet_01v8 = nfet NOT (lvtnfet OR hvinmos) |
| nshort_PERI = nfet_01v8 NOT COREID |
| |
| // ;ss |
| // nshort_CORE = nfet_01v8 AND COREID |
| |
| nshort_COREorg = (nfet_01v8 NOT nlvtpass_drc) AND COREID |
| nshort_COREnew = (nfet_01v8 AND nlvtpass_drc) AND COREID |
| |
| phv = INTERACT pfet hvi |
| phvW5 = EXPAND EDGE (LENGTH (phv NOT COINCIDENT EDGE diff) == 5.0) INSIDE BY 0.005 |
| phvL4 = EXPAND EDGE (LENGTH (phv COINCIDENT EDGE diff) == 4.0) INSIDE BY 0.005 |
| phv5x4 = INTERACT (INTERACT phv phvW5) phvL4 |
| phvNoCap = phv NOT phv5x4 |
| PFET_01V8_HVT = INTERACT pfet hvtp |
| phighvtW5 = EXPAND EDGE (LENGTH (PFET_01V8_HVT NOT COINCIDENT EDGE diff) == 5.0) INSIDE BY 0.005 |
| phighvtL4 = EXPAND EDGE (LENGTH (PFET_01V8_HVT COINCIDENT EDGE diff) == 4.0) INSIDE BY 0.005 |
| phighvt5x4 = INTERACT (INTERACT PFET_01V8_HVT phighvtW5) phighvtL4 |
| phighvtNoCap = PFET_01V8_HVT NOT phighvt5x4 |
| phighvt_CORE = PFET_01V8_HVT AND COREID |
| phighvt5x4_PERI = phighvt5x4 NOT COREID |
| phighvtNoCap_PERI = phighvtNoCap NOT COREID |
| plowvt = pfet AND lvtn |
| plowvtW5 = EXPAND EDGE (LENGTH (plowvt NOT COINCIDENT EDGE diff) == 5.0) INSIDE BY 0.005 |
| plowvtL4 = EXPAND EDGE (LENGTH (plowvt COINCIDENT EDGE diff) == 4.0) INSIDE BY 0.005 |
| plowvt5x4 = INTERACT (INTERACT plowvt plowvtW5) plowvtL4 |
| plowvtNoCap = plowvt NOT plowvt5x4 |
| pshort = (pfet OR pshortesd) NOT (phv OR |
| (PFET_01V8_HVT OR plowvt)) |
| pshortW5 = EXPAND EDGE (LENGTH (pshort NOT COINCIDENT EDGE diff) == 5.0) INSIDE BY 0.005 |
| pshortL4 = EXPAND EDGE (LENGTH (pshort COINCIDENT EDGE diff) == 4.0) INSIDE BY 0.005 |
| pshort5x4 = INTERACT (INTERACT pshort pshortW5) pshortL4 |
| pshortNoCap = pshort NOT pshort5x4 |
| xcnwvc = ((TAPgate AND nwell) NOT COREID) NOT (hvtp OR hvi) |
| xcnwvc2 = (((TAPgate AND nwell) NOT COREID) AND hvtp) NOT hvi |
| xchvnwc = ((TAPgate AND nwell) NOT COREID) AND hvi |
| varactor = (SIZE (xcnwvc2 OR xcnwvc) BY 0.465) OR xchvnwc |
| ppu_drc = WITH TEXT allGate "ppu" polyModel |
| nlvtpass_drc = WITH TEXT allGate "nlvtpass" polyModel |
| fnpass_drc = WITH TEXT allGate "fnpass" polyModel |
| npass_drc = WITH TEXT allGate "npass" polyModel |
| npd_drc = WITH TEXT allGate "npd" polyModel |
| npd_npass_drc = npass_drc OR npd_drc |
| |
| // ;ss same illegal device checks as lvsRules |
| |
| "r_0_Illegal ppu device" { |
| @ Illegal ppu device: ppu_drc must be enclosed by nwell |
| ppu_drc NOT nwell |
| } |
| "r_1_Illegal ppu device" { |
| @ Illegal ppu device: ppu_drc must be enclosed by hvtp |
| ppu_drc NOT hvtp |
| } |
| "r_2_Illegal ppu device" { |
| @ Illegal ppu device: ppu_drc must be enclosed by ncm |
| ppu_drc NOT ncm |
| } |
| "r_3_Illegal ppu device" { |
| @ Illegal ppu device: ppu_drc must be enclosed by psdm |
| ppu_drc NOT psdm |
| } |
| "r_4_Illegal ppu device" { |
| @ Illegal ppu device: ppu_drc must be enclosed by COREID |
| ppu_drc NOT COREID |
| } |
| "r_5_Illegal fnpass device" { |
| @ Illegal fnpass device: fnpass_drc must be enclosed by hvi |
| fnpass_drc NOT hvi |
| } |
| "r_6_Illegal fnpass device" { |
| @ Illegal fnpass device: fnpass_drc must be enclosed by ldntm |
| fnpass_drc NOT ldntm |
| } |
| "r_7_Illegal fnpass device" { |
| @ Illegal fnpass device: fnpass_drc must be enclosed by nsdm |
| fnpass_drc NOT nsdm |
| } |
| "r_8_Illegal fnpass device" { |
| @ Illegal fnpass device: fnpass_drc must be enclosed by COREID |
| fnpass_drc NOT COREID |
| } |
| "r_9_Illegal npass/npd device" { |
| @ Illegal npass/npd device: npd_npass_drc must be enclosed by nsdm |
| npd_npass_drc NOT nsdm |
| } |
| "r_10_Illegal npass/npd device" { |
| @ Illegal npass/npd device: npd_npass_drc must be enclosed by COREID |
| npd_npass_drc NOT COREID |
| } |
| "r_11_Illegal nlvtpass device" { |
| @ Illegal nlvtpass device: nlvtpass_drc must be enclosed by lvtn |
| nlvtpass_drc NOT lvtn |
| } |
| "r_12_Illegal nlvtpass device" { |
| @ Illegal nlvtpass device: nlvtpass_drc must be enclosed by nsdm |
| nlvtpass_drc NOT nsdm |
| } |
| "r_13_Illegal nlvtpass device" { |
| @ Illegal nlvtpass device: nlvtpass_drc must be enclosed by COREID |
| nlvtpass_drc NOT COREID |
| } |
| "r_14_Illegal nfet_01v8 device nshort_PERI must not overlap ncm" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap ncm |
| nshort_PERI AND ncm |
| } |
| "r_15_Illegal nfet_01v8 device nshort_PERI must not overlap nwell" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap nwell |
| nshort_PERI AND nwell |
| } |
| "r_16_Illegal nfet_01v8 device nshort_PERI must not overlap tap" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap tap |
| nshort_PERI AND tap |
| } |
| "r_17_Illegal nfet_01v8 device nshort_PERI must not overlap tunm" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap tunm |
| nshort_PERI AND tunm |
| } |
| "r_18_Illegal nfet_01v8 device nshort_PERI must not overlap diffres" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap diffres |
| nshort_PERI AND diffres |
| } |
| "r_19_Illegal nfet_01v8 device nshort_PERI must not overlap diffcut" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap diffcut |
| nshort_PERI AND diffcut |
| } |
| "r_20_Illegal nfet_01v8 device nshort_PERI must not overlap npc" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap npc |
| nshort_PERI AND npc |
| } |
| "r_21_Illegal nfet_01v8 device nshort_PERI must not overlap polyres" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap polyres |
| nshort_PERI AND polyres |
| } |
| "r_22_Illegal nfet_01v8 device nshort_PERI must not overlap polycut" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap polycut |
| nshort_PERI AND polycut |
| } |
| "r_23_Illegal nfet_01v8 device nshort_PERI must not overlap li1res" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap li1res |
| nshort_PERI AND li1res |
| } |
| "r_24_Illegal nfet_01v8 device nshort_PERI must not overlap li1cut" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap li1cut |
| nshort_PERI AND li1cut |
| } |
| "r_25_Illegal nfet_01v8 device nshort_PERI must not overlap fuse" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap fuse |
| nshort_PERI AND fuse |
| } |
| "r_26_Illegal nfet_01v8 device nshort_PERI must not overlap psdm" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap psdm |
| nshort_PERI AND psdm |
| } |
| "r_27_Illegal nfet_01v8 device nshort_PERI must not overlap capacitor" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap capacitor |
| nshort_PERI AND capacitor |
| } |
| "r_28_Illegal nfet_01v8 device nshort_PERI must not overlap LVID" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap LVID |
| nshort_PERI AND LVID |
| } |
| "r_29_Illegal nfet_01v8 device nshort_PERI must not overlap ENID" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap ENID |
| nshort_PERI AND ENID |
| } |
| "r_30_Illegal nfet_01v8 device nshort_PERI must not overlap hvtp" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap hvtp |
| nshort_PERI AND hvtp |
| } |
| "r_31_Illegal nfet_01v8 device nshort_PERI must not overlap lvtn" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap lvtn |
| nshort_PERI AND lvtn |
| } |
| "r_32_Illegal nfet_01v8 device nshort_PERI must not overlap hvi" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap hvi |
| nshort_PERI AND hvi |
| } |
| "r_33_Illegal nfet_01v8 device nshort_PERI must not overlap pnp" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap pnp |
| nshort_PERI AND pnp |
| } |
| "r_34_Illegal nfet_01v8 device nshort_PERI must not overlap DiodeID" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap DiodeID |
| nshort_PERI AND DiodeID |
| } |
| "r_35_Illegal nfet_01v8 device nshort_PERI must not overlap PHdiodeID" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap PHdiodeID |
| nshort_PERI AND PHdiodeID |
| } |
| "r_36_Illegal nfet_01v8 device nshort_PERI must not overlap ldntm" { |
| @ Illegal nfet_01v8 device: nshort_PERI must not overlap ldntm |
| nshort_PERI AND ldntm |
| } |
| "r_37_Illegal npass/npd device nshort_COREorg must not overlap ncm" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap ncm |
| nshort_COREorg AND ncm |
| } |
| "r_38_Illegal npass/npd device nshort_COREorg must not overlap nwell" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap nwell |
| nshort_COREorg AND nwell |
| } |
| "r_39_Illegal npass/npd device nshort_COREorg must not overlap tap" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap tap |
| nshort_COREorg AND tap |
| } |
| "r_40_Illegal npass/npd device nshort_COREorg must not overlap tunm" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap tunm |
| nshort_COREorg AND tunm |
| } |
| "r_41_Illegal npass/npd device nshort_COREorg must not overlap diffres" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap diffres |
| nshort_COREorg AND diffres |
| } |
| "r_42_Illegal npass/npd device nshort_COREorg must not overlap diffcut" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap diffcut |
| nshort_COREorg AND diffcut |
| } |
| "r_43_Illegal npass/npd device nshort_COREorg must not overlap npc" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap npc |
| nshort_COREorg AND npc |
| } |
| "r_44_Illegal npass/npd device nshort_COREorg must not overlap polyres" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap polyres |
| nshort_COREorg AND polyres |
| } |
| "r_45_Illegal npass/npd device nshort_COREorg must not overlap polycut" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap polycut |
| nshort_COREorg AND polycut |
| } |
| "r_46_Illegal npass/npd device nshort_COREorg must not overlap li1res" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap li1res |
| nshort_COREorg AND li1res |
| } |
| "r_47_Illegal npass/npd device nshort_COREorg must not overlap li1cut" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap li1cut |
| nshort_COREorg AND li1cut |
| } |
| "r_48_Illegal npass/npd device nshort_COREorg must not overlap fuse" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap fuse |
| nshort_COREorg AND fuse |
| } |
| "r_49_Illegal npass/npd device nshort_COREorg must not overlap psdm" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap psdm |
| nshort_COREorg AND psdm |
| } |
| "r_50_Illegal npass/npd device nshort_COREorg must not overlap capacitor" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap capacitor |
| nshort_COREorg AND capacitor |
| } |
| "r_51_Illegal npass/npd device nshort_COREorg must not overlap LVID" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap LVID |
| nshort_COREorg AND LVID |
| } |
| "r_52_Illegal npass/npd device nshort_COREorg must not overlap ENID" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap ENID |
| nshort_COREorg AND ENID |
| } |
| "r_53_Illegal npass/npd device nshort_COREorg must not overlap hvtp" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap hvtp |
| nshort_COREorg AND hvtp |
| } |
| "r_54_Illegal npass/npd device nshort_COREorg must not overlap lvtn" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap lvtn |
| nshort_COREorg AND lvtn |
| } |
| "r_55_Illegal npass/npd device nshort_COREorg must not overlap hvi" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap hvi |
| nshort_COREorg AND hvi |
| } |
| "r_56_Illegal npass/npd device nshort_COREorg must not overlap pnp" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap pnp |
| nshort_COREorg AND pnp |
| } |
| "r_57_Illegal npass/npd device nshort_COREorg must not overlap DiodeID" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap DiodeID |
| nshort_COREorg AND DiodeID |
| } |
| "r_58_Illegal npass/npd device nshort_COREorg must not overlap ESDID" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap ESDID |
| nshort_COREorg AND ESDID |
| } |
| "r_59_Illegal npass/npd device nshort_COREorg must not overlap PHdiodeID" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap PHdiodeID |
| nshort_COREorg AND PHdiodeID |
| } |
| "r_60_Illegal npass/npd device nshort_COREorg must not overlap ldntm" { |
| @ Illegal npass/npd device: nshort_COREorg must not overlap ldntm |
| nshort_COREorg AND ldntm |
| } |
| "r_61_Illegal npass/npd device nshort_COREnew must not overlap ncm" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap ncm |
| nshort_COREnew AND ncm |
| } |
| "r_62_Illegal npass/npd device nshort_COREnew must not overlap nwell" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap nwell |
| nshort_COREnew AND nwell |
| } |
| "r_63_Illegal npass/npd device nshort_COREnew must not overlap tap" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap tap |
| nshort_COREnew AND tap |
| } |
| "r_64_Illegal npass/npd device nshort_COREnew must not overlap tunm" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap tunm |
| nshort_COREnew AND tunm |
| } |
| "r_65_Illegal npass/npd device nshort_COREnew must not overlap diffres" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap diffres |
| nshort_COREnew AND diffres |
| } |
| "r_66_Illegal npass/npd device nshort_COREnew must not overlap diffcut" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap diffcut |
| nshort_COREnew AND diffcut |
| } |
| "r_67_Illegal npass/npd device nshort_COREnew must not overlap npc" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap npc |
| nshort_COREnew AND npc |
| } |
| "r_68_Illegal npass/npd device nshort_COREnew must not overlap polyres" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap polyres |
| nshort_COREnew AND polyres |
| } |
| "r_69_Illegal npass/npd device nshort_COREnew must not overlap polycut" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap polycut |
| nshort_COREnew AND polycut |
| } |
| "r_70_Illegal npass/npd device nshort_COREnew must not overlap li1res" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap li1res |
| nshort_COREnew AND li1res |
| } |
| "r_71_Illegal npass/npd device nshort_COREnew must not overlap li1cut" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap li1cut |
| nshort_COREnew AND li1cut |
| } |
| "r_72_Illegal npass/npd device nshort_COREnew must not overlap fuse" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap fuse |
| nshort_COREnew AND fuse |
| } |
| "r_73_Illegal npass/npd device nshort_COREnew must not overlap psdm" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap psdm |
| nshort_COREnew AND psdm |
| } |
| "r_74_Illegal npass/npd device nshort_COREnew must not overlap capacitor" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap capacitor |
| nshort_COREnew AND capacitor |
| } |
| "r_75_Illegal npass/npd device nshort_COREnew must not overlap LVID" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap LVID |
| nshort_COREnew AND LVID |
| } |
| "r_76_Illegal npass/npd device nshort_COREnew must not overlap ENID" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap ENID |
| nshort_COREnew AND ENID |
| } |
| "r_77_Illegal npass/npd device nshort_COREnew must not overlap hvtp" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap hvtp |
| nshort_COREnew AND hvtp |
| } |
| "r_78_Illegal npass/npd device nshort_COREnew must not overlap hvi" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap hvi |
| nshort_COREnew AND hvi |
| } |
| "r_79_Illegal npass/npd device nshort_COREnew must not overlap pnp" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap pnp |
| nshort_COREnew AND pnp |
| } |
| "r_80_Illegal npass/npd device nshort_COREnew must not overlap DiodeID" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap DiodeID |
| nshort_COREnew AND DiodeID |
| } |
| "r_81_Illegal npass/npd device nshort_COREnew must not overlap ESDID" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap ESDID |
| nshort_COREnew AND ESDID |
| } |
| "r_82_Illegal npass/npd device nshort_COREnew must not overlap PHdiodeID" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap PHdiodeID |
| nshort_COREnew AND PHdiodeID |
| } |
| "r_83_Illegal npass/npd device nshort_COREnew must not overlap ldntm" { |
| @ Illegal npass/npd device: nshort_COREnew must not overlap ldntm |
| nshort_COREnew AND ldntm |
| } |
| "r_84_Illegal nlowvt device nlowvt must not overlap ncm" { |
| @ Illegal nlowvt device: nlowvt must not overlap ncm |
| nlowvt AND ncm |
| } |
| "r_85_Illegal nlowvt device nlowvt must not overlap nwell" { |
| @ Illegal nlowvt device: nlowvt must not overlap nwell |
| nlowvt AND nwell |
| } |
| "r_86_Illegal nlowvt device nlowvt must not overlap tap" { |
| @ Illegal nlowvt device: nlowvt must not overlap tap |
| nlowvt AND tap |
| } |
| "r_87_Illegal nlowvt device nlowvt must not overlap tunm" { |
| @ Illegal nlowvt device: nlowvt must not overlap tunm |
| nlowvt AND tunm |
| } |
| "r_88_Illegal nlowvt device nlowvt must not overlap diffres" { |
| @ Illegal nlowvt device: nlowvt must not overlap diffres |
| nlowvt AND diffres |
| } |
| "r_89_Illegal nlowvt device nlowvt must not overlap diffcut" { |
| @ Illegal nlowvt device: nlowvt must not overlap diffcut |
| nlowvt AND diffcut |
| } |
| "r_90_Illegal nlowvt device nlowvt must not overlap npc" { |
| @ Illegal nlowvt device: nlowvt must not overlap npc |
| nlowvt AND npc |
| } |
| "r_91_Illegal nlowvt device nlowvt must not overlap polyres" { |
| @ Illegal nlowvt device: nlowvt must not overlap polyres |
| nlowvt AND polyres |
| } |
| "r_92_Illegal nlowvt device nlowvt must not overlap polycut" { |
| @ Illegal nlowvt device: nlowvt must not overlap polycut |
| nlowvt AND polycut |
| } |
| "r_93_Illegal nlowvt device nlowvt must not overlap li1res" { |
| @ Illegal nlowvt device: nlowvt must not overlap li1res |
| nlowvt AND li1res |
| } |
| "r_94_Illegal nlowvt device nlowvt must not overlap li1cut" { |
| @ Illegal nlowvt device: nlowvt must not overlap li1cut |
| nlowvt AND li1cut |
| } |
| "r_95_Illegal nlowvt device nlowvt must not overlap fuse" { |
| @ Illegal nlowvt device: nlowvt must not overlap fuse |
| nlowvt AND fuse |
| } |
| "r_96_Illegal nlowvt device nlowvt must not overlap psdm" { |
| @ Illegal nlowvt device: nlowvt must not overlap psdm |
| nlowvt AND psdm |
| } |
| "r_97_Illegal nlowvt device nlowvt must not overlap capacitor" { |
| @ Illegal nlowvt device: nlowvt must not overlap capacitor |
| nlowvt AND capacitor |
| } |
| "r_98_Illegal nlowvt device nlowvt must not overlap LVID" { |
| @ Illegal nlowvt device: nlowvt must not overlap LVID |
| nlowvt AND LVID |
| } |
| "r_99_Illegal nlowvt device nlowvt must not overlap ENID" { |
| @ Illegal nlowvt device: nlowvt must not overlap ENID |
| nlowvt AND ENID |
| } |
| "r_100_Illegal nlowvt device nlowvt must not overlap hvtp" { |
| @ Illegal nlowvt device: nlowvt must not overlap hvtp |
| nlowvt AND hvtp |
| } |
| "r_101_Illegal nlowvt device nlowvt must not overlap hvi" { |
| @ Illegal nlowvt device: nlowvt must not overlap hvi |
| nlowvt AND hvi |
| } |
| "r_102_Illegal nlowvt device nlowvt must not overlap pnp" { |
| @ Illegal nlowvt device: nlowvt must not overlap pnp |
| nlowvt AND pnp |
| } |
| "r_103_Illegal nlowvt device nlowvt must not overlap DiodeID" { |
| @ Illegal nlowvt device: nlowvt must not overlap DiodeID |
| nlowvt AND DiodeID |
| } |
| "r_104_Illegal nlowvt device nlowvt must not overlap COREID" { |
| @ Illegal nlowvt device: nlowvt must not overlap COREID |
| nlowvt AND COREID |
| } |
| "r_105_Illegal nlowvt device nlowvt must not overlap ESDID" { |
| @ Illegal nlowvt device: nlowvt must not overlap ESDID |
| nlowvt AND ESDID |
| } |
| "r_106_Illegal nlowvt device nlowvt must not overlap PHdiodeID" { |
| @ Illegal nlowvt device: nlowvt must not overlap PHdiodeID |
| nlowvt AND PHdiodeID |
| } |
| "r_107_Illegal nlowvt device nlowvt must not overlap ldntm" { |
| @ Illegal nlowvt device: nlowvt must not overlap ldntm |
| nlowvt AND ldntm |
| } |
| "r_108_Illegal sonos device sonos_e must not overlap ncm" { |
| @ Illegal sonos device: sonos_e must not overlap ncm |
| sonos_e AND ncm |
| } |
| "r_109_Illegal sonos device sonos_e must not overlap nwell" { |
| @ Illegal sonos device: sonos_e must not overlap nwell |
| sonos_e AND nwell |
| } |
| "r_110_Illegal sonos device sonos_e must not overlap tap" { |
| @ Illegal sonos device: sonos_e must not overlap tap |
| sonos_e AND tap |
| } |
| "r_111_Illegal sonos device sonos_e must not overlap diffres" { |
| @ Illegal sonos device: sonos_e must not overlap diffres |
| sonos_e AND diffres |
| } |
| "r_112_Illegal sonos device sonos_e must not overlap diffcut" { |
| @ Illegal sonos device: sonos_e must not overlap diffcut |
| sonos_e AND diffcut |
| } |
| "r_113_Illegal sonos device sonos_e must not overlap npc" { |
| @ Illegal sonos device: sonos_e must not overlap npc |
| sonos_e AND npc |
| } |
| "r_114_Illegal sonos device sonos_e must not overlap polyres" { |
| @ Illegal sonos device: sonos_e must not overlap polyres |
| sonos_e AND polyres |
| } |
| "r_115_Illegal sonos device sonos_e must not overlap polycut" { |
| @ Illegal sonos device: sonos_e must not overlap polycut |
| sonos_e AND polycut |
| } |
| "r_116_Illegal sonos device sonos_e must not overlap li1res" { |
| @ Illegal sonos device: sonos_e must not overlap li1res |
| sonos_e AND li1res |
| } |
| "r_117_Illegal sonos device sonos_e must not overlap li1cut" { |
| @ Illegal sonos device: sonos_e must not overlap li1cut |
| sonos_e AND li1cut |
| } |
| "r_118_Illegal sonos device sonos_e must not overlap fuse" { |
| @ Illegal sonos device: sonos_e must not overlap fuse |
| sonos_e AND fuse |
| } |
| "r_119_Illegal sonos device sonos_e must not overlap psdm" { |
| @ Illegal sonos device: sonos_e must not overlap psdm |
| sonos_e AND psdm |
| } |
| "r_120_Illegal sonos device sonos_e must not overlap capacitor" { |
| @ Illegal sonos device: sonos_e must not overlap capacitor |
| sonos_e AND capacitor |
| } |
| "r_121_Illegal sonos device sonos_e must not overlap LVID" { |
| @ Illegal sonos device: sonos_e must not overlap LVID |
| sonos_e AND LVID |
| } |
| "r_122_Illegal sonos device sonos_e must not overlap ENID" { |
| @ Illegal sonos device: sonos_e must not overlap ENID |
| sonos_e AND ENID |
| } |
| "r_123_Illegal sonos device sonos_e must not overlap hvtp" { |
| @ Illegal sonos device: sonos_e must not overlap hvtp |
| sonos_e AND hvtp |
| } |
| "r_124_Illegal sonos device sonos_e must not overlap hvi" { |
| @ Illegal sonos device: sonos_e must not overlap hvi |
| sonos_e AND hvi |
| } |
| "r_125_Illegal sonos device sonos_e must not overlap pnp" { |
| @ Illegal sonos device: sonos_e must not overlap pnp |
| sonos_e AND pnp |
| } |
| "r_126_Illegal sonos device sonos_e must not overlap DiodeID" { |
| @ Illegal sonos device: sonos_e must not overlap DiodeID |
| sonos_e AND DiodeID |
| } |
| "r_127_Illegal sonos device sonos_e must not overlap ESDID" { |
| @ Illegal sonos device: sonos_e must not overlap ESDID |
| sonos_e AND ESDID |
| } |
| "r_128_Illegal sonos device sonos_e must not overlap PHdiodeID" { |
| @ Illegal sonos device: sonos_e must not overlap PHdiodeID |
| sonos_e AND PHdiodeID |
| } |
| "r_129_Illegal nhv device nhv must not overlap ncm" { |
| @ Illegal nhv device: nhv must not overlap ncm |
| nhv AND ncm |
| } |
| "r_130_Illegal nhv device nhv must not overlap nwell" { |
| @ Illegal nhv device: nhv must not overlap nwell |
| nhv AND nwell |
| } |
| "r_131_Illegal nhv device nhv must not overlap tap" { |
| @ Illegal nhv device: nhv must not overlap tap |
| nhv AND tap |
| } |
| "r_132_Illegal nhv device nhv must not overlap tunm" { |
| @ Illegal nhv device: nhv must not overlap tunm |
| nhv AND tunm |
| } |
| "r_133_Illegal nhv device nhv must not overlap diffres" { |
| @ Illegal nhv device: nhv must not overlap diffres |
| nhv AND diffres |
| } |
| "r_134_Illegal nhv device nhv must not overlap diffcut" { |
| @ Illegal nhv device: nhv must not overlap diffcut |
| nhv AND diffcut |
| } |
| "r_135_Illegal nhv device nhv must not overlap npc" { |
| @ Illegal nhv device: nhv must not overlap npc |
| nhv AND npc |
| } |
| "r_136_Illegal nhv device nhv must not overlap polyres" { |
| @ Illegal nhv device: nhv must not overlap polyres |
| nhv AND polyres |
| } |
| "r_137_Illegal nhv device nhv must not overlap polycut" { |
| @ Illegal nhv device: nhv must not overlap polycut |
| nhv AND polycut |
| } |
| "r_138_Illegal nhv device nhv must not overlap li1res" { |
| @ Illegal nhv device: nhv must not overlap li1res |
| nhv AND li1res |
| } |
| "r_139_Illegal nhv device nhv must not overlap li1cut" { |
| @ Illegal nhv device: nhv must not overlap li1cut |
| nhv AND li1cut |
| } |
| "r_140_Illegal nhv device nhv must not overlap fuse" { |
| @ Illegal nhv device: nhv must not overlap fuse |
| nhv AND fuse |
| } |
| "r_141_Illegal nhv device nhv must not overlap psdm" { |
| @ Illegal nhv device: nhv must not overlap psdm |
| nhv AND psdm |
| } |
| "r_142_Illegal nhv device nhv must not overlap capacitor" { |
| @ Illegal nhv device: nhv must not overlap capacitor |
| nhv AND capacitor |
| } |
| "r_143_Illegal nhv device nhv must not overlap LVID" { |
| @ Illegal nhv device: nhv must not overlap LVID |
| nhv AND LVID |
| } |
| "r_144_Illegal nhv device nhv must not overlap ENID" { |
| @ Illegal nhv device: nhv must not overlap ENID |
| nhv AND ENID |
| } |
| "r_145_Illegal nhv device nhv must not overlap hvtp" { |
| @ Illegal nhv device: nhv must not overlap hvtp |
| nhv AND hvtp |
| } |
| "r_146_Illegal nhv device nhv must not overlap lvtn" { |
| @ Illegal nhv device: nhv must not overlap lvtn |
| nhv AND lvtn |
| } |
| "r_147_Illegal nhv device nhv must not overlap pnp" { |
| @ Illegal nhv device: nhv must not overlap pnp |
| nhv AND pnp |
| } |
| "r_148_Illegal nhv device nhv must not overlap DiodeID" { |
| @ Illegal nhv device: nhv must not overlap DiodeID |
| nhv AND DiodeID |
| } |
| "r_149_Illegal nhv device nhv must not overlap COREID" { |
| @ Illegal nhv device: nhv must not overlap COREID |
| nhv AND COREID |
| } |
| "r_150_Illegal nhv device nhv must not overlap PHdiodeID" { |
| @ Illegal nhv device: nhv must not overlap PHdiodeID |
| nhv AND PHdiodeID |
| } |
| "r_151_Illegal nhv device nhv must not overlap ldntm" { |
| @ Illegal nhv device: nhv must not overlap ldntm |
| nhv AND ldntm |
| } |
| "r_152_Illegal nhvnative device nhvnativeNoCap must not overlap ncm" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap ncm |
| nhvnativeNoCap AND ncm |
| } |
| "r_153_Illegal nhvnative device nhvnativeNoCap must not overlap nwell" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap nwell |
| nhvnativeNoCap AND nwell |
| } |
| "r_154_Illegal nhvnative device nhvnativeNoCap must not overlap tap" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap tap |
| nhvnativeNoCap AND tap |
| } |
| "r_155_Illegal nhvnative device nhvnativeNoCap must not overlap tunm" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap tunm |
| nhvnativeNoCap AND tunm |
| } |
| "r_156_Illegal nhvnative device nhvnativeNoCap must not overlap diffres" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap diffres |
| nhvnativeNoCap AND diffres |
| } |
| "r_157_Illegal nhvnative device nhvnativeNoCap must not overlap diffcut" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap diffcut |
| nhvnativeNoCap AND diffcut |
| } |
| "r_158_Illegal nhvnative device nhvnativeNoCap must not overlap npc" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap npc |
| nhvnativeNoCap AND npc |
| } |
| "r_159_Illegal nhvnative device nhvnativeNoCap must not overlap polyres" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap polyres |
| nhvnativeNoCap AND polyres |
| } |
| "r_160_Illegal nhvnative device nhvnativeNoCap must not overlap polycut" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap polycut |
| nhvnativeNoCap AND polycut |
| } |
| "r_161_Illegal nhvnative device nhvnativeNoCap must not overlap li1res" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap li1res |
| nhvnativeNoCap AND li1res |
| } |
| "r_162_Illegal nhvnative device nhvnativeNoCap must not overlap li1cut" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap li1cut |
| nhvnativeNoCap AND li1cut |
| } |
| "r_163_Illegal nhvnative device nhvnativeNoCap must not overlap fuse" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap fuse |
| nhvnativeNoCap AND fuse |
| } |
| "r_164_Illegal nhvnative device nhvnativeNoCap must not overlap psdm" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap psdm |
| nhvnativeNoCap AND psdm |
| } |
| "r_165_Illegal nhvnative device nhvnativeNoCap must not overlap capacitor" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap capacitor |
| nhvnativeNoCap AND capacitor |
| } |
| "r_166_Illegal nhvnative device nhvnativeNoCap must not overlap LVID" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap LVID |
| nhvnativeNoCap AND LVID |
| } |
| "r_167_Illegal nhvnative device nhvnativeNoCap must not overlap ENID" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap ENID |
| nhvnativeNoCap AND ENID |
| } |
| "r_168_Illegal nhvnative device nhvnativeNoCap must not overlap hvtp" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap hvtp |
| nhvnativeNoCap AND hvtp |
| } |
| "r_169_Illegal nhvnative device nhvnativeNoCap must not overlap pnp" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap pnp |
| nhvnativeNoCap AND pnp |
| } |
| "r_170_Illegal nhvnative device nhvnativeNoCap must not overlap DiodeID" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap DiodeID |
| nhvnativeNoCap AND DiodeID |
| } |
| "r_171_Illegal nhvnative device nhvnativeNoCap must not overlap COREID" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap COREID |
| nhvnativeNoCap AND COREID |
| } |
| "r_172_Illegal nhvnative device nhvnativeNoCap must not overlap ESDID" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap ESDID |
| nhvnativeNoCap AND ESDID |
| } |
| "r_173_Illegal nhvnative device nhvnativeNoCap must not overlap PHdiodeID" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap PHdiodeID |
| nhvnativeNoCap AND PHdiodeID |
| } |
| "r_174_Illegal nhvnative device nhvnativeNoCap must not overlap ldntm" { |
| @ Illegal nhvnative device: nhvnativeNoCap must not overlap ldntm |
| nhvnativeNoCap AND ldntm |
| } |
| "r_175_Illegal nhvnative device nhvnative10x4 must not overlap ncm" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap ncm |
| nhvnative10x4 AND ncm |
| } |
| "r_176_Illegal nhvnative device nhvnative10x4 must not overlap nwell" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap nwell |
| nhvnative10x4 AND nwell |
| } |
| "r_177_Illegal nhvnative device nhvnative10x4 must not overlap tap" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap tap |
| nhvnative10x4 AND tap |
| } |
| "r_178_Illegal nhvnative device nhvnative10x4 must not overlap tunm" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap tunm |
| nhvnative10x4 AND tunm |
| } |
| "r_179_Illegal nhvnative device nhvnative10x4 must not overlap diffres" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap diffres |
| nhvnative10x4 AND diffres |
| } |
| "r_180_Illegal nhvnative device nhvnative10x4 must not overlap diffcut" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap diffcut |
| nhvnative10x4 AND diffcut |
| } |
| "r_181_Illegal nhvnative device nhvnative10x4 must not overlap npc" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap npc |
| nhvnative10x4 AND npc |
| } |
| "r_182_Illegal nhvnative device nhvnative10x4 must not overlap polyres" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap polyres |
| nhvnative10x4 AND polyres |
| } |
| "r_183_Illegal nhvnative device nhvnative10x4 must not overlap polycut" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap polycut |
| nhvnative10x4 AND polycut |
| } |
| "r_184_Illegal nhvnative device nhvnative10x4 must not overlap li1res" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap li1res |
| nhvnative10x4 AND li1res |
| } |
| "r_185_Illegal nhvnative device nhvnative10x4 must not overlap li1cut" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap li1cut |
| nhvnative10x4 AND li1cut |
| } |
| "r_186_Illegal nhvnative device nhvnative10x4 must not overlap fuse" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap fuse |
| nhvnative10x4 AND fuse |
| } |
| "r_187_Illegal nhvnative device nhvnative10x4 must not overlap psdm" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap psdm |
| nhvnative10x4 AND psdm |
| } |
| "r_188_Illegal nhvnative device nhvnative10x4 must not overlap LVID" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap LVID |
| nhvnative10x4 AND LVID |
| } |
| "r_189_Illegal nhvnative device nhvnative10x4 must not overlap ENID" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap ENID |
| nhvnative10x4 AND ENID |
| } |
| "r_190_Illegal nhvnative device nhvnative10x4 must not overlap hvtp" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap hvtp |
| nhvnative10x4 AND hvtp |
| } |
| "r_191_Illegal nhvnative device nhvnative10x4 must not overlap pnp" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap pnp |
| nhvnative10x4 AND pnp |
| } |
| "r_192_Illegal nhvnative device nhvnative10x4 must not overlap DiodeID" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap DiodeID |
| nhvnative10x4 AND DiodeID |
| } |
| "r_193_Illegal nhvnative device nhvnative10x4 must not overlap COREID" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap COREID |
| nhvnative10x4 AND COREID |
| } |
| "r_194_Illegal nhvnative device nhvnative10x4 must not overlap ESDID" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap ESDID |
| nhvnative10x4 AND ESDID |
| } |
| "r_195_Illegal nhvnative device nhvnative10x4 must not overlap PHdiodeID" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap PHdiodeID |
| nhvnative10x4 AND PHdiodeID |
| } |
| "r_196_Illegal nhvnative device nhvnative10x4 must not overlap ldntm" { |
| @ Illegal nhvnative device: nhvnative10x4 must not overlap ldntm |
| nhvnative10x4 AND ldntm |
| } |
| "r_197_Illegal ntvnative device ntvnative must not overlap ncm" { |
| @ Illegal ntvnative device: ntvnative must not overlap ncm |
| ntvnative AND ncm |
| } |
| "r_198_Illegal ntvnative device ntvnative must not overlap nwell" { |
| @ Illegal ntvnative device: ntvnative must not overlap nwell |
| ntvnative AND nwell |
| } |
| "r_199_Illegal ntvnative device ntvnative must not overlap tap" { |
| @ Illegal ntvnative device: ntvnative must not overlap tap |
| ntvnative AND tap |
| } |
| "r_200_Illegal ntvnative device ntvnative must not overlap tunm" { |
| @ Illegal ntvnative device: ntvnative must not overlap tunm |
| ntvnative AND tunm |
| } |
| "r_201_Illegal ntvnative device ntvnative must not overlap diffres" { |
| @ Illegal ntvnative device: ntvnative must not overlap diffres |
| ntvnative AND diffres |
| } |
| "r_202_Illegal ntvnative device ntvnative must not overlap diffcut" { |
| @ Illegal ntvnative device: ntvnative must not overlap diffcut |
| ntvnative AND diffcut |
| } |
| "r_203_Illegal ntvnative device ntvnative must not overlap npc" { |
| @ Illegal ntvnative device: ntvnative must not overlap npc |
| ntvnative AND npc |
| } |
| "r_204_Illegal ntvnative device ntvnative must not overlap polyres" { |
| @ Illegal ntvnative device: ntvnative must not overlap polyres |
| ntvnative AND polyres |
| } |
| "r_205_Illegal ntvnative device ntvnative must not overlap polycut" { |
| @ Illegal ntvnative device: ntvnative must not overlap polycut |
| ntvnative AND polycut |
| } |
| "r_206_Illegal ntvnative device ntvnative must not overlap li1res" { |
| @ Illegal ntvnative device: ntvnative must not overlap li1res |
| ntvnative AND li1res |
| } |
| "r_207_Illegal ntvnative device ntvnative must not overlap li1cut" { |
| @ Illegal ntvnative device: ntvnative must not overlap li1cut |
| ntvnative AND li1cut |
| } |
| "r_208_Illegal ntvnative device ntvnative must not overlap fuse" { |
| @ Illegal ntvnative device: ntvnative must not overlap fuse |
| ntvnative AND fuse |
| } |
| "r_209_Illegal ntvnative device ntvnative must not overlap psdm" { |
| @ Illegal ntvnative device: ntvnative must not overlap psdm |
| ntvnative AND psdm |
| } |
| "r_210_Illegal ntvnative device ntvnative must not overlap capacitor" { |
| @ Illegal ntvnative device: ntvnative must not overlap capacitor |
| ntvnative AND capacitor |
| } |
| "r_211_Illegal ntvnative device ntvnative must not overlap ENID" { |
| @ Illegal ntvnative device: ntvnative must not overlap ENID |
| ntvnative AND ENID |
| } |
| "r_212_Illegal ntvnative device ntvnative must not overlap hvtp" { |
| @ Illegal ntvnative device: ntvnative must not overlap hvtp |
| ntvnative AND hvtp |
| } |
| "r_213_Illegal ntvnative device ntvnative must not overlap pnp" { |
| @ Illegal ntvnative device: ntvnative must not overlap pnp |
| ntvnative AND pnp |
| } |
| "r_214_Illegal ntvnative device ntvnative must not overlap DiodeID" { |
| @ Illegal ntvnative device: ntvnative must not overlap DiodeID |
| ntvnative AND DiodeID |
| } |
| "r_215_Illegal ntvnative device ntvnative must not overlap COREID" { |
| @ Illegal ntvnative device: ntvnative must not overlap COREID |
| ntvnative AND COREID |
| } |
| "r_216_Illegal ntvnative device ntvnative must not overlap ESDID" { |
| @ Illegal ntvnative device: ntvnative must not overlap ESDID |
| ntvnative AND ESDID |
| } |
| "r_217_Illegal ntvnative device ntvnative must not overlap PHdiodeID" { |
| @ Illegal ntvnative device: ntvnative must not overlap PHdiodeID |
| ntvnative AND PHdiodeID |
| } |
| "r_218_Illegal ntvnative device ntvnative must not overlap ldntm" { |
| @ Illegal ntvnative device: ntvnative must not overlap ldntm |
| ntvnative AND ldntm |
| } |
| "r_219_Illegal fnpass device fnpass must not overlap ncm" { |
| @ Illegal fnpass device: fnpass must not overlap ncm |
| fnpass AND ncm |
| } |
| "r_220_Illegal fnpass device fnpass must not overlap nwell" { |
| @ Illegal fnpass device: fnpass must not overlap nwell |
| fnpass AND nwell |
| } |
| "r_221_Illegal fnpass device fnpass must not overlap tap" { |
| @ Illegal fnpass device: fnpass must not overlap tap |
| fnpass AND tap |
| } |
| "r_222_Illegal fnpass device fnpass must not overlap tunm" { |
| @ Illegal fnpass device: fnpass must not overlap tunm |
| fnpass AND tunm |
| } |
| "r_223_Illegal fnpass device fnpass must not overlap diffres" { |
| @ Illegal fnpass device: fnpass must not overlap diffres |
| fnpass AND diffres |
| } |
| "r_224_Illegal fnpass device fnpass must not overlap diffcut" { |
| @ Illegal fnpass device: fnpass must not overlap diffcut |
| fnpass AND diffcut |
| } |
| "r_225_Illegal fnpass device fnpass must not overlap npc" { |
| @ Illegal fnpass device: fnpass must not overlap npc |
| fnpass AND npc |
| } |
| "r_226_Illegal fnpass device fnpass must not overlap polyres" { |
| @ Illegal fnpass device: fnpass must not overlap polyres |
| fnpass AND polyres |
| } |
| "r_227_Illegal fnpass device fnpass must not overlap polycut" { |
| @ Illegal fnpass device: fnpass must not overlap polycut |
| fnpass AND polycut |
| } |
| "r_228_Illegal fnpass device fnpass must not overlap li1res" { |
| @ Illegal fnpass device: fnpass must not overlap li1res |
| fnpass AND li1res |
| } |
| "r_229_Illegal fnpass device fnpass must not overlap li1cut" { |
| @ Illegal fnpass device: fnpass must not overlap li1cut |
| fnpass AND li1cut |
| } |
| "r_230_Illegal fnpass device fnpass must not overlap fuse" { |
| @ Illegal fnpass device: fnpass must not overlap fuse |
| fnpass AND fuse |
| } |
| "r_231_Illegal fnpass device fnpass must not overlap capacitor" { |
| @ Illegal fnpass device: fnpass must not overlap capacitor |
| fnpass AND capacitor |
| } |
| "r_232_Illegal fnpass device fnpass must not overlap LVID" { |
| @ Illegal fnpass device: fnpass must not overlap LVID |
| fnpass AND LVID |
| } |
| "r_233_Illegal fnpass device fnpass must not overlap ENID" { |
| @ Illegal fnpass device: fnpass must not overlap ENID |
| fnpass AND ENID |
| } |
| "r_234_Illegal fnpass device fnpass must not overlap hvtp" { |
| @ Illegal fnpass device: fnpass must not overlap hvtp |
| fnpass AND hvtp |
| } |
| "r_235_Illegal fnpass device fnpass must not overlap pnp" { |
| @ Illegal fnpass device: fnpass must not overlap pnp |
| fnpass AND pnp |
| } |
| "r_236_Illegal fnpass device fnpass must not overlap DiodeID" { |
| @ Illegal fnpass device: fnpass must not overlap DiodeID |
| fnpass AND DiodeID |
| } |
| "r_237_Illegal fnpass device fnpass must not overlap ESDID" { |
| @ Illegal fnpass device: fnpass must not overlap ESDID |
| fnpass AND ESDID |
| } |
| "r_238_Illegal fnpass device fnpass must not overlap PHdiodeID" { |
| @ Illegal fnpass device: fnpass must not overlap PHdiodeID |
| fnpass AND PHdiodeID |
| } |
| "r_239_Illegal fnpass device fnpass must not overlap lvtn" { |
| @ Illegal fnpass device: fnpass must not overlap lvtn |
| fnpass AND lvtn |
| } |
| "r_240_Illegal nhvesd device nhvesd must not overlap ncm" { |
| @ Illegal nhvesd device: nhvesd must not overlap ncm |
| nhvesd AND ncm |
| } |
| "r_241_Illegal nhvesd device nhvesd must not overlap nwell" { |
| @ Illegal nhvesd device: nhvesd must not overlap nwell |
| nhvesd AND nwell |
| } |
| "r_242_Illegal nhvesd device nhvesd must not overlap tap" { |
| @ Illegal nhvesd device: nhvesd must not overlap tap |
| nhvesd AND tap |
| } |
| "r_243_Illegal nhvesd device nhvesd must not overlap tunm" { |
| @ Illegal nhvesd device: nhvesd must not overlap tunm |
| nhvesd AND tunm |
| } |
| "r_244_Illegal nhvesd device nhvesd must not overlap diffres" { |
| @ Illegal nhvesd device: nhvesd must not overlap diffres |
| nhvesd AND diffres |
| } |
| "r_245_Illegal nhvesd device nhvesd must not overlap diffcut" { |
| @ Illegal nhvesd device: nhvesd must not overlap diffcut |
| nhvesd AND diffcut |
| } |
| "r_246_Illegal nhvesd device nhvesd must not overlap npc" { |
| @ Illegal nhvesd device: nhvesd must not overlap npc |
| nhvesd AND npc |
| } |
| "r_247_Illegal nhvesd device nhvesd must not overlap polyres" { |
| @ Illegal nhvesd device: nhvesd must not overlap polyres |
| nhvesd AND polyres |
| } |
| "r_248_Illegal nhvesd device nhvesd must not overlap polycut" { |
| @ Illegal nhvesd device: nhvesd must not overlap polycut |
| nhvesd AND polycut |
| } |
| "r_249_Illegal nhvesd device nhvesd must not overlap li1res" { |
| @ Illegal nhvesd device: nhvesd must not overlap li1res |
| nhvesd AND li1res |
| } |
| "r_250_Illegal nhvesd device nhvesd must not overlap li1cut" { |
| @ Illegal nhvesd device: nhvesd must not overlap li1cut |
| nhvesd AND li1cut |
| } |
| "r_251_Illegal nhvesd device nhvesd must not overlap fuse" { |
| @ Illegal nhvesd device: nhvesd must not overlap fuse |
| nhvesd AND fuse |
| } |
| "r_252_Illegal nhvesd device nhvesd must not overlap psdm" { |
| @ Illegal nhvesd device: nhvesd must not overlap psdm |
| nhvesd AND psdm |
| } |
| "r_253_Illegal nhvesd device nhvesd must not overlap capacitor" { |
| @ Illegal nhvesd device: nhvesd must not overlap capacitor |
| nhvesd AND capacitor |
| } |
| "r_254_Illegal nhvesd device nhvesd must not overlap LVID" { |
| @ Illegal nhvesd device: nhvesd must not overlap LVID |
| nhvesd AND LVID |
| } |
| "r_255_Illegal nhvesd device nhvesd must not overlap ENID" { |
| @ Illegal nhvesd device: nhvesd must not overlap ENID |
| nhvesd AND ENID |
| } |
| "r_256_Illegal nhvesd device nhvesd must not overlap hvtp" { |
| @ Illegal nhvesd device: nhvesd must not overlap hvtp |
| nhvesd AND hvtp |
| } |
| "r_257_Illegal nhvesd device nhvesd must not overlap lvtn" { |
| @ Illegal nhvesd device: nhvesd must not overlap lvtn |
| nhvesd AND lvtn |
| } |
| "r_258_Illegal nhvesd device nhvesd must not overlap pnp" { |
| @ Illegal nhvesd device: nhvesd must not overlap pnp |
| nhvesd AND pnp |
| } |
| "r_259_Illegal nhvesd device nhvesd must not overlap DiodeID" { |
| @ Illegal nhvesd device: nhvesd must not overlap DiodeID |
| nhvesd AND DiodeID |
| } |
| "r_260_Illegal nhvesd device nhvesd must not overlap COREID" { |
| @ Illegal nhvesd device: nhvesd must not overlap COREID |
| nhvesd AND COREID |
| } |
| "r_261_Illegal nhvesd device nhvesd must not overlap PHdiodeID" { |
| @ Illegal nhvesd device: nhvesd must not overlap PHdiodeID |
| nhvesd AND PHdiodeID |
| } |
| "r_262_Illegal nhvesd device nhvesd must not overlap ldntm" { |
| @ Illegal nhvesd device: nhvesd must not overlap ldntm |
| nhvesd AND ldntm |
| } |
| "r_263_Illegal nhvnativeesd device nhvnativeesd must not overlap ncm" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap ncm |
| nhvnativeesd AND ncm |
| } |
| "r_264_Illegal nhvnativeesd device nhvnativeesd must not overlap nwell" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap nwell |
| nhvnativeesd AND nwell |
| } |
| "r_265_Illegal nhvnativeesd device nhvnativeesd must not overlap tap" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap tap |
| nhvnativeesd AND tap |
| } |
| "r_266_Illegal nhvnativeesd device nhvnativeesd must not overlap tunm" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap tunm |
| nhvnativeesd AND tunm |
| } |
| "r_267_Illegal nhvnativeesd device nhvnativeesd must not overlap diffres" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap diffres |
| nhvnativeesd AND diffres |
| } |
| "r_268_Illegal nhvnativeesd device nhvnativeesd must not overlap diffcut" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap diffcut |
| nhvnativeesd AND diffcut |
| } |
| "r_269_Illegal nhvnativeesd device nhvnativeesd must not overlap npc" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap npc |
| nhvnativeesd AND npc |
| } |
| "r_270_Illegal nhvnativeesd device nhvnativeesd must not overlap polyres" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap polyres |
| nhvnativeesd AND polyres |
| } |
| "r_271_Illegal nhvnativeesd device nhvnativeesd must not overlap polycut" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap polycut |
| nhvnativeesd AND polycut |
| } |
| "r_272_Illegal nhvnativeesd device nhvnativeesd must not overlap li1res" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap li1res |
| nhvnativeesd AND li1res |
| } |
| "r_273_Illegal nhvnativeesd device nhvnativeesd must not overlap li1cut" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap li1cut |
| nhvnativeesd AND li1cut |
| } |
| "r_274_Illegal nhvnativeesd device nhvnativeesd must not overlap fuse" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap fuse |
| nhvnativeesd AND fuse |
| } |
| "r_275_Illegal nhvnativeesd device nhvnativeesd must not overlap psdm" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap psdm |
| nhvnativeesd AND psdm |
| } |
| "r_276_Illegal nhvnativeesd device nhvnativeesd must not overlap capacitor" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap capacitor |
| nhvnativeesd AND capacitor |
| } |
| "r_277_Illegal nhvnativeesd device nhvnativeesd must not overlap LVID" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap LVID |
| nhvnativeesd AND LVID |
| } |
| "r_278_Illegal nhvnativeesd device nhvnativeesd must not overlap ENID" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap ENID |
| nhvnativeesd AND ENID |
| } |
| "r_279_Illegal nhvnativeesd device nhvnativeesd must not overlap hvtp" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap hvtp |
| nhvnativeesd AND hvtp |
| } |
| "r_280_Illegal nhvnativeesd device nhvnativeesd must not overlap pnp" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap pnp |
| nhvnativeesd AND pnp |
| } |
| "r_281_Illegal nhvnativeesd device nhvnativeesd must not overlap DiodeID" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap DiodeID |
| nhvnativeesd AND DiodeID |
| } |
| "r_282_Illegal nhvnativeesd device nhvnativeesd must not overlap COREID" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap COREID |
| nhvnativeesd AND COREID |
| } |
| "r_283_Illegal nhvnativeesd device nhvnativeesd must not overlap PHdiodeID" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap PHdiodeID |
| nhvnativeesd AND PHdiodeID |
| } |
| "r_284_Illegal nhvnativeesd device nhvnativeesd must not overlap ldntm" { |
| @ Illegal nhvnativeesd device: nhvnativeesd must not overlap ldntm |
| nhvnativeesd AND ldntm |
| } |
| "r_285_Illegal nshortesd device nshortesd must not overlap ncm" { |
| @ Illegal nshortesd device: nshortesd must not overlap ncm |
| nshortesd AND ncm |
| } |
| "r_286_Illegal nshortesd device nshortesd must not overlap nwell" { |
| @ Illegal nshortesd device: nshortesd must not overlap nwell |
| nshortesd AND nwell |
| } |
| "r_287_Illegal nshortesd device nshortesd must not overlap tap" { |
| @ Illegal nshortesd device: nshortesd must not overlap tap |
| nshortesd AND tap |
| } |
| "r_288_Illegal nshortesd device nshortesd must not overlap tunm" { |
| @ Illegal nshortesd device: nshortesd must not overlap tunm |
| nshortesd AND tunm |
| } |
| "r_289_Illegal nshortesd device nshortesd must not overlap diffres" { |
| @ Illegal nshortesd device: nshortesd must not overlap diffres |
| nshortesd AND diffres |
| } |
| "r_290_Illegal nshortesd device nshortesd must not overlap diffcut" { |
| @ Illegal nshortesd device: nshortesd must not overlap diffcut |
| nshortesd AND diffcut |
| } |
| "r_291_Illegal nshortesd device nshortesd must not overlap npc" { |
| @ Illegal nshortesd device: nshortesd must not overlap npc |
| nshortesd AND npc |
| } |
| "r_292_Illegal nshortesd device nshortesd must not overlap polyres" { |
| @ Illegal nshortesd device: nshortesd must not overlap polyres |
| nshortesd AND polyres |
| } |
| "r_293_Illegal nshortesd device nshortesd must not overlap polycut" { |
| @ Illegal nshortesd device: nshortesd must not overlap polycut |
| nshortesd AND polycut |
| } |
| "r_294_Illegal nshortesd device nshortesd must not overlap li1res" { |
| @ Illegal nshortesd device: nshortesd must not overlap li1res |
| nshortesd AND li1res |
| } |
| "r_295_Illegal nshortesd device nshortesd must not overlap li1cut" { |
| @ Illegal nshortesd device: nshortesd must not overlap li1cut |
| nshortesd AND li1cut |
| } |
| "r_296_Illegal nshortesd device nshortesd must not overlap fuse" { |
| @ Illegal nshortesd device: nshortesd must not overlap fuse |
| nshortesd AND fuse |
| } |
| "r_297_Illegal nshortesd device nshortesd must not overlap psdm" { |
| @ Illegal nshortesd device: nshortesd must not overlap psdm |
| nshortesd AND psdm |
| } |
| "r_298_Illegal nshortesd device nshortesd must not overlap capacitor" { |
| @ Illegal nshortesd device: nshortesd must not overlap capacitor |
| nshortesd AND capacitor |
| } |
| "r_299_Illegal nshortesd device nshortesd must not overlap LVID" { |
| @ Illegal nshortesd device: nshortesd must not overlap LVID |
| nshortesd AND LVID |
| } |
| "r_300_Illegal nshortesd device nshortesd must not overlap ENID" { |
| @ Illegal nshortesd device: nshortesd must not overlap ENID |
| nshortesd AND ENID |
| } |
| "r_301_Illegal nshortesd device nshortesd must not overlap hvtp" { |
| @ Illegal nshortesd device: nshortesd must not overlap hvtp |
| nshortesd AND hvtp |
| } |
| "r_302_Illegal nshortesd device nshortesd must not overlap lvtn" { |
| @ Illegal nshortesd device: nshortesd must not overlap lvtn |
| nshortesd AND lvtn |
| } |
| "r_303_Illegal nshortesd device nshortesd must not overlap hvi" { |
| @ Illegal nshortesd device: nshortesd must not overlap hvi |
| nshortesd AND hvi |
| } |
| "r_304_Illegal nshortesd device nshortesd must not overlap pnp" { |
| @ Illegal nshortesd device: nshortesd must not overlap pnp |
| nshortesd AND pnp |
| } |
| "r_305_Illegal nshortesd device nshortesd must not overlap DiodeID" { |
| @ Illegal nshortesd device: nshortesd must not overlap DiodeID |
| nshortesd AND DiodeID |
| } |
| "r_306_Illegal nshortesd device nshortesd must not overlap COREID" { |
| @ Illegal nshortesd device: nshortesd must not overlap COREID |
| nshortesd AND COREID |
| } |
| "r_307_Illegal nshortesd device nshortesd must not overlap PHdiodeID" { |
| @ Illegal nshortesd device: nshortesd must not overlap PHdiodeID |
| nshortesd AND PHdiodeID |
| } |
| "r_308_Illegal nshortesd device nshortesd must not overlap ldntm" { |
| @ Illegal nshortesd device: nshortesd must not overlap ldntm |
| nshortesd AND ldntm |
| } |
| "r_309_Illegal xcnwvc device xcnwvc must not overlap ncm" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap ncm |
| xcnwvc AND ncm |
| } |
| "r_310_Illegal xcnwvc device xcnwvc must not overlap tunm" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap tunm |
| xcnwvc AND tunm |
| } |
| "r_311_Illegal xcnwvc device xcnwvc must not overlap diff" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap diff |
| xcnwvc AND diff |
| } |
| "r_312_Illegal xcnwvc device xcnwvc must not overlap diffres" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap diffres |
| xcnwvc AND diffres |
| } |
| "r_313_Illegal xcnwvc device xcnwvc must not overlap diffcut" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap diffcut |
| xcnwvc AND diffcut |
| } |
| "r_314_Illegal xcnwvc device xcnwvc must not overlap npc" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap npc |
| xcnwvc AND npc |
| } |
| "r_315_Illegal xcnwvc device xcnwvc must not overlap polyres" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap polyres |
| xcnwvc AND polyres |
| } |
| "r_316_Illegal xcnwvc device xcnwvc must not overlap polycut" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap polycut |
| xcnwvc AND polycut |
| } |
| "r_317_Illegal xcnwvc device xcnwvc must not overlap li1res" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap li1res |
| xcnwvc AND li1res |
| } |
| "r_318_Illegal xcnwvc device xcnwvc must not overlap li1cut" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap li1cut |
| xcnwvc AND li1cut |
| } |
| "r_319_Illegal xcnwvc device xcnwvc must not overlap fuse" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap fuse |
| xcnwvc AND fuse |
| } |
| "r_320_Illegal xcnwvc device xcnwvc must not overlap psdm" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap psdm |
| xcnwvc AND psdm |
| } |
| "r_321_Illegal xcnwvc device xcnwvc must not overlap capacitor" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap capacitor |
| xcnwvc AND capacitor |
| } |
| "r_322_Illegal xcnwvc device xcnwvc must not overlap LVID" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap LVID |
| xcnwvc AND LVID |
| } |
| "r_323_Illegal xcnwvc device xcnwvc must not overlap ENID" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap ENID |
| xcnwvc AND ENID |
| } |
| "r_324_Illegal xcnwvc device xcnwvc must not overlap hvtp" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap hvtp |
| xcnwvc AND hvtp |
| } |
| "r_325_Illegal xcnwvc device xcnwvc must not overlap hvi" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap hvi |
| xcnwvc AND hvi |
| } |
| "r_326_Illegal xcnwvc device xcnwvc must not overlap pnp" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap pnp |
| xcnwvc AND pnp |
| } |
| "r_327_Illegal xcnwvc device xcnwvc must not overlap DiodeID" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap DiodeID |
| xcnwvc AND DiodeID |
| } |
| "r_328_Illegal xcnwvc device xcnwvc must not overlap ESDID" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap ESDID |
| xcnwvc AND ESDID |
| } |
| "r_329_Illegal xcnwvc device xcnwvc must not overlap COREID" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap COREID |
| xcnwvc AND COREID |
| } |
| "r_330_Illegal xcnwvc device xcnwvc must not overlap PHdiodeID" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap PHdiodeID |
| xcnwvc AND PHdiodeID |
| } |
| "r_331_Illegal xcnwvc device xcnwvc must not overlap ldntm" { |
| @ Illegal xcnwvc device: xcnwvc must not overlap ldntm |
| xcnwvc AND ldntm |
| } |
| "r_332_Illegal xcnwvc2 device xcnwvc2 must not overlap tunm" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap tunm |
| xcnwvc2 AND tunm |
| } |
| "r_333_Illegal xcnwvc2 device xcnwvc2 must not overlap diff" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap diff |
| xcnwvc2 AND diff |
| } |
| "r_334_Illegal xcnwvc2 device xcnwvc2 must not overlap diffres" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap diffres |
| xcnwvc2 AND diffres |
| } |
| "r_335_Illegal xcnwvc2 device xcnwvc2 must not overlap diffcut" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap diffcut |
| xcnwvc2 AND diffcut |
| } |
| "r_336_Illegal xcnwvc2 device xcnwvc2 must not overlap npc" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap npc |
| xcnwvc2 AND npc |
| } |
| "r_337_Illegal xcnwvc2 device xcnwvc2 must not overlap polyres" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap polyres |
| xcnwvc2 AND polyres |
| } |
| "r_338_Illegal xcnwvc2 device xcnwvc2 must not overlap polycut" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap polycut |
| xcnwvc2 AND polycut |
| } |
| "r_339_Illegal xcnwvc2 device xcnwvc2 must not overlap li1res" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap li1res |
| xcnwvc2 AND li1res |
| } |
| "r_340_Illegal xcnwvc2 device xcnwvc2 must not overlap li1cut" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap li1cut |
| xcnwvc2 AND li1cut |
| } |
| "r_341_Illegal xcnwvc2 device xcnwvc2 must not overlap fuse" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap fuse |
| xcnwvc2 AND fuse |
| } |
| "r_342_Illegal xcnwvc2 device xcnwvc2 must not overlap psdm" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap psdm |
| xcnwvc2 AND psdm |
| } |
| "r_343_Illegal xcnwvc2 device xcnwvc2 must not overlap capacitor" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap capacitor |
| xcnwvc2 AND capacitor |
| } |
| "r_344_Illegal xcnwvc2 device xcnwvc2 must not overlap LVID" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap LVID |
| xcnwvc2 AND LVID |
| } |
| "r_345_Illegal xcnwvc2 device xcnwvc2 must not overlap ENID" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap ENID |
| xcnwvc2 AND ENID |
| } |
| "r_346_Illegal xcnwvc2 device xcnwvc2 must not overlap hvi" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap hvi |
| xcnwvc2 AND hvi |
| } |
| "r_347_Illegal xcnwvc2 device xcnwvc2 must not overlap pnp" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap pnp |
| xcnwvc2 AND pnp |
| } |
| "r_348_Illegal xcnwvc2 device xcnwvc2 must not overlap DiodeID" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap DiodeID |
| xcnwvc2 AND DiodeID |
| } |
| "r_349_Illegal xcnwvc2 device xcnwvc2 must not overlap ESDID" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap ESDID |
| xcnwvc2 AND ESDID |
| } |
| "r_350_Illegal xcnwvc2 device xcnwvc2 must not overlap COREID" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap COREID |
| xcnwvc2 AND COREID |
| } |
| "r_351_Illegal xcnwvc2 device xcnwvc2 must not overlap PHdiodeID" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap PHdiodeID |
| xcnwvc2 AND PHdiodeID |
| } |
| "r_352_Illegal xcnwvc2 device xcnwvc2 must not overlap ldntm" { |
| @ Illegal xcnwvc2 device: xcnwvc2 must not overlap ldntm |
| xcnwvc2 AND ldntm |
| } |
| "r_353_Illegal pshort device pshortNoCap must not overlap tap" { |
| @ Illegal pshort device: pshortNoCap must not overlap tap |
| pshortNoCap AND tap |
| } |
| "r_354_Illegal pshort device pshortNoCap must not overlap tunm" { |
| @ Illegal pshort device: pshortNoCap must not overlap tunm |
| pshortNoCap AND tunm |
| } |
| "r_355_Illegal pshort device pshortNoCap must not overlap diffres" { |
| @ Illegal pshort device: pshortNoCap must not overlap diffres |
| pshortNoCap AND diffres |
| } |
| "r_356_Illegal pshort device pshortNoCap must not overlap diffcut" { |
| @ Illegal pshort device: pshortNoCap must not overlap diffcut |
| pshortNoCap AND diffcut |
| } |
| "r_357_Illegal pshort device pshortNoCap must not overlap npc" { |
| @ Illegal pshort device: pshortNoCap must not overlap npc |
| pshortNoCap AND npc |
| } |
| "r_358_Illegal pshort device pshortNoCap must not overlap polyres" { |
| @ Illegal pshort device: pshortNoCap must not overlap polyres |
| pshortNoCap AND polyres |
| } |
| "r_359_Illegal pshort device pshortNoCap must not overlap polycut" { |
| @ Illegal pshort device: pshortNoCap must not overlap polycut |
| pshortNoCap AND polycut |
| } |
| "r_360_Illegal pshort device pshortNoCap must not overlap li1res" { |
| @ Illegal pshort device: pshortNoCap must not overlap li1res |
| pshortNoCap AND li1res |
| } |
| "r_361_Illegal pshort device pshortNoCap must not overlap li1cut" { |
| @ Illegal pshort device: pshortNoCap must not overlap li1cut |
| pshortNoCap AND li1cut |
| } |
| "r_362_Illegal pshort device pshortNoCap must not overlap fuse" { |
| @ Illegal pshort device: pshortNoCap must not overlap fuse |
| pshortNoCap AND fuse |
| } |
| "r_363_Illegal pshort device pshortNoCap must not overlap nsdm" { |
| @ Illegal pshort device: pshortNoCap must not overlap nsdm |
| pshortNoCap AND nsdm |
| } |
| "r_364_Illegal pshort device pshortNoCap must not overlap capacitor" { |
| @ Illegal pshort device: pshortNoCap must not overlap capacitor |
| pshortNoCap AND capacitor |
| } |
| "r_365_Illegal pshort device pshortNoCap must not overlap LVID" { |
| @ Illegal pshort device: pshortNoCap must not overlap LVID |
| pshortNoCap AND LVID |
| } |
| "r_366_Illegal pshort device pshortNoCap must not overlap ENID" { |
| @ Illegal pshort device: pshortNoCap must not overlap ENID |
| pshortNoCap AND ENID |
| } |
| "r_367_Illegal pshort device pshortNoCap must not overlap lvtn" { |
| @ Illegal pshort device: pshortNoCap must not overlap lvtn |
| pshortNoCap AND lvtn |
| } |
| "r_368_Illegal pshort device pshortNoCap must not overlap hvi" { |
| @ Illegal pshort device: pshortNoCap must not overlap hvi |
| pshortNoCap AND hvi |
| } |
| "r_369_Illegal pshort device pshortNoCap must not overlap pnp" { |
| @ Illegal pshort device: pshortNoCap must not overlap pnp |
| pshortNoCap AND pnp |
| } |
| "r_370_Illegal pshort device pshortNoCap must not overlap DiodeID" { |
| @ Illegal pshort device: pshortNoCap must not overlap DiodeID |
| pshortNoCap AND DiodeID |
| } |
| "r_371_Illegal pshort device pshortNoCap must not overlap COREID" { |
| @ Illegal pshort device: pshortNoCap must not overlap COREID |
| pshortNoCap AND COREID |
| } |
| "r_372_Illegal pshort device pshortNoCap must not overlap PHdiodeID" { |
| @ Illegal pshort device: pshortNoCap must not overlap PHdiodeID |
| pshortNoCap AND PHdiodeID |
| } |
| "r_373_Illegal pshort device pshortNoCap must not overlap ldntm" { |
| @ Illegal pshort device: pshortNoCap must not overlap ldntm |
| pshortNoCap AND ldntm |
| } |
| "r_374_Illegal pshort device pshort5x4 must not overlap tap" { |
| @ Illegal pshort device: pshort5x4 must not overlap tap |
| pshort5x4 AND tap |
| } |
| "r_375_Illegal pshort device pshort5x4 must not overlap tunm" { |
| @ Illegal pshort device: pshort5x4 must not overlap tunm |
| pshort5x4 AND tunm |
| } |
| "r_376_Illegal pshort device pshort5x4 must not overlap diffres" { |
| @ Illegal pshort device: pshort5x4 must not overlap diffres |
| pshort5x4 AND diffres |
| } |
| "r_377_Illegal pshort device pshort5x4 must not overlap diffcut" { |
| @ Illegal pshort device: pshort5x4 must not overlap diffcut |
| pshort5x4 AND diffcut |
| } |
| "r_378_Illegal pshort device pshort5x4 must not overlap npc" { |
| @ Illegal pshort device: pshort5x4 must not overlap npc |
| pshort5x4 AND npc |
| } |
| "r_379_Illegal pshort device pshort5x4 must not overlap polyres" { |
| @ Illegal pshort device: pshort5x4 must not overlap polyres |
| pshort5x4 AND polyres |
| } |
| "r_380_Illegal pshort device pshort5x4 must not overlap polycut" { |
| @ Illegal pshort device: pshort5x4 must not overlap polycut |
| pshort5x4 AND polycut |
| } |
| "r_381_Illegal pshort device pshort5x4 must not overlap li1res" { |
| @ Illegal pshort device: pshort5x4 must not overlap li1res |
| pshort5x4 AND li1res |
| } |
| "r_382_Illegal pshort device pshort5x4 must not overlap li1cut" { |
| @ Illegal pshort device: pshort5x4 must not overlap li1cut |
| pshort5x4 AND li1cut |
| } |
| "r_383_Illegal pshort device pshort5x4 must not overlap fuse" { |
| @ Illegal pshort device: pshort5x4 must not overlap fuse |
| pshort5x4 AND fuse |
| } |
| "r_384_Illegal pshort device pshort5x4 must not overlap nsdm" { |
| @ Illegal pshort device: pshort5x4 must not overlap nsdm |
| pshort5x4 AND nsdm |
| } |
| "r_385_Illegal pshort device pshort5x4 must not overlap LVID" { |
| @ Illegal pshort device: pshort5x4 must not overlap LVID |
| pshort5x4 AND LVID |
| } |
| "r_386_Illegal pshort device pshort5x4 must not overlap ENID" { |
| @ Illegal pshort device: pshort5x4 must not overlap ENID |
| pshort5x4 AND ENID |
| } |
| "r_387_Illegal pshort device pshort5x4 must not overlap lvtn" { |
| @ Illegal pshort device: pshort5x4 must not overlap lvtn |
| pshort5x4 AND lvtn |
| } |
| "r_388_Illegal pshort device pshort5x4 must not overlap hvi" { |
| @ Illegal pshort device: pshort5x4 must not overlap hvi |
| pshort5x4 AND hvi |
| } |
| "r_389_Illegal pshort device pshort5x4 must not overlap pnp" { |
| @ Illegal pshort device: pshort5x4 must not overlap pnp |
| pshort5x4 AND pnp |
| } |
| "r_390_Illegal pshort device pshort5x4 must not overlap DiodeID" { |
| @ Illegal pshort device: pshort5x4 must not overlap DiodeID |
| pshort5x4 AND DiodeID |
| } |
| "r_391_Illegal pshort device pshort5x4 must not overlap COREID" { |
| @ Illegal pshort device: pshort5x4 must not overlap COREID |
| pshort5x4 AND COREID |
| } |
| "r_392_Illegal pshort device pshort5x4 must not overlap PHdiodeID" { |
| @ Illegal pshort device: pshort5x4 must not overlap PHdiodeID |
| pshort5x4 AND PHdiodeID |
| } |
| "r_393_Illegal pshort device pshort5x4 must not overlap ldntm" { |
| @ Illegal pshort device: pshort5x4 must not overlap ldntm |
| pshort5x4 AND ldntm |
| } |
| "r_394_Illegal phv device phvNoCap must not overlap ncm" { |
| @ Illegal phv device: phvNoCap must not overlap ncm |
| phvNoCap AND ncm |
| } |
| "r_395_Illegal phv device phvNoCap must not overlap tap" { |
| @ Illegal phv device: phvNoCap must not overlap tap |
| phvNoCap AND tap |
| } |
| "r_396_Illegal phv device phvNoCap must not overlap tunm" { |
| @ Illegal phv device: phvNoCap must not overlap tunm |
| phvNoCap AND tunm |
| } |
| "r_397_Illegal phv device phvNoCap must not overlap diffres" { |
| @ Illegal phv device: phvNoCap must not overlap diffres |
| phvNoCap AND diffres |
| } |
| "r_398_Illegal phv device phvNoCap must not overlap diffcut" { |
| @ Illegal phv device: phvNoCap must not overlap diffcut |
| phvNoCap AND diffcut |
| } |
| "r_399_Illegal phv device phvNoCap must not overlap npc" { |
| @ Illegal phv device: phvNoCap must not overlap npc |
| phvNoCap AND npc |
| } |
| "r_400_Illegal phv device phvNoCap must not overlap polyres" { |
| @ Illegal phv device: phvNoCap must not overlap polyres |
| phvNoCap AND polyres |
| } |
| "r_401_Illegal phv device phvNoCap must not overlap polycut" { |
| @ Illegal phv device: phvNoCap must not overlap polycut |
| phvNoCap AND polycut |
| } |
| "r_402_Illegal phv device phvNoCap must not overlap li1res" { |
| @ Illegal phv device: phvNoCap must not overlap li1res |
| phvNoCap AND li1res |
| } |
| "r_403_Illegal phv device phvNoCap must not overlap li1cut" { |
| @ Illegal phv device: phvNoCap must not overlap li1cut |
| phvNoCap AND li1cut |
| } |
| "r_404_Illegal phv device phvNoCap must not overlap fuse" { |
| @ Illegal phv device: phvNoCap must not overlap fuse |
| phvNoCap AND fuse |
| } |
| "r_405_Illegal phv device phvNoCap must not overlap nsdm" { |
| @ Illegal phv device: phvNoCap must not overlap nsdm |
| phvNoCap AND nsdm |
| } |
| "r_406_Illegal phv device phvNoCap must not overlap capacitor" { |
| @ Illegal phv device: phvNoCap must not overlap capacitor |
| phvNoCap AND capacitor |
| } |
| "r_407_Illegal phv device phvNoCap must not overlap LVID" { |
| @ Illegal phv device: phvNoCap must not overlap LVID |
| phvNoCap AND LVID |
| } |
| "r_408_Illegal phv device phvNoCap must not overlap ENID" { |
| @ Illegal phv device: phvNoCap must not overlap ENID |
| phvNoCap AND ENID |
| } |
| "r_409_Illegal phv device phvNoCap must not overlap pnp" { |
| @ Illegal phv device: phvNoCap must not overlap pnp |
| phvNoCap AND pnp |
| } |
| "r_410_Illegal phv device phvNoCap must not overlap DiodeID" { |
| @ Illegal phv device: phvNoCap must not overlap DiodeID |
| phvNoCap AND DiodeID |
| } |
| "r_411_Illegal phv device phvNoCap must not overlap COREID" { |
| @ Illegal phv device: phvNoCap must not overlap COREID |
| phvNoCap AND COREID |
| } |
| "r_412_Illegal phv device phvNoCap must not overlap PHdiodeID" { |
| @ Illegal phv device: phvNoCap must not overlap PHdiodeID |
| phvNoCap AND PHdiodeID |
| } |
| "r_413_Illegal phv device phvNoCap must not overlap ldntm" { |
| @ Illegal phv device: phvNoCap must not overlap ldntm |
| phvNoCap AND ldntm |
| } |
| "r_414_Illegal phv device phv5x4 must not overlap ncm" { |
| @ Illegal phv device: phv5x4 must not overlap ncm |
| phv5x4 AND ncm |
| } |
| "r_415_Illegal phv device phv5x4 must not overlap tap" { |
| @ Illegal phv device: phv5x4 must not overlap tap |
| phv5x4 AND tap |
| } |
| "r_416_Illegal phv device phv5x4 must not overlap tunm" { |
| @ Illegal phv device: phv5x4 must not overlap tunm |
| phv5x4 AND tunm |
| } |
| "r_417_Illegal phv device phv5x4 must not overlap diffres" { |
| @ Illegal phv device: phv5x4 must not overlap diffres |
| phv5x4 AND diffres |
| } |
| "r_418_Illegal phv device phv5x4 must not overlap diffcut" { |
| @ Illegal phv device: phv5x4 must not overlap diffcut |
| phv5x4 AND diffcut |
| } |
| "r_419_Illegal phv device phv5x4 must not overlap npc" { |
| @ Illegal phv device: phv5x4 must not overlap npc |
| phv5x4 AND npc |
| } |
| "r_420_Illegal phv device phv5x4 must not overlap polyres" { |
| @ Illegal phv device: phv5x4 must not overlap polyres |
| phv5x4 AND polyres |
| } |
| "r_421_Illegal phv device phv5x4 must not overlap polycut" { |
| @ Illegal phv device: phv5x4 must not overlap polycut |
| phv5x4 AND polycut |
| } |
| "r_422_Illegal phv device phv5x4 must not overlap li1res" { |
| @ Illegal phv device: phv5x4 must not overlap li1res |
| phv5x4 AND li1res |
| } |
| "r_423_Illegal phv device phv5x4 must not overlap li1cut" { |
| @ Illegal phv device: phv5x4 must not overlap li1cut |
| phv5x4 AND li1cut |
| } |
| "r_424_Illegal phv device phv5x4 must not overlap fuse" { |
| @ Illegal phv device: phv5x4 must not overlap fuse |
| phv5x4 AND fuse |
| } |
| "r_425_Illegal phv device phv5x4 must not overlap nsdm" { |
| @ Illegal phv device: phv5x4 must not overlap nsdm |
| phv5x4 AND nsdm |
| } |
| "r_426_Illegal phv device phv5x4 must not overlap LVID" { |
| @ Illegal phv device: phv5x4 must not overlap LVID |
| phv5x4 AND LVID |
| } |
| "r_427_Illegal phv device phv5x4 must not overlap ENID" { |
| @ Illegal phv device: phv5x4 must not overlap ENID |
| phv5x4 AND ENID |
| } |
| "r_428_Illegal phv device phv5x4 must not overlap pnp" { |
| @ Illegal phv device: phv5x4 must not overlap pnp |
| phv5x4 AND pnp |
| } |
| "r_429_Illegal phv device phv5x4 must not overlap DiodeID" { |
| @ Illegal phv device: phv5x4 must not overlap DiodeID |
| phv5x4 AND DiodeID |
| } |
| "r_430_Illegal phv device phv5x4 must not overlap COREID" { |
| @ Illegal phv device: phv5x4 must not overlap COREID |
| phv5x4 AND COREID |
| } |
| "r_431_Illegal phv device phv5x4 must not overlap PHdiodeID" { |
| @ Illegal phv device: phv5x4 must not overlap PHdiodeID |
| phv5x4 AND PHdiodeID |
| } |
| "r_432_Illegal phv device phv5x4 must not overlap ldntm" { |
| @ Illegal phv device: phv5x4 must not overlap ldntm |
| phv5x4 AND ldntm |
| } |
| "r_433_Illegal phvesd device phvesd must not overlap ncm" { |
| @ Illegal phvesd device: phvesd must not overlap ncm |
| phvesd AND ncm |
| } |
| "r_434_Illegal phvesd device phvesd must not overlap tap" { |
| @ Illegal phvesd device: phvesd must not overlap tap |
| phvesd AND tap |
| } |
| "r_435_Illegal phvesd device phvesd must not overlap tunm" { |
| @ Illegal phvesd device: phvesd must not overlap tunm |
| phvesd AND tunm |
| } |
| "r_436_Illegal phvesd device phvesd must not overlap diffres" { |
| @ Illegal phvesd device: phvesd must not overlap diffres |
| phvesd AND diffres |
| } |
| "r_437_Illegal phvesd device phvesd must not overlap diffcut" { |
| @ Illegal phvesd device: phvesd must not overlap diffcut |
| phvesd AND diffcut |
| } |
| "r_438_Illegal phvesd device phvesd must not overlap npc" { |
| @ Illegal phvesd device: phvesd must not overlap npc |
| phvesd AND npc |
| } |
| "r_439_Illegal phvesd device phvesd must not overlap polyres" { |
| @ Illegal phvesd device: phvesd must not overlap polyres |
| phvesd AND polyres |
| } |
| "r_440_Illegal phvesd device phvesd must not overlap polycut" { |
| @ Illegal phvesd device: phvesd must not overlap polycut |
| phvesd AND polycut |
| } |
| "r_441_Illegal phvesd device phvesd must not overlap li1res" { |
| @ Illegal phvesd device: phvesd must not overlap li1res |
| phvesd AND li1res |
| } |
| "r_442_Illegal phvesd device phvesd must not overlap li1cut" { |
| @ Illegal phvesd device: phvesd must not overlap li1cut |
| phvesd AND li1cut |
| } |
| "r_443_Illegal phvesd device phvesd must not overlap fuse" { |
| @ Illegal phvesd device: phvesd must not overlap fuse |
| phvesd AND fuse |
| } |
| "r_444_Illegal phvesd device phvesd must not overlap nsdm" { |
| @ Illegal phvesd device: phvesd must not overlap nsdm |
| phvesd AND nsdm |
| } |
| "r_445_Illegal phvesd device phvesd must not overlap capacitor" { |
| @ Illegal phvesd device: phvesd must not overlap capacitor |
| phvesd AND capacitor |
| } |
| "r_446_Illegal phvesd device phvesd must not overlap LVID" { |
| @ Illegal phvesd device: phvesd must not overlap LVID |
| phvesd AND LVID |
| } |
| "r_447_Illegal phvesd device phvesd must not overlap ENID" { |
| @ Illegal phvesd device: phvesd must not overlap ENID |
| phvesd AND ENID |
| } |
| "r_448_Illegal phvesd device phvesd must not overlap hvtp" { |
| @ Illegal phvesd device: phvesd must not overlap hvtp |
| phvesd AND hvtp |
| } |
| "r_449_Illegal phvesd device phvesd must not overlap lvtn" { |
| @ Illegal phvesd device: phvesd must not overlap lvtn |
| phvesd AND lvtn |
| } |
| "r_450_Illegal phvesd device phvesd must not overlap pnp" { |
| @ Illegal phvesd device: phvesd must not overlap pnp |
| phvesd AND pnp |
| } |
| "r_451_Illegal phvesd device phvesd must not overlap DiodeID" { |
| @ Illegal phvesd device: phvesd must not overlap DiodeID |
| phvesd AND DiodeID |
| } |
| "r_452_Illegal phvesd device phvesd must not overlap COREID" { |
| @ Illegal phvesd device: phvesd must not overlap COREID |
| phvesd AND COREID |
| } |
| "r_453_Illegal phvesd device phvesd must not overlap PHdiodeID" { |
| @ Illegal phvesd device: phvesd must not overlap PHdiodeID |
| phvesd AND PHdiodeID |
| } |
| "r_454_Illegal phvesd device phvesd must not overlap ldntm" { |
| @ Illegal phvesd device: phvesd must not overlap ldntm |
| phvesd AND ldntm |
| } |
| "r_455_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap tap" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap tap |
| phighvtNoCap_PERI AND tap |
| } |
| "r_456_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap tunm" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap tunm |
| phighvtNoCap_PERI AND tunm |
| } |
| "r_457_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap diffres" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap diffres |
| phighvtNoCap_PERI AND diffres |
| } |
| "r_458_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap diffcut" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap diffcut |
| phighvtNoCap_PERI AND diffcut |
| } |
| "r_459_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap npc" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap npc |
| phighvtNoCap_PERI AND npc |
| } |
| "r_460_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap polyres" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap polyres |
| phighvtNoCap_PERI AND polyres |
| } |
| "r_461_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap polycut" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap polycut |
| phighvtNoCap_PERI AND polycut |
| } |
| "r_462_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap li1res" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap li1res |
| phighvtNoCap_PERI AND li1res |
| } |
| "r_463_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap li1cut" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap li1cut |
| phighvtNoCap_PERI AND li1cut |
| } |
| "r_464_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap fuse" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap fuse |
| phighvtNoCap_PERI AND fuse |
| } |
| "r_465_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap nsdm" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap nsdm |
| phighvtNoCap_PERI AND nsdm |
| } |
| "r_466_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap capacitor" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap capacitor |
| phighvtNoCap_PERI AND capacitor |
| } |
| "r_467_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap LVID" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap LVID |
| phighvtNoCap_PERI AND LVID |
| } |
| "r_468_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap ENID" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap ENID |
| phighvtNoCap_PERI AND ENID |
| } |
| "r_469_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap hvi" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap hvi |
| phighvtNoCap_PERI AND hvi |
| } |
| "r_470_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap pnp" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap pnp |
| phighvtNoCap_PERI AND pnp |
| } |
| "r_471_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap DiodeID" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap DiodeID |
| phighvtNoCap_PERI AND DiodeID |
| } |
| "r_472_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap COREID" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap COREID |
| phighvtNoCap_PERI AND COREID |
| } |
| "r_473_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap ESDID" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap ESDID |
| phighvtNoCap_PERI AND ESDID |
| } |
| "r_474_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap PHdiodeID" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap PHdiodeID |
| phighvtNoCap_PERI AND PHdiodeID |
| } |
| "r_475_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap ldntm" { |
| @ Illegal PFET_01V8_HVT device: phighvtNoCap_PERI must not overlap ldntm |
| phighvtNoCap_PERI AND ldntm |
| } |
| "r_476_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap tap" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap tap |
| phighvt5x4_PERI AND tap |
| } |
| "r_477_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap tunm" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap tunm |
| phighvt5x4_PERI AND tunm |
| } |
| "r_478_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap diffres" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap diffres |
| phighvt5x4_PERI AND diffres |
| } |
| "r_479_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap diffcut" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap diffcut |
| phighvt5x4_PERI AND diffcut |
| } |
| "r_480_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap npc" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap npc |
| phighvt5x4_PERI AND npc |
| } |
| "r_481_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap polyres" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap polyres |
| phighvt5x4_PERI AND polyres |
| } |
| "r_482_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap polycut" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap polycut |
| phighvt5x4_PERI AND polycut |
| } |
| "r_483_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap li1res" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap li1res |
| phighvt5x4_PERI AND li1res |
| } |
| "r_484_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap li1cut" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap li1cut |
| phighvt5x4_PERI AND li1cut |
| } |
| "r_485_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap fuse" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap fuse |
| phighvt5x4_PERI AND fuse |
| } |
| "r_486_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap nsdm" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap nsdm |
| phighvt5x4_PERI AND nsdm |
| } |
| "r_487_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap LVID" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap LVID |
| phighvt5x4_PERI AND LVID |
| } |
| "r_488_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap ENID" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap ENID |
| phighvt5x4_PERI AND ENID |
| } |
| "r_489_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap hvi" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap hvi |
| phighvt5x4_PERI AND hvi |
| } |
| "r_490_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap pnp" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap pnp |
| phighvt5x4_PERI AND pnp |
| } |
| "r_491_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap DiodeID" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap DiodeID |
| phighvt5x4_PERI AND DiodeID |
| } |
| "r_492_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap COREID" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap COREID |
| phighvt5x4_PERI AND COREID |
| } |
| "r_493_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap ESDID" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap ESDID |
| phighvt5x4_PERI AND ESDID |
| } |
| "r_494_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap PHdiodeID" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap PHdiodeID |
| phighvt5x4_PERI AND PHdiodeID |
| } |
| "r_495_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap ldntm" { |
| @ Illegal PFET_01V8_HVT device: phighvt5x4_PERI must not overlap ldntm |
| phighvt5x4_PERI AND ldntm |
| } |
| "r_496_Illegal ppu device phighvt_CORE must not overlap tap" { |
| @ Illegal ppu device: phighvt_CORE must not overlap tap |
| phighvt_CORE AND tap |
| } |
| "r_497_Illegal ppu device phighvt_CORE must not overlap tunm" { |
| @ Illegal ppu device: phighvt_CORE must not overlap tunm |
| phighvt_CORE AND tunm |
| } |
| "r_498_Illegal ppu device phighvt_CORE must not overlap diffres" { |
| @ Illegal ppu device: phighvt_CORE must not overlap diffres |
| phighvt_CORE AND diffres |
| } |
| "r_499_Illegal ppu device phighvt_CORE must not overlap diffcut" { |
| @ Illegal ppu device: phighvt_CORE must not overlap diffcut |
| phighvt_CORE AND diffcut |
| } |
| "r_500_Illegal ppu device phighvt_CORE must not overlap npc" { |
| @ Illegal ppu device: phighvt_CORE must not overlap npc |
| phighvt_CORE AND npc |
| } |
| "r_501_Illegal ppu device phighvt_CORE must not overlap polyres" { |
| @ Illegal ppu device: phighvt_CORE must not overlap polyres |
| phighvt_CORE AND polyres |
| } |
| "r_502_Illegal ppu device phighvt_CORE must not overlap polycut" { |
| @ Illegal ppu device: phighvt_CORE must not overlap polycut |
| phighvt_CORE AND polycut |
| } |
| "r_503_Illegal ppu device phighvt_CORE must not overlap li1res" { |
| @ Illegal ppu device: phighvt_CORE must not overlap li1res |
| phighvt_CORE AND li1res |
| } |
| "r_504_Illegal ppu device phighvt_CORE must not overlap li1cut" { |
| @ Illegal ppu device: phighvt_CORE must not overlap li1cut |
| phighvt_CORE AND li1cut |
| } |
| "r_505_Illegal ppu device phighvt_CORE must not overlap fuse" { |
| @ Illegal ppu device: phighvt_CORE must not overlap fuse |
| phighvt_CORE AND fuse |
| } |
| "r_506_Illegal ppu device phighvt_CORE must not overlap nsdm" { |
| @ Illegal ppu device: phighvt_CORE must not overlap nsdm |
| phighvt_CORE AND nsdm |
| } |
| "r_507_Illegal ppu device phighvt_CORE must not overlap capacitor" { |
| @ Illegal ppu device: phighvt_CORE must not overlap capacitor |
| phighvt_CORE AND capacitor |
| } |
| "r_508_Illegal ppu device phighvt_CORE must not overlap LVID" { |
| @ Illegal ppu device: phighvt_CORE must not overlap LVID |
| phighvt_CORE AND LVID |
| } |
| "r_509_Illegal ppu device phighvt_CORE must not overlap ENID" { |
| @ Illegal ppu device: phighvt_CORE must not overlap ENID |
| phighvt_CORE AND ENID |
| } |
| "r_510_Illegal ppu device phighvt_CORE must not overlap hvi" { |
| @ Illegal ppu device: phighvt_CORE must not overlap hvi |
| phighvt_CORE AND hvi |
| } |
| "r_511_Illegal ppu device phighvt_CORE must not overlap pnp" { |
| @ Illegal ppu device: phighvt_CORE must not overlap pnp |
| phighvt_CORE AND pnp |
| } |
| "r_512_Illegal ppu device phighvt_CORE must not overlap DiodeID" { |
| @ Illegal ppu device: phighvt_CORE must not overlap DiodeID |
| phighvt_CORE AND DiodeID |
| } |
| "r_513_Illegal ppu device phighvt_CORE must not overlap ESDID" { |
| @ Illegal ppu device: phighvt_CORE must not overlap ESDID |
| phighvt_CORE AND ESDID |
| } |
| "r_514_Illegal ppu device phighvt_CORE must not overlap PHdiodeID" { |
| @ Illegal ppu device: phighvt_CORE must not overlap PHdiodeID |
| phighvt_CORE AND PHdiodeID |
| } |
| "r_515_Illegal ppu device phighvt_CORE must not overlap ldntm" { |
| @ Illegal ppu device: phighvt_CORE must not overlap ldntm |
| phighvt_CORE AND ldntm |
| } |
| "r_516_phighvt in core must overlap ncm" { |
| @ PFET_01V8_HVT in core must overlap ncm: phighvt_CORE must be enclosed by ncm |
| phighvt_CORE NOT ncm |
| } |
| "r_517_Illegal plowvt device plowvtNoCap must not overlap tap" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap tap |
| plowvtNoCap AND tap |
| } |
| "r_518_Illegal plowvt device plowvtNoCap must not overlap tunm" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap tunm |
| plowvtNoCap AND tunm |
| } |
| "r_519_Illegal plowvt device plowvtNoCap must not overlap diffres" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap diffres |
| plowvtNoCap AND diffres |
| } |
| "r_520_Illegal plowvt device plowvtNoCap must not overlap diffcut" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap diffcut |
| plowvtNoCap AND diffcut |
| } |
| "r_521_Illegal plowvt device plowvtNoCap must not overlap npc" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap npc |
| plowvtNoCap AND npc |
| } |
| "r_522_Illegal plowvt device plowvtNoCap must not overlap polyres" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap polyres |
| plowvtNoCap AND polyres |
| } |
| "r_523_Illegal plowvt device plowvtNoCap must not overlap polycut" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap polycut |
| plowvtNoCap AND polycut |
| } |
| "r_524_Illegal plowvt device plowvtNoCap must not overlap li1res" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap li1res |
| plowvtNoCap AND li1res |
| } |
| "r_525_Illegal plowvt device plowvtNoCap must not overlap li1cut" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap li1cut |
| plowvtNoCap AND li1cut |
| } |
| "r_526_Illegal plowvt device plowvtNoCap must not overlap fuse" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap fuse |
| plowvtNoCap AND fuse |
| } |
| "r_527_Illegal plowvt device plowvtNoCap must not overlap nsdm" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap nsdm |
| plowvtNoCap AND nsdm |
| } |
| "r_528_Illegal plowvt device plowvtNoCap must not overlap capacitor" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap capacitor |
| plowvtNoCap AND capacitor |
| } |
| "r_529_Illegal plowvt device plowvtNoCap must not overlap LVID" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap LVID |
| plowvtNoCap AND LVID |
| } |
| "r_530_Illegal plowvt device plowvtNoCap must not overlap ENID" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap ENID |
| plowvtNoCap AND ENID |
| } |
| "r_531_Illegal plowvt device plowvtNoCap must not overlap hvtp" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap hvtp |
| plowvtNoCap AND hvtp |
| } |
| "r_532_Illegal plowvt device plowvtNoCap must not overlap hvi" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap hvi |
| plowvtNoCap AND hvi |
| } |
| "r_533_Illegal plowvt device plowvtNoCap must not overlap pnp" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap pnp |
| plowvtNoCap AND pnp |
| } |
| "r_534_Illegal plowvt device plowvtNoCap must not overlap DiodeID" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap DiodeID |
| plowvtNoCap AND DiodeID |
| } |
| "r_535_Illegal plowvt device plowvtNoCap must not overlap COREID" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap COREID |
| plowvtNoCap AND COREID |
| } |
| "r_536_Illegal plowvt device plowvtNoCap must not overlap ESDID" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap ESDID |
| plowvtNoCap AND ESDID |
| } |
| "r_537_Illegal plowvt device plowvtNoCap must not overlap PHdiodeID" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap PHdiodeID |
| plowvtNoCap AND PHdiodeID |
| } |
| "r_538_Illegal plowvt device plowvtNoCap must not overlap ldntm" { |
| @ Illegal plowvt device: plowvtNoCap must not overlap ldntm |
| plowvtNoCap AND ldntm |
| } |
| "r_539_Illegal plowvt device plowvt5x4 must not overlap tap" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap tap |
| plowvt5x4 AND tap |
| } |
| "r_540_Illegal plowvt device plowvt5x4 must not overlap tunm" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap tunm |
| plowvt5x4 AND tunm |
| } |
| "r_541_Illegal plowvt device plowvt5x4 must not overlap diffres" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap diffres |
| plowvt5x4 AND diffres |
| } |
| "r_542_Illegal plowvt device plowvt5x4 must not overlap diffcut" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap diffcut |
| plowvt5x4 AND diffcut |
| } |
| "r_543_Illegal plowvt device plowvt5x4 must not overlap npc" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap npc |
| plowvt5x4 AND npc |
| } |
| "r_544_Illegal plowvt device plowvt5x4 must not overlap polyres" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap polyres |
| plowvt5x4 AND polyres |
| } |
| "r_545_Illegal plowvt device plowvt5x4 must not overlap polycut" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap polycut |
| plowvt5x4 AND polycut |
| } |
| "r_546_Illegal plowvt device plowvt5x4 must not overlap li1res" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap li1res |
| plowvt5x4 AND li1res |
| } |
| "r_547_Illegal plowvt device plowvt5x4 must not overlap li1cut" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap li1cut |
| plowvt5x4 AND li1cut |
| } |
| "r_548_Illegal plowvt device plowvt5x4 must not overlap fuse" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap fuse |
| plowvt5x4 AND fuse |
| } |
| "r_549_Illegal plowvt device plowvt5x4 must not overlap nsdm" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap nsdm |
| plowvt5x4 AND nsdm |
| } |
| "r_550_Illegal plowvt device plowvt5x4 must not overlap LVID" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap LVID |
| plowvt5x4 AND LVID |
| } |
| "r_551_Illegal plowvt device plowvt5x4 must not overlap ENID" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap ENID |
| plowvt5x4 AND ENID |
| } |
| "r_552_Illegal plowvt device plowvt5x4 must not overlap hvtp" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap hvtp |
| plowvt5x4 AND hvtp |
| } |
| "r_553_Illegal plowvt device plowvt5x4 must not overlap hvi" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap hvi |
| plowvt5x4 AND hvi |
| } |
| "r_554_Illegal plowvt device plowvt5x4 must not overlap pnp" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap pnp |
| plowvt5x4 AND pnp |
| } |
| "r_555_Illegal plowvt device plowvt5x4 must not overlap DiodeID" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap DiodeID |
| plowvt5x4 AND DiodeID |
| } |
| "r_556_Illegal plowvt device plowvt5x4 must not overlap COREID" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap COREID |
| plowvt5x4 AND COREID |
| } |
| "r_557_Illegal plowvt device plowvt5x4 must not overlap ESDID" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap ESDID |
| plowvt5x4 AND ESDID |
| } |
| "r_558_Illegal plowvt device plowvt5x4 must not overlap PHdiodeID" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap PHdiodeID |
| plowvt5x4 AND PHdiodeID |
| } |
| "r_559_Illegal plowvt device plowvt5x4 must not overlap ldntm" { |
| @ Illegal plowvt device: plowvt5x4 must not overlap ldntm |
| plowvt5x4 AND ldntm |
| } |
| |
| // end illegal device checks |
| |
| q0allGate = SIZE allGate BY 0.005 |
| q1allGate = MOSDIFFnotPOLY AND q0allGate |
| drainOnly = allGate NOT (NOT TOUCH (INTERACT q0allGate q1allGate >= 2) q1allGate) |
| q0wfl_allGateMosDiffHoles = (HOLES MOSDIFF) NOT MOSDIFF |
| q0wfl_allGateTapInDiffHole = (tap WITH EDGE (tap COINCIDENT INSIDE EDGE q0wfl_allGateMosDiffHoles)) INSIDE q0wfl_allGateMosDiffHoles |
| q0wfl_allGateFilledDiffHoles = q0wfl_allGateMosDiffHoles INSIDE q0wfl_allGateTapInDiffHole |
| q0wfl_allGateGateHoles = (HOLES allGate) NOT allGate |
| q0wfl_allGateCapHoles = q0wfl_allGateFilledDiffHoles AND q0wfl_allGateGateHoles |
| q0wfl_allGateCapHoles_sz = SIZE q0wfl_allGateCapHoles BY 0.005 |
| q0wfl_allGateDiff = NOT TOUCH (INTERACT MOSDIFF q0wfl_allGateCapHoles_sz) q0wfl_allGateCapHoles_sz |
| q0wfl_allGateDiffNotPoly = q0wfl_allGateDiff AND MOSDIFFnotPOLY |
| q0wfl_allGateDiffNotPolyBtTap = q0wfl_allGateDiffNotPoly WITH EDGE (q0wfl_allGateDiffNotPoly COINCIDENT OUTSIDE EDGE tap) |
| q0wfl_allGateDiffNotPolyNoTap = q0wfl_allGateDiffNotPoly NOT q0wfl_allGateDiffNotPolyBtTap |
| q0wfl_allGateDiffNotButting = NOT TOUCH (INTERACT q0wfl_allGateDiff q0wfl_allGateDiffNotPolyNoTap) q0wfl_allGateDiffNotPolyNoTap |
| q0wfl_allGateDiff_b = q0wfl_allGateDiff NOT q0wfl_allGateDiffNotButting |
| q0wfl_allGateGateHoled = DONUT allGate |
| waffleCap = q0wfl_allGateGateHoled AND q0wfl_allGateDiff_b |
| q0wfl_allGateCapGood = waffleCap WITH EDGE (waffleCap COINCIDENT OUTSIDE EDGE MOSDIFFnotPOLY) == 2 |
| q0wfl_allGateCapBad = waffleCap NOT q0wfl_allGateCapGood |
| "r_560_Illegal" { |
| @ Illegal: The waffle cap poly:gate layer must touch exactly two unique (MOSDIFFnotPOLY) regions |
| COPY q0wfl_allGateCapBad |
| } |
| q2allGate = (HOLES MOSDIFFandPOLY) NOT MOSDIFFandPOLY |
| q3allGate = q2allGate INSIDE (MOSDIFFnotPOLY OR tap) |
| q4allGate = MOSDIFFnotPOLY NOT q3allGate |
| q5allGate = INTERACT allGate q3allGate |
| q6allGate = INTERACT q5allGate q4allGate |
| halfFieldless = q6allGate NOT waffleCap |
| q8allGate = allGate AND blackBoxCells |
| fixedBlackBox = COPY q8allGate |
| normGate = (((allGate NOT waffleCap) NOT drainOnly) NOT halfFieldless) NOT fixedBlackBox |
| nshortnormGate = nfet_01v8 AND normGate |
| nshortwaffleCap = nfet_01v8 AND waffleCap |
| nshortdrainOnly = nfet_01v8 AND drainOnly |
| nshorthalfFieldless = nfet_01v8 AND halfFieldless |
| nshortfixedBlackBox = nfet_01v8 AND fixedBlackBox |
| nlowvtnormGate = nlowvt AND normGate |
| nlowvtwaffleCap = nlowvt AND waffleCap |
| nlowvtdrainOnly = nlowvt AND drainOnly |
| nlowvthalfFieldless = nlowvt AND halfFieldless |
| nlowvtfixedBlackBox = nlowvt AND fixedBlackBox |
| sonos_enormGate = sonos_e AND normGate |
| sonos_ewaffleCap = sonos_e AND waffleCap |
| sonos_edrainOnly = sonos_e AND drainOnly |
| sonos_ehalfFieldless = sonos_e AND halfFieldless |
| sonos_efixedBlackBox = sonos_e AND fixedBlackBox |
| nhvnormGate = nhv AND normGate |
| nhvwaffleCap = nhv AND waffleCap |
| nhvdrainOnly = nhv AND drainOnly |
| nhvhalfFieldless = nhv AND halfFieldless |
| nhvfixedBlackBox = nhv AND fixedBlackBox |
| nhvnativenormGate = nhvnative AND normGate |
| nhvnativewaffleCap = nhvnative AND waffleCap |
| nhvnativedrainOnly = nhvnative AND drainOnly |
| nhvnativehalfFieldless = nhvnative AND halfFieldless |
| nhvnativefixedBlackBox = nhvnative AND fixedBlackBox |
| ntvnativenormGate = ntvnative AND normGate |
| ntvnativewaffleCap = ntvnative AND waffleCap |
| ntvnativedrainOnly = ntvnative AND drainOnly |
| ntvnativehalfFieldless = ntvnative AND halfFieldless |
| ntvnativefixedBlackBox = ntvnative AND fixedBlackBox |
| fnpassnormGate = fnpass AND normGate |
| fnpasswaffleCap = fnpass AND waffleCap |
| fnpassdrainOnly = fnpass AND drainOnly |
| fnpasshalfFieldless = fnpass AND halfFieldless |
| fnpassfixedBlackBox = fnpass AND fixedBlackBox |
| nhvesdnormGate = nhvesd AND normGate |
| nhvesdwaffleCap = nhvesd AND waffleCap |
| nhvesddrainOnly = nhvesd AND drainOnly |
| nhvesdhalfFieldless = nhvesd AND halfFieldless |
| nhvesdfixedBlackBox = nhvesd AND fixedBlackBox |
| nhvnativeesdnormGate = nhvnativeesd AND normGate |
| nhvnativeesdwaffleCap = nhvnativeesd AND waffleCap |
| nhvnativeesddrainOnly = nhvnativeesd AND drainOnly |
| nhvnativeesdhalfFieldless = nhvnativeesd AND halfFieldless |
| nhvnativeesdfixedBlackBox = nhvnativeesd AND fixedBlackBox |
| nshortesdnormGate = nshortesd AND normGate |
| nshortesdwaffleCap = nshortesd AND waffleCap |
| nshortesddrainOnly = nshortesd AND drainOnly |
| nshortesdhalfFieldless = nshortesd AND halfFieldless |
| nshortesdfixedBlackBox = nshortesd AND fixedBlackBox |
| pshortnormGate = pshort AND normGate |
| pshortwaffleCap = pshort AND waffleCap |
| pshortdrainOnly = pshort AND drainOnly |
| pshorthalfFieldless = pshort AND halfFieldless |
| pshortfixedBlackBox = pshort AND fixedBlackBox |
| phvnormGate = phv AND normGate |
| phvwaffleCap = phv AND waffleCap |
| phvdrainOnly = phv AND drainOnly |
| phvhalfFieldless = phv AND halfFieldless |
| phvfixedBlackBox = phv AND fixedBlackBox |
| phvesdnormGate = phvesd AND normGate |
| phvesdwaffleCap = phvesd AND waffleCap |
| phvesddrainOnly = phvesd AND drainOnly |
| phvesdhalfFieldless = phvesd AND halfFieldless |
| phvesdfixedBlackBox = phvesd AND fixedBlackBox |
| phighvtnormGate = PFET_01V8_HVT AND normGate |
| phighvtwaffleCap = PFET_01V8_HVT AND waffleCap |
| phighvtdrainOnly = PFET_01V8_HVT AND drainOnly |
| phighvthalfFieldless = PFET_01V8_HVT AND halfFieldless |
| phighvtfixedBlackBox = PFET_01V8_HVT AND fixedBlackBox |
| plowvtnormGate = plowvt AND normGate |
| plowvtwaffleCap = plowvt AND waffleCap |
| plowvtdrainOnly = plowvt AND drainOnly |
| plowvthalfFieldless = plowvt AND halfFieldless |
| plowvtfixedBlackBox = plowvt AND fixedBlackBox |
| q0bigallGate = SIZE allGate BY 0.005 |
| q0bigTermallGate = q0bigallGate AND MOSDIFFnotPOLY |
| q0GATEadjallGate = (INTERACT MOSDIFFandPOLY polyGate) NOT polyGate |
| q0bigGATEdjallGate = SIZE q0GATEadjallGate BY 0.005 |
| q0bigGATEadjallGate = INTERACT q0bigGATEdjallGate q0bigTermallGate == 1 |
| q1GATEadjallGate = q0GATEadjallGate AND q0bigGATEadjallGate |
| MOSDIFFnotPOLYgate = MOSDIFFnotPOLY OR q1GATEadjallGate |
| q0NDIFF_cond = NDIFF_cond NOT licon1 |
| q1NDIFF_cond = licon1 AND NDIFF_cond |
| q2NDIFF_cond = q0NDIFF_cond COINCIDENT EDGE nfet_01v8 |
| q3NDIFF_cond = q0NDIFF_cond COINCIDENT EDGE q1NDIFF_cond |
| q4NDIFF_cond = INTERNAL q2NDIFF_cond q3NDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q5NDIFF_cond = q4NDIFF_cond INSIDE NDIFF_cond |
| q6NDIFF_cond = SIZE diff BY -0.005 |
| q7NDIFF_cond = q5NDIFF_cond AND q6NDIFF_cond |
| q8NDIFF_cond = q7NDIFF_cond NOT licon1 |
| q0nshort = q8NDIFF_cond NOT (INTERACT q8NDIFF_cond licon1 > 1) |
| q0diffTap = diffTap NOT nfet_01v8 |
| q1diffTap = q0diffTap COINCIDENT EDGE nfet_01v8 |
| q2diffTap = EXPAND EDGE q1diffTap INSIDE BY 0.005 |
| q1nshort = (SIZE q2diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR nfet_01v8 |
| |
| |
| // ;ss sheet res values for NRS / NRD |
| |
| VARIABLE n_res 120.0 |
| VARIABLE nv_res 114.0 |
| VARIABLE p_res 197.0 |
| VARIABLE pv_res 191.0 |
| |
| |
| DEVICE MN(nfet_01v8) nshortfixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nshortfixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MN(nfet_01v8) nshortfixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLY> <q0nshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nshortfixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MN(nfet_01v8) nshorthalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 nshorthalfFieldless MOSDIFFnotPOLY diff q1nshort n_res |
| |
| DEVICE MN(nfet_01v8) nshorthalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLY> <q0nshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 nshorthalfFieldless MOSDIFFnotPOLY diff q1nshort q0nshort n_res |
| |
| |
| DEVICE MN(nfet_01v8) nshortdrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 nshortdrainOnly NDIFF_cond diff q1nshort n_res |
| |
| DEVICE MN(nfet_01v8) nshortdrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLY> <q0nshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 nshortdrainOnly NDIFF_cond diff q1nshort q0nshort n_res |
| |
| |
| //TRACE PROPERTY npass l l 1 |
| //TRACE PROPERTY npass w w 1 |
| //TRACE PROPERTY npass m m 0 |
| |
| //CMACRO TRACE_MOS_ELEMENT3 nfet_01v8 npass m mult w l |
| |
| //TRACE PROPERTY drainOnly udef_a udef_a 1 |
| //TRACE PROPERTY drainOnly udef_p udef_p 1 |
| //TRACE PROPERTY drainOnly m m 0 |
| |
| // CMACRO TRACE_MOS drainOnly m mult w l |
| |
| |
| DEVICE MN(nfet_01v8) nshortwaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nshortwaffleCap diff |
| |
| DEVICE MN(nfet_01v8) nshortwaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLY> <q0nshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nshortwaffleCap diff |
| |
| |
| DEVICE MN(nfet_01v8) nshortnormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 nshortnormGate MOSDIFFnotPOLYgate diff q1nshort n_res |
| |
| DEVICE MN(nfet_01v8) nshortnormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nshort> <MOSDIFFnotPOLYgate> <q0nshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 nshortnormGate MOSDIFFnotPOLYgate diff q1nshort q0nshort n_res |
| |
| |
| // ;ss Use MACRO for TRACE PROPERTY |
| // needed to properly handle "mult" |
| |
| // TRACE PROPERTY MN(nfet_01v8) w w 1e-10 |
| // TRACE PROPERTY MN(nfet_01v8) l l 1e-10 |
| // TRACE PROPERTY MN(nfet_01v8) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MN nfet_01v8 m mult w l |
| //CMACRO TRACE_MOS_ELEMENT3 MN npass m mult w l udef_a udef_p |
| CMACRO TRACE_MOS_ELEMENT3 MN npass m mult w l |
| //TRACE PROPERTY MN npass udef_a udef_a 0 |
| //TRACE PROPERTY MN npass udef_p udef_p 0 |
| |
| |
| // TRACE PROPERTY MN w w 1e-10 |
| // TRACE PROPERTY MN l l 1e-10 |
| // TRACE PROPERTY MN m m 0 |
| |
| //CMACRO TRACE_MOS MN m mult w l |
| |
| |
| |
| q9NDIFF_cond = NDIFF_cond NOT licon1 |
| q10NDIFF_cond = licon1 AND NDIFF_cond |
| q11NDIFF_cond = q9NDIFF_cond COINCIDENT EDGE nlowvt |
| q12NDIFF_cond = q9NDIFF_cond COINCIDENT EDGE q10NDIFF_cond |
| q13NDIFF_cond = INTERNAL q11NDIFF_cond q12NDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q14NDIFF_cond = q13NDIFF_cond INSIDE NDIFF_cond |
| q15NDIFF_cond = SIZE diff BY -0.005 |
| q16NDIFF_cond = q14NDIFF_cond AND q15NDIFF_cond |
| q17NDIFF_cond = q16NDIFF_cond NOT licon1 |
| q0nlowvt = q17NDIFF_cond NOT (INTERACT q17NDIFF_cond licon1 > 1) |
| q3diffTap = diffTap NOT nlowvt |
| q4diffTap = q3diffTap COINCIDENT EDGE nlowvt |
| q5diffTap = EXPAND EDGE q4diffTap INSIDE BY 0.005 |
| q1nlowvt = (SIZE q5diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR nlowvt |
| |
| |
| DEVICE MN(nlowvt) nlowvtfixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nlowvtfixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MN(nlowvt) nlowvtfixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLY> <q0nlowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nlowvtfixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MN(nlowvt) nlowvthalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 nlowvthalfFieldless MOSDIFFnotPOLY diff q1nlowvt n_res |
| |
| DEVICE MN(nlowvt) nlowvthalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLY> <q0nlowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 nlowvthalfFieldless MOSDIFFnotPOLY diff q1nlowvt q0nlowvt n_res |
| |
| |
| DEVICE MN(nlowvt) nlowvtdrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 nlowvtdrainOnly NDIFF_cond diff q1nlowvt n_res |
| |
| DEVICE MN(nlowvt) nlowvtdrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLY> <q0nlowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 nlowvtdrainOnly NDIFF_cond diff q1nlowvt q0nlowvt n_res |
| |
| |
| //TRACE PROPERTY drainOnly(nlowvt) udef_a udef_a 1 |
| //TRACE PROPERTY drainOnly(nlowvt) udef_p udef_p 1 |
| //TRACE PROPERTY drainOnly(nlowvt) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly nlowvt m mult w l |
| |
| |
| DEVICE MN(nlowvt) nlowvtwaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nlowvtwaffleCap diff |
| |
| DEVICE MN(nlowvt) nlowvtwaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLY> <q0nlowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nlowvtwaffleCap diff |
| |
| |
| DEVICE MN(nlowvt) nlowvtnormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 nlowvtnormGate MOSDIFFnotPOLYgate diff q1nlowvt n_res |
| |
| DEVICE MN(nlowvt) nlowvtnormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nlowvt> <MOSDIFFnotPOLYgate> <q0nlowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 nlowvtnormGate MOSDIFFnotPOLYgate diff q1nlowvt q0nlowvt n_res |
| |
| |
| // TRACE PROPERTY MN(nlowvt) w w 1e-10 |
| // TRACE PROPERTY MN(nlowvt) l l 1e-10 |
| // TRACE PROPERTY MN(nlowvt) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MN nlowvt m mult w l |
| |
| |
| q18NDIFF_cond = NDIFF_cond NOT licon1 |
| q19NDIFF_cond = licon1 AND NDIFF_cond |
| q20NDIFF_cond = q18NDIFF_cond COINCIDENT EDGE sonos_e |
| q21NDIFF_cond = q18NDIFF_cond COINCIDENT EDGE q19NDIFF_cond |
| q22NDIFF_cond = INTERNAL q20NDIFF_cond q21NDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q23NDIFF_cond = q22NDIFF_cond INSIDE NDIFF_cond |
| q24NDIFF_cond = SIZE diff BY -0.005 |
| q25NDIFF_cond = q23NDIFF_cond AND q24NDIFF_cond |
| q26NDIFF_cond = q25NDIFF_cond NOT licon1 |
| q0sonos_e = q26NDIFF_cond NOT (INTERACT q26NDIFF_cond licon1 > 1) |
| q6diffTap = diffTap NOT sonos_e |
| q7diffTap = q6diffTap COINCIDENT EDGE sonos_e |
| q8diffTap = EXPAND EDGE q7diffTap INSIDE BY 0.005 |
| q1sonos_e = (SIZE q8diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR sonos_e |
| |
| |
| DEVICE M(sonos_e) sonos_efixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox sonos_efixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE M(sonos_e) sonos_efixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLY> <q0sonos_e> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox sonos_efixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE M(sonos_e) sonos_ehalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 sonos_ehalfFieldless MOSDIFFnotPOLY diff q1sonos_e n_res |
| |
| DEVICE M(sonos_e) sonos_ehalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLY> <q0sonos_e> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 sonos_ehalfFieldless MOSDIFFnotPOLY diff q1sonos_e q0sonos_e n_res |
| |
| |
| DEVICE MN(sonos_e) sonos_edrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 sonos_edrainOnly NDIFF_cond diff q1sonos_e n_res |
| |
| DEVICE MN(sonos_e) sonos_edrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLY> <q0sonos_e> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 sonos_edrainOnly NDIFF_cond diff q1sonos_e q0sonos_e n_res |
| |
| |
| //TRACE PROPERTY drainOnly(sonos_e) udef_a udef_a 1 |
| //TRACE PROPERTY drainOnly(sonos_e) udef_p udef_p 1 |
| //TRACE PROPERTY drainOnly(sonos_e) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly sonos_e m mult w l |
| |
| |
| DEVICE M(sonos_e) sonos_ewaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle sonos_ewaffleCap diff |
| |
| DEVICE M(sonos_e) sonos_ewaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLY> <q0sonos_e> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle sonos_ewaffleCap diff |
| |
| |
| DEVICE M(sonos_e) sonos_enormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 sonos_enormGate MOSDIFFnotPOLYgate diff q1sonos_e n_res |
| |
| DEVICE M(sonos_e) sonos_enormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1sonos_e> <MOSDIFFnotPOLYgate> <q0sonos_e> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 sonos_enormGate MOSDIFFnotPOLYgate diff q1sonos_e q0sonos_e n_res |
| |
| |
| // TRACE PROPERTY M(sonos_e) w w 1e-10 |
| // TRACE PROPERTY M(sonos_e) l l 1e-10 |
| // TRACE PROPERTY M(sonos_e) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT M sonos_e m mult w l |
| |
| // TRACE PROPERTY M w w 1e-10 |
| // TRACE PROPERTY M l l 1e-10 |
| // TRACE PROPERTY M m m 0 |
| |
| CMACRO TRACE_MOS M m mult w l |
| |
| |
| q27NDIFF_cond = NDIFF_cond NOT licon1 |
| q28NDIFF_cond = licon1 AND NDIFF_cond |
| q29NDIFF_cond = q27NDIFF_cond COINCIDENT EDGE fnpass |
| q30NDIFF_cond = q27NDIFF_cond COINCIDENT EDGE q28NDIFF_cond |
| q31NDIFF_cond = INTERNAL q29NDIFF_cond q30NDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q32NDIFF_cond = q31NDIFF_cond INSIDE NDIFF_cond |
| q33NDIFF_cond = SIZE diff BY -0.005 |
| q34NDIFF_cond = q32NDIFF_cond AND q33NDIFF_cond |
| q35NDIFF_cond = q34NDIFF_cond NOT licon1 |
| q0fnpass = q35NDIFF_cond NOT (INTERACT q35NDIFF_cond licon1 > 1) |
| q9diffTap = diffTap NOT fnpass |
| q10diffTap = q9diffTap COINCIDENT EDGE fnpass |
| q11diffTap = EXPAND EDGE q10diffTap INSIDE BY 0.005 |
| q1fnpass = (SIZE q11diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR fnpass |
| |
| DEVICE M(fnpass) fnpassfixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox fnpassfixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE M(fnpass) fnpassfixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLY> <q0fnpass> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox fnpassfixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE M(fnpass) fnpasshalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 fnpasshalfFieldless MOSDIFFnotPOLY diff q1fnpass n_res |
| |
| DEVICE M(fnpass) fnpasshalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLY> <q0fnpass> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 fnpasshalfFieldless MOSDIFFnotPOLY diff q1fnpass q0fnpass n_res |
| |
| |
| DEVICE MN(fnpass) fnpassdrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 fnpassdrainOnly NDIFF_cond diff q1fnpass n_res |
| |
| DEVICE MN(fnpass) fnpassdrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLY> <q0fnpass> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 fnpassdrainOnly NDIFF_cond diff q1fnpass q0fnpass n_res |
| |
| |
| // TRACE PROPERTY drainOnly(fnpass) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(fnpass) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(fnpass) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly fnpass m mult w l |
| |
| |
| DEVICE M(fnpass) fnpasswaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle fnpasswaffleCap diff |
| |
| DEVICE M(fnpass) fnpasswaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLY> <q0fnpass> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle fnpasswaffleCap diff |
| |
| |
| DEVICE M(fnpass) fnpassnormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 fnpassnormGate MOSDIFFnotPOLYgate diff q1fnpass n_res |
| |
| DEVICE M(fnpass) fnpassnormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1fnpass> <MOSDIFFnotPOLYgate> <q0fnpass> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 fnpassnormGate MOSDIFFnotPOLYgate diff q1fnpass q0fnpass n_res |
| |
| |
| // TRACE PROPERTY M(fnpass) w w 1e-10 |
| // TRACE PROPERTY M(fnpass) l l 1e-10 |
| // TRACE PROPERTY M(fnpass) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT M fnpass m mult w l |
| |
| |
| q36NDIFF_cond = NDIFF_cond NOT licon1 |
| q37NDIFF_cond = licon1 AND NDIFF_cond |
| q38NDIFF_cond = q36NDIFF_cond COINCIDENT EDGE nhv |
| q39NDIFF_cond = q36NDIFF_cond COINCIDENT EDGE q37NDIFF_cond |
| q40NDIFF_cond = INTERNAL q38NDIFF_cond q39NDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q41NDIFF_cond = q40NDIFF_cond INSIDE NDIFF_cond |
| q42NDIFF_cond = SIZE diff BY -0.005 |
| q43NDIFF_cond = q41NDIFF_cond AND q42NDIFF_cond |
| q44NDIFF_cond = q43NDIFF_cond NOT licon1 |
| q0nhv = q44NDIFF_cond NOT (INTERACT q44NDIFF_cond licon1 > 1) |
| q12diffTap = diffTap NOT nhv |
| q13diffTap = q12diffTap COINCIDENT EDGE nhv |
| q14diffTap = EXPAND EDGE q13diffTap INSIDE BY 0.005 |
| q1nhv = (SIZE q14diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR nhv |
| |
| |
| DEVICE MN(nhv) nhvfixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nhvfixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MN(nhv) nhvfixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLY> <q0nhv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nhvfixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MN(nhv) nhvhalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 nhvhalfFieldless MOSDIFFnotPOLY diff q1nhv nv_res |
| |
| DEVICE MN(nhv) nhvhalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLY> <q0nhv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 nhvhalfFieldless MOSDIFFnotPOLY diff q1nhv q0nhv nv_res |
| |
| |
| DEVICE MN(nhv) nhvdrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 nhvdrainOnly NDIFF_cond diff q1nhv nv_res |
| |
| DEVICE MN(nhv) nhvdrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLY> <q0nhv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 nhvdrainOnly NDIFF_cond diff q1nhv q0nhv nv_res |
| |
| |
| // TRACE PROPERTY drainOnly(nhv) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(nhv) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(nhv) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly nhv m mult w l |
| |
| |
| DEVICE MN(nhv) nhvwaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nhvwaffleCap diff |
| |
| DEVICE MN(nhv) nhvwaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLY> <q0nhv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nhvwaffleCap diff |
| |
| |
| DEVICE MN(nhv) nhvnormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 nhvnormGate MOSDIFFnotPOLYgate diff q1nhv nv_res |
| |
| DEVICE MN(nhv) nhvnormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhv> <MOSDIFFnotPOLYgate> <q0nhv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 nhvnormGate MOSDIFFnotPOLYgate diff q1nhv q0nhv nv_res |
| |
| |
| // TRACE PROPERTY MN(nhv) w w 1e-10 |
| // TRACE PROPERTY MN(nhv) l l 1e-10 |
| // TRACE PROPERTY MN(nhv) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MN nhv m mult w l |
| |
| |
| q45NDIFF_cond = NDIFF_cond NOT licon1 |
| q46NDIFF_cond = licon1 AND NDIFF_cond |
| q47NDIFF_cond = q45NDIFF_cond COINCIDENT EDGE nhvnative |
| q48NDIFF_cond = q45NDIFF_cond COINCIDENT EDGE q46NDIFF_cond |
| q49NDIFF_cond = INTERNAL q47NDIFF_cond q48NDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q50NDIFF_cond = q49NDIFF_cond INSIDE NDIFF_cond |
| q51NDIFF_cond = SIZE diff BY -0.005 |
| q52NDIFF_cond = q50NDIFF_cond AND q51NDIFF_cond |
| q53NDIFF_cond = q52NDIFF_cond NOT licon1 |
| q0nhvnative = q53NDIFF_cond NOT (INTERACT q53NDIFF_cond licon1 > 1) |
| q15diffTap = diffTap NOT nhvnative |
| q16diffTap = q15diffTap COINCIDENT EDGE nhvnative |
| q17diffTap = EXPAND EDGE q16diffTap INSIDE BY 0.005 |
| q1nhvnative = (SIZE q17diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR nhvnative |
| |
| DEVICE MN(nhvnative) nhvnativefixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nhvnativefixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MN(nhvnative) nhvnativefixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLY> <q0nhvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nhvnativefixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MN(nhvnative) nhvnativehalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 nhvnativehalfFieldless MOSDIFFnotPOLY diff q1nhvnative nv_res |
| |
| DEVICE MN(nhvnative) nhvnativehalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLY> <q0nhvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 nhvnativehalfFieldless MOSDIFFnotPOLY diff q1nhvnative q0nhvnative nv_res |
| |
| |
| DEVICE MN(nhvnative) nhvnativedrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 nhvnativedrainOnly NDIFF_cond diff q1nhvnative nv_res |
| |
| DEVICE MN(nhvnative) nhvnativedrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLY> <q0nhvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 nhvnativedrainOnly NDIFF_cond diff q1nhvnative q0nhvnative nv_res |
| |
| |
| // TRACE PROPERTY drainOnly(nhvnative) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(nhvnative) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(nhvnative) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly nhvnative m mult w l |
| |
| |
| DEVICE MN(nhvnative) nhvnativewaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nhvnativewaffleCap diff |
| |
| DEVICE MN(nhvnative) nhvnativewaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLY> <q0nhvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nhvnativewaffleCap diff |
| |
| |
| DEVICE MN(nhvnative) nhvnativenormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 nhvnativenormGate MOSDIFFnotPOLYgate diff q1nhvnative nv_res |
| |
| DEVICE MN(nhvnative) nhvnativenormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1nhvnative> <MOSDIFFnotPOLYgate> <q0nhvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 nhvnativenormGate MOSDIFFnotPOLYgate diff q1nhvnative q0nhvnative nv_res |
| |
| |
| // TRACE PROPERTY MN(nhvnative) w w 1e-10 |
| // TRACE PROPERTY MN(nhvnative) l l 1e-10 |
| // TRACE PROPERTY MN(nhvnative) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MN nhvnative m mult w l |
| |
| |
| q54NDIFF_cond = NDIFF_cond NOT licon1 |
| q55NDIFF_cond = licon1 AND NDIFF_cond |
| q56NDIFF_cond = q54NDIFF_cond COINCIDENT EDGE ntvnative |
| q57NDIFF_cond = q54NDIFF_cond COINCIDENT EDGE q55NDIFF_cond |
| q58NDIFF_cond = INTERNAL q56NDIFF_cond q57NDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q59NDIFF_cond = q58NDIFF_cond INSIDE NDIFF_cond |
| q60NDIFF_cond = SIZE diff BY -0.005 |
| q61NDIFF_cond = q59NDIFF_cond AND q60NDIFF_cond |
| q62NDIFF_cond = q61NDIFF_cond NOT licon1 |
| q0ntvnative = q62NDIFF_cond NOT (INTERACT q62NDIFF_cond licon1 > 1) |
| q18diffTap = diffTap NOT ntvnative |
| q19diffTap = q18diffTap COINCIDENT EDGE ntvnative |
| q20diffTap = EXPAND EDGE q19diffTap INSIDE BY 0.005 |
| q1ntvnative = (SIZE q20diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR ntvnative |
| |
| DEVICE MN(ntvnative) ntvnativefixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox ntvnativefixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MN(ntvnative) ntvnativefixedBlackBox POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLY> <q0ntvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox ntvnativefixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MN(ntvnative) ntvnativehalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 ntvnativehalfFieldless MOSDIFFnotPOLY diff q1ntvnative nv_res |
| |
| DEVICE MN(ntvnative) ntvnativehalfFieldless POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLY> <q0ntvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 ntvnativehalfFieldless MOSDIFFnotPOLY diff q1ntvnative q0ntvnative nv_res |
| |
| |
| DEVICE MN(ntvnative) ntvnativedrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 ntvnativedrainOnly NDIFF_cond diff q1ntvnative nv_res |
| |
| DEVICE MN(ntvnative) ntvnativedrainOnly POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLY> <q0ntvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 ntvnativedrainOnly NDIFF_cond diff q1ntvnative q0ntvnative nv_res |
| |
| |
| // TRACE PROPERTY drainOnly(ntvnative) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(ntvnative) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(ntvnative) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly ntvnative m mult w l |
| |
| |
| DEVICE MN(ntvnative) ntvnativewaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle ntvnativewaffleCap diff |
| |
| DEVICE MN(ntvnative) ntvnativewaffleCap POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLY> <q0ntvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle ntvnativewaffleCap diff |
| |
| |
| DEVICE MN(ntvnative) ntvnativenormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 ntvnativenormGate MOSDIFFnotPOLYgate diff q1ntvnative nv_res |
| |
| DEVICE MN(ntvnative) ntvnativenormGate POLY_cond(g) NDIFF_cond(s) NDIFF_cond(d) Substrate(b) <diff> <q1ntvnative> <MOSDIFFnotPOLYgate> <q0ntvnative> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 ntvnativenormGate MOSDIFFnotPOLYgate diff q1ntvnative q0ntvnative nv_res |
| |
| |
| // TRACE PROPERTY MN(ntvnative) w w 1e-10 |
| // TRACE PROPERTY MN(ntvnative) l l 1e-10 |
| // TRACE PROPERTY MN(ntvnative) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MN ntvnative m mult w l |
| |
| |
| q0PDIFF_cond = PDIFF_cond NOT licon1 |
| q1PDIFF_cond = licon1 AND PDIFF_cond |
| q2PDIFF_cond = q0PDIFF_cond COINCIDENT EDGE pshort |
| q3PDIFF_cond = q0PDIFF_cond COINCIDENT EDGE q1PDIFF_cond |
| q4PDIFF_cond = INTERNAL q2PDIFF_cond q3PDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q5PDIFF_cond = q4PDIFF_cond INSIDE PDIFF_cond |
| q6PDIFF_cond = SIZE diff BY -0.005 |
| q7PDIFF_cond = q5PDIFF_cond AND q6PDIFF_cond |
| q8PDIFF_cond = q7PDIFF_cond NOT licon1 |
| q0pshort = q8PDIFF_cond NOT (INTERACT q8PDIFF_cond licon1 > 1) |
| q21diffTap = diffTap NOT pshort |
| q22diffTap = q21diffTap COINCIDENT EDGE pshort |
| q23diffTap = EXPAND EDGE q22diffTap INSIDE BY 0.005 |
| q1pshort = (SIZE q23diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR pshort |
| |
| |
| DEVICE MP(pshort) pshortfixedBlackBox POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox pshortfixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MP(pshort) pshortfixedBlackBox POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLY> <q0pshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox pshortfixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MP(pshort) pshorthalfFieldless POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 pshorthalfFieldless MOSDIFFnotPOLY diff q1pshort p_res |
| |
| DEVICE MP(pshort) pshorthalfFieldless POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLY> <q0pshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 pshorthalfFieldless MOSDIFFnotPOLY diff q1pshort q0pshort p_res |
| |
| |
| DEVICE MP(pshort) pshortdrainOnly POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 pshortdrainOnly PDIFF_cond diff q1pshort p_res |
| |
| DEVICE MP(pshort) pshortdrainOnly POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLY> <q0pshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 pshortdrainOnly PDIFF_cond diff q1pshort q0pshort p_res |
| |
| |
| // TRACE PROPERTY drainOnly(pshort) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(pshort) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(pshort) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly pshort m mult w l |
| |
| |
| DEVICE MP(pshort) pshortwaffleCap POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle pshortwaffleCap diff |
| |
| DEVICE MP(pshort) pshortwaffleCap POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLY> <q0pshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle pshortwaffleCap diff |
| |
| |
| DEVICE MP(pshort) pshortnormGate POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 pshortnormGate MOSDIFFnotPOLYgate diff q1pshort p_res |
| |
| DEVICE MP(pshort) pshortnormGate POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1pshort> <MOSDIFFnotPOLYgate> <q0pshort> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 pshortnormGate MOSDIFFnotPOLYgate diff q1pshort q0pshort p_res |
| |
| |
| // TRACE PROPERTY MP(pshort) w w 1e-10 |
| // TRACE PROPERTY MP(pshort) l l 1e-10 |
| // TRACE PROPERTY MP(pshort) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MP pshort m mult w l |
| |
| // TRACE PROPERTY MP w w 1e-10 |
| // TRACE PROPERTY MP l l 1e-10 |
| // TRACE PROPERTY MP m m 0 |
| |
| CMACRO TRACE_MOS MP m mult w l |
| |
| |
| q9PDIFF_cond = PDIFF_cond NOT licon1 |
| q10PDIFF_cond = licon1 AND PDIFF_cond |
| q11PDIFF_cond = q9PDIFF_cond COINCIDENT EDGE PFET_01V8_HVT |
| q12PDIFF_cond = q9PDIFF_cond COINCIDENT EDGE q10PDIFF_cond |
| q13PDIFF_cond = INTERNAL q11PDIFF_cond q12PDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q14PDIFF_cond = q13PDIFF_cond INSIDE PDIFF_cond |
| q15PDIFF_cond = SIZE diff BY -0.005 |
| q16PDIFF_cond = q14PDIFF_cond AND q15PDIFF_cond |
| q17PDIFF_cond = q16PDIFF_cond NOT licon1 |
| q0phighvt = q17PDIFF_cond NOT (INTERACT q17PDIFF_cond licon1 > 1) |
| q24diffTap = diffTap NOT PFET_01V8_HVT |
| q25diffTap = q24diffTap COINCIDENT EDGE PFET_01V8_HVT |
| q26diffTap = EXPAND EDGE q25diffTap INSIDE BY 0.005 |
| q1phighvt = (SIZE q26diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR PFET_01V8_HVT |
| |
| |
| DEVICE MP(PFET_01V8_HVT) phighvtfixedBlackBox POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox phighvtfixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MP(PFET_01V8_HVT) phighvtfixedBlackBox POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLY> <q0phighvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox phighvtfixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MP(PFET_01V8_HVT) phighvthalfFieldless POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 phighvthalfFieldless MOSDIFFnotPOLY diff q1phighvt p_res |
| |
| DEVICE MP(PFET_01V8_HVT) phighvthalfFieldless POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLY> <q0phighvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 phighvthalfFieldless MOSDIFFnotPOLY diff q1phighvt q0phighvt p_res |
| |
| |
| DEVICE MP(PFET_01V8_HVT) phighvtdrainOnly POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 phighvtdrainOnly PDIFF_cond diff q1phighvt p_res |
| |
| DEVICE MP(PFET_01V8_HVT) phighvtdrainOnly POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLY> <q0phighvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 phighvtdrainOnly PDIFF_cond diff q1phighvt q0phighvt p_res |
| |
| |
| // TRACE PROPERTY drainOnly(PFET_01V8_HVT) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(PFET_01V8_HVT) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(PFET_01V8_HVT) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly PFET_01V8_HVT m mult w l |
| |
| |
| DEVICE MP(PFET_01V8_HVT) phighvtwaffleCap POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle phighvtwaffleCap diff |
| |
| DEVICE MP(PFET_01V8_HVT) phighvtwaffleCap POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLY> <q0phighvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle phighvtwaffleCap diff |
| |
| |
| // ;ss HAS THIS ONE |
| // M7 11 A1N vpwr vpb PFET_01V8_HVT L=0.15 W=0.42 AD=0.0441 AS=0.0986408 PD=0.63 PS=0.848873 NRD=23.443 NRS=84.3554 m=1 r=2.8 sa=0.845 sb=0.625 a=0.063 p=1.14 |
| |
| DEVICE MP(PFET_01V8_HVT) phighvtnormGate POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 phighvtnormGate MOSDIFFnotPOLYgate diff q1phighvt p_res |
| |
| |
| // M8 6 A2N 11 vpb PFET_01V8_HVT L=0.15 W=0.42 AD=0.1113 AS=0.0441 PD=1.37 PS=0.63 NRD=0 NRS=14.28 m=1 r=2.8 sa=1.205 sb=0.265 a=0.063 p=1.14 |
| // periminsidenrs=0 perimcoinnrs=0 sum_s_length=0 count_s=0 nrstmp=0.119 $X=1340 $Y=1485 $D=89 |
| |
| DEVICE MP(PFET_01V8_HVT) phighvtnormGate POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phighvt> <MOSDIFFnotPOLYgate> <q0phighvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 phighvtnormGate MOSDIFFnotPOLYgate diff q1phighvt q0phighvt p_res |
| |
| |
| // TRACE PROPERTY MP(PFET_01V8_HVT) w w 1e-10 |
| // TRACE PROPERTY MP(PFET_01V8_HVT) l l 1e-10 |
| // TRACE PROPERTY MP(PFET_01V8_HVT) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MP PFET_01V8_HVT m mult w l |
| |
| |
| q18PDIFF_cond = PDIFF_cond NOT licon1 |
| q19PDIFF_cond = licon1 AND PDIFF_cond |
| q20PDIFF_cond = q18PDIFF_cond COINCIDENT EDGE plowvt |
| q21PDIFF_cond = q18PDIFF_cond COINCIDENT EDGE q19PDIFF_cond |
| q22PDIFF_cond = INTERNAL q20PDIFF_cond q21PDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q23PDIFF_cond = q22PDIFF_cond INSIDE PDIFF_cond |
| q24PDIFF_cond = SIZE diff BY -0.005 |
| q25PDIFF_cond = q23PDIFF_cond AND q24PDIFF_cond |
| q26PDIFF_cond = q25PDIFF_cond NOT licon1 |
| q0plowvt = q26PDIFF_cond NOT (INTERACT q26PDIFF_cond licon1 > 1) |
| q27diffTap = diffTap NOT plowvt |
| q28diffTap = q27diffTap COINCIDENT EDGE plowvt |
| q29diffTap = EXPAND EDGE q28diffTap INSIDE BY 0.005 |
| q1plowvt = (SIZE q29diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR plowvt |
| |
| |
| DEVICE MP(plowvt) plowvtfixedBlackBox POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox plowvtfixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MP(plowvt) plowvtfixedBlackBox POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLY> <q0plowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox plowvtfixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MP(plowvt) plowvthalfFieldless POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 plowvthalfFieldless MOSDIFFnotPOLY diff q1plowvt p_res |
| |
| DEVICE MP(plowvt) plowvthalfFieldless POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLY> <q0plowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 plowvthalfFieldless MOSDIFFnotPOLY diff q1plowvt q0plowvt p_res |
| |
| |
| DEVICE MP(plowvt) plowvtdrainOnly POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 plowvtdrainOnly PDIFF_cond diff q1plowvt p_res |
| |
| DEVICE MP(plowvt) plowvtdrainOnly POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLY> <q0plowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 plowvtdrainOnly PDIFF_cond diff q1plowvt q0plowvt p_res |
| |
| |
| // TRACE PROPERTY drainOnly(plowvt) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(plowvt) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(plowvt) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly plowvt m mult w l |
| |
| |
| DEVICE MP(plowvt) plowvtwaffleCap POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle plowvtwaffleCap diff |
| |
| DEVICE MP(plowvt) plowvtwaffleCap POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLY> <q0plowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle plowvtwaffleCap diff |
| |
| |
| DEVICE MP(plowvt) plowvtnormGate POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 plowvtnormGate MOSDIFFnotPOLYgate diff q1plowvt p_res |
| |
| DEVICE MP(plowvt) plowvtnormGate POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1plowvt> <MOSDIFFnotPOLYgate> <q0plowvt> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 plowvtnormGate MOSDIFFnotPOLYgate diff q1plowvt q0plowvt p_res |
| |
| |
| // TRACE PROPERTY MP(plowvt) w w 1e-10 |
| // TRACE PROPERTY MP(plowvt) l l 1e-10 |
| // TRACE PROPERTY MP(plowvt) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MP plowvt m mult w l |
| |
| |
| q27PDIFF_cond = PDIFF_cond NOT licon1 |
| q28PDIFF_cond = licon1 AND PDIFF_cond |
| q29PDIFF_cond = q27PDIFF_cond COINCIDENT EDGE phv |
| q30PDIFF_cond = q27PDIFF_cond COINCIDENT EDGE q28PDIFF_cond |
| q31PDIFF_cond = INTERNAL q29PDIFF_cond q30PDIFF_cond < 10 OPPOSITE PARALLEL REGION |
| q32PDIFF_cond = q31PDIFF_cond INSIDE PDIFF_cond |
| q33PDIFF_cond = SIZE diff BY -0.005 |
| q34PDIFF_cond = q32PDIFF_cond AND q33PDIFF_cond |
| q35PDIFF_cond = q34PDIFF_cond NOT licon1 |
| q0phv = q35PDIFF_cond NOT (INTERACT q35PDIFF_cond licon1 > 1) |
| q30diffTap = diffTap NOT phv |
| q31diffTap = q30diffTap COINCIDENT EDGE phv |
| q32diffTap = EXPAND EDGE q31diffTap INSIDE BY 0.005 |
| q1phv = (SIZE q32diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR phv |
| |
| |
| DEVICE MP(phv) phvfixedBlackBox POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox phvfixedBlackBox MOSDIFFnotPOLY |
| |
| DEVICE MP(phv) phvfixedBlackBox POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLY> <q0phv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox phvfixedBlackBox MOSDIFFnotPOLY |
| |
| |
| DEVICE MP(phv) phvhalfFieldless POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 phvhalfFieldless MOSDIFFnotPOLY diff q1phv pv_res |
| |
| DEVICE MP(phv) phvhalfFieldless POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLY> <q0phv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 phvhalfFieldless MOSDIFFnotPOLY diff q1phv q0phv pv_res |
| |
| |
| DEVICE MP(phv) phvdrainOnly POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 phvdrainOnly PDIFF_cond diff q1phv pv_res |
| |
| DEVICE MP(phv) phvdrainOnly POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLY> <q0phv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 phvdrainOnly PDIFF_cond diff q1phv q0phv pv_res |
| |
| |
| // TRACE PROPERTY drainOnly(phv) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(phv) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(phv) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly phv m mult w l |
| |
| |
| DEVICE MP(phv) phvwaffleCap POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle phvwaffleCap diff |
| |
| DEVICE MP(phv) phvwaffleCap POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLY> <q0phv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle phvwaffleCap diff |
| |
| |
| DEVICE MP(phv) phvnormGate POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 phvnormGate MOSDIFFnotPOLYgate diff q1phv pv_res |
| |
| DEVICE MP(phv) phvnormGate POLY_cond(g) PDIFF_cond(s) PDIFF_cond(d) MosNwell(b) <diff> <q1phv> <MOSDIFFnotPOLYgate> <q0phv> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 phvnormGate MOSDIFFnotPOLYgate diff q1phv q0phv pv_res |
| |
| |
| // TRACE PROPERTY MP(phv) w w 1e-10 |
| // TRACE PROPERTY MP(phv) l l 1e-10 |
| // TRACE PROPERTY MP(phv) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MP phv m mult w l |
| |
| |
| q0bigesdGate = SIZE esdGate BY 0.005 |
| q0bigTermesdGate = q0bigesdGate AND MOSDIFFTAPESDnotPOLY |
| q0GATEadjesdGate = (INTERACT MOSDIFFTAPESDandPOLY polyGate) NOT polyGate |
| q0bigGATEdjesdGate = SIZE q0GATEadjesdGate BY 0.005 |
| q0bigGATEadjesdGate = INTERACT q0bigGATEdjesdGate q0bigTermesdGate == 1 |
| q1GATEadjesdGate = q0GATEadjesdGate AND q0bigGATEadjesdGate |
| MOSDIFFTAPESDnotPOLYgate = MOSDIFFTAPESDnotPOLY OR q1GATEadjesdGate |
| q1bigesdGate = SIZE esdGate BY 0.005 |
| q1bigTermesdGate = q1bigesdGate AND PMOSDIFFTAPESDnotPOLY |
| q2GATEadjesdGate = (INTERACT PMOSDIFFTAPESDandPOLY polyGate) NOT polyGate |
| q1bigGATEdjesdGate = SIZE q2GATEadjesdGate BY 0.005 |
| q1bigGATEadjesdGate = INTERACT q1bigGATEdjesdGate q1bigTermesdGate == 1 |
| q3GATEadjesdGate = q2GATEadjesdGate AND q1bigGATEadjesdGate |
| PMOSDIFFTAPESDnotPOLYgate = PMOSDIFFTAPESDnotPOLY OR q3GATEadjesdGate |
| q0NFOM_cond = NFOM_cond NOT licon1 |
| q1NFOM_cond = licon1 AND NFOM_cond |
| q2NFOM_cond = q0NFOM_cond COINCIDENT EDGE nshortesd |
| q3NFOM_cond = q0NFOM_cond COINCIDENT EDGE q1NFOM_cond |
| q4NFOM_cond = INTERNAL q2NFOM_cond q3NFOM_cond < 10 OPPOSITE PARALLEL REGION |
| q5NFOM_cond = q4NFOM_cond INSIDE NFOM_cond |
| q6NFOM_cond = SIZE diffESDtap BY -0.005 |
| q7NFOM_cond = q5NFOM_cond AND q6NFOM_cond |
| q8NFOM_cond = q7NFOM_cond NOT licon1 |
| q0nshortesd = q8NFOM_cond NOT (INTERACT q8NFOM_cond licon1 > 1) |
| q33diffTap = diffTap NOT nshortesd |
| q34diffTap = q33diffTap COINCIDENT EDGE nshortesd |
| q35diffTap = EXPAND EDGE q34diffTap INSIDE BY 0.005 |
| q1nshortesd = (SIZE q35diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR nshortesd |
| |
| DEVICE MN(nshortesd) nshortesdfixedBlackBox POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nshortesdfixedBlackBox MOSDIFFTAPESDnotPOLY |
| |
| DEVICE MN(nshortesd) nshortesdfixedBlackBox POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLY> <q0nshortesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nshortesdfixedBlackBox MOSDIFFTAPESDnotPOLY |
| |
| |
| DEVICE MN(nshortesd) nshortesdhalfFieldless POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 nshortesdhalfFieldless MOSDIFFTAPESDnotPOLY diffESDtap q1nshortesd n_res |
| |
| DEVICE MN(nshortesd) nshortesdhalfFieldless POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLY> <q0nshortesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 nshortesdhalfFieldless MOSDIFFTAPESDnotPOLY diffESDtap q1nshortesd q0nshortesd n_res |
| |
| |
| DEVICE MP(nshortesd) nshortesddrainOnly POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 nshortesddrainOnly NFOM_cond diffESDtap q1nshortesd n_res |
| |
| DEVICE MP(nshortesd) nshortesddrainOnly POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLY> <q0nshortesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 nshortesddrainOnly NFOM_cond diffESDtap q1nshortesd q0nshortesd n_res |
| |
| |
| // TRACE PROPERTY drainOnly(nshortesd) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(nshortesd) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(nshortesd) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly nshortesd m mult w l |
| |
| |
| DEVICE MN(nshortesd) nshortesdwaffleCap POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nshortesdwaffleCap diffESDtap |
| |
| DEVICE MN(nshortesd) nshortesdwaffleCap POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLY> <q0nshortesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nshortesdwaffleCap diffESDtap |
| |
| |
| DEVICE MN(nshortesd) nshortesdnormGate POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 nshortesdnormGate MOSDIFFTAPESDnotPOLYgate diffESDtap q1nshortesd n_res |
| |
| DEVICE MN(nshortesd) nshortesdnormGate POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nshortesd> <MOSDIFFTAPESDnotPOLYgate> <q0nshortesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 nshortesdnormGate MOSDIFFTAPESDnotPOLYgate diffESDtap q1nshortesd q0nshortesd n_res |
| |
| |
| // TRACE PROPERTY MN(nshortesd) w w 1e-10 |
| // TRACE PROPERTY MN(nshortesd) l l 1e-10 |
| // TRACE PROPERTY MN(nshortesd) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MN nshortesd m mult w l |
| |
| |
| q9NFOM_cond = NFOM_cond NOT licon1 |
| q10NFOM_cond = licon1 AND NFOM_cond |
| q11NFOM_cond = q9NFOM_cond COINCIDENT EDGE nhvesd |
| q12NFOM_cond = q9NFOM_cond COINCIDENT EDGE q10NFOM_cond |
| q13NFOM_cond = INTERNAL q11NFOM_cond q12NFOM_cond < 10 OPPOSITE PARALLEL REGION |
| q14NFOM_cond = q13NFOM_cond INSIDE NFOM_cond |
| q15NFOM_cond = SIZE diffESDtap BY -0.005 |
| q16NFOM_cond = q14NFOM_cond AND q15NFOM_cond |
| q17NFOM_cond = q16NFOM_cond NOT licon1 |
| q0nhvesd = q17NFOM_cond NOT (INTERACT q17NFOM_cond licon1 > 1) |
| q36diffTap = diffTap NOT nhvesd |
| q37diffTap = q36diffTap COINCIDENT EDGE nhvesd |
| q38diffTap = EXPAND EDGE q37diffTap INSIDE BY 0.005 |
| q1nhvesd = (SIZE q38diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR nhvesd |
| |
| DEVICE MN(nhvesd) nhvesdfixedBlackBox POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nhvesdfixedBlackBox MOSDIFFTAPESDnotPOLY |
| |
| DEVICE MN(nhvesd) nhvesdfixedBlackBox POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLY> <q0nhvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nhvesdfixedBlackBox MOSDIFFTAPESDnotPOLY |
| |
| |
| DEVICE MN(nhvesd) nhvesdhalfFieldless POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 nhvesdhalfFieldless MOSDIFFTAPESDnotPOLY diffESDtap q1nhvesd nv_res |
| |
| DEVICE MN(nhvesd) nhvesdhalfFieldless POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLY> <q0nhvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 nhvesdhalfFieldless MOSDIFFTAPESDnotPOLY diffESDtap q1nhvesd q0nhvesd nv_res |
| |
| |
| DEVICE MN(nhvesd) nhvesddrainOnly POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 nhvesddrainOnly NFOM_cond diffESDtap q1nhvesd nv_res |
| |
| DEVICE MN(nhvesd) nhvesddrainOnly POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLY> <q0nhvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 nhvesddrainOnly NFOM_cond diffESDtap q1nhvesd q0nhvesd nv_res |
| |
| |
| // TRACE PROPERTY drainOnly(nhvesd) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(nhvesd) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(nhvesd) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly nhvesd m mult w l |
| |
| |
| |
| DEVICE MN(nhvesd) nhvesdwaffleCap POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nhvesdwaffleCap diffESDtap |
| |
| DEVICE MN(nhvesd) nhvesdwaffleCap POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLY> <q0nhvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nhvesdwaffleCap diffESDtap |
| |
| |
| DEVICE MN(nhvesd) nhvesdnormGate POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 nhvesdnormGate MOSDIFFTAPESDnotPOLYgate diffESDtap q1nhvesd nv_res |
| |
| DEVICE MN(nhvesd) nhvesdnormGate POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvesd> <MOSDIFFTAPESDnotPOLYgate> <q0nhvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 nhvesdnormGate MOSDIFFTAPESDnotPOLYgate diffESDtap q1nhvesd q0nhvesd nv_res |
| |
| |
| // TRACE PROPERTY MN(nhvesd) w w 1e-10 |
| // TRACE PROPERTY MN(nhvesd) l l 1e-10 |
| // TRACE PROPERTY MN(nhvesd) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MN nhvesd m mult w l |
| |
| |
| q18NFOM_cond = NFOM_cond NOT licon1 |
| q19NFOM_cond = licon1 AND NFOM_cond |
| q20NFOM_cond = q18NFOM_cond COINCIDENT EDGE nhvnativeesd |
| q21NFOM_cond = q18NFOM_cond COINCIDENT EDGE q19NFOM_cond |
| q22NFOM_cond = INTERNAL q20NFOM_cond q21NFOM_cond < 10 OPPOSITE PARALLEL REGION |
| q23NFOM_cond = q22NFOM_cond INSIDE NFOM_cond |
| q24NFOM_cond = SIZE diffESDtap BY -0.005 |
| q25NFOM_cond = q23NFOM_cond AND q24NFOM_cond |
| q26NFOM_cond = q25NFOM_cond NOT licon1 |
| q0nhvnativeesd = q26NFOM_cond NOT (INTERACT q26NFOM_cond licon1 > 1) |
| q39diffTap = diffTap NOT nhvnativeesd |
| q40diffTap = q39diffTap COINCIDENT EDGE nhvnativeesd |
| q41diffTap = EXPAND EDGE q40diffTap INSIDE BY 0.005 |
| q1nhvnativeesd = (SIZE q41diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR nhvnativeesd |
| |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesdfixedBlackBox POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nhvnativeesdfixedBlackBox MOSDIFFTAPESDnotPOLY |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesdfixedBlackBox POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLY> <q0nhvnativeesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox nhvnativeesdfixedBlackBox MOSDIFFTAPESDnotPOLY |
| |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesdhalfFieldless POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 nhvnativeesdhalfFieldless MOSDIFFTAPESDnotPOLY diffESDtap q1nhvnativeesd nv_res |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesdhalfFieldless POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLY> <q0nhvnativeesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 nhvnativeesdhalfFieldless MOSDIFFTAPESDnotPOLY diffESDtap q1nhvnativeesd q0nhvnativeesd nv_res |
| |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesddrainOnly POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 nhvnativeesddrainOnly NFOM_cond diffESDtap q1nhvnativeesd nv_res |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesddrainOnly POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLY> <q0nhvnativeesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 nhvnativeesddrainOnly NFOM_cond diffESDtap q1nhvnativeesd q0nhvnativeesd nv_res |
| |
| |
| // TRACE PROPERTY drainOnly(nhvnativeesd) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(nhvnativeesd) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(nhvnativeesd) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly nhvnativeesd m mult w l |
| |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesdwaffleCap POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nhvnativeesdwaffleCap diffESDtap |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesdwaffleCap POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLY> <q0nhvnativeesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle nhvnativeesdwaffleCap diffESDtap |
| |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesdnormGate POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 nhvnativeesdnormGate MOSDIFFTAPESDnotPOLYgate diffESDtap q1nhvnativeesd nv_res |
| |
| DEVICE MN(nhvnativeesd) nhvnativeesdnormGate POLY_cond(g) NFOM_cond(s) NFOM_cond(d) Substrate(b) <diffESDtap> <q1nhvnativeesd> <MOSDIFFTAPESDnotPOLYgate> <q0nhvnativeesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 nhvnativeesdnormGate MOSDIFFTAPESDnotPOLYgate diffESDtap q1nhvnativeesd q0nhvnativeesd nv_res |
| |
| |
| // TRACE PROPERTY MN(nhvnativeesd) w w 1e-10 |
| // TRACE PROPERTY MN(nhvnativeesd) l l 1e-10 |
| // TRACE PROPERTY MN(nhvnativeesd) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MN nhvnativeesd m mult w l |
| |
| |
| q0PFOM_cond = PFOM_cond NOT licon1 |
| q1PFOM_cond = licon1 AND PFOM_cond |
| q2PFOM_cond = q0PFOM_cond COINCIDENT EDGE phvesd |
| q3PFOM_cond = q0PFOM_cond COINCIDENT EDGE q1PFOM_cond |
| q4PFOM_cond = INTERNAL q2PFOM_cond q3PFOM_cond < 10 OPPOSITE PARALLEL REGION |
| q5PFOM_cond = q4PFOM_cond INSIDE PFOM_cond |
| q6PFOM_cond = SIZE pdiffESDtap BY -0.005 |
| q7PFOM_cond = q5PFOM_cond AND q6PFOM_cond |
| q8PFOM_cond = q7PFOM_cond NOT licon1 |
| q0phvesd = q8PFOM_cond NOT (INTERACT q8PFOM_cond licon1 > 1) |
| q42diffTap = diffTap NOT phvesd |
| q43diffTap = q42diffTap COINCIDENT EDGE phvesd |
| q44diffTap = EXPAND EDGE q43diffTap INSIDE BY 0.005 |
| q1phvesd = (SIZE q44diffTap BY (20.0 - 0.005) INSIDE OF diffTap) OR phvesd |
| |
| |
| DEVICE MP(phvesd) phvesdfixedBlackBox POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox phvesdfixedBlackBox PMOSDIFFTAPESDnotPOLY |
| |
| DEVICE MP(phvesd) phvesdfixedBlackBox POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLY> <q0phvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_BlackBox phvesdfixedBlackBox PMOSDIFFTAPESDnotPOLY |
| |
| |
| DEVICE MP(phvesd) phvesdhalfFieldless POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField1 phvesdhalfFieldless PMOSDIFFTAPESDnotPOLY pdiffESDtap q1phvesd pv_res |
| |
| DEVICE MP(phvesd) phvesdhalfFieldless POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLY> <q0phvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_halfField2 phvesdhalfFieldless PMOSDIFFTAPESDnotPOLY pdiffESDtap q1phvesd q0phvesd pv_res |
| |
| |
| DEVICE MP(phvesd) phvesddrainOnly POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly1 phvesddrainOnly PFOM_cond pdiffESDtap q1phvesd pv_res |
| |
| DEVICE MP(phvesd) phvesddrainOnly POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLY> <q0phvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_drainOnly2 phvesddrainOnly PFOM_cond pdiffESDtap q1phvesd q0phvesd pv_res |
| |
| |
| // TRACE PROPERTY drainOnly(phvesd) udef_a udef_a 1 |
| // TRACE PROPERTY drainOnly(phvesd) udef_p udef_p 1 |
| // TRACE PROPERTY drainOnly(phvesd) m m 0 |
| |
| // CMACRO TRACE_MOS_ELEMENT drainOnly phvesd m mult w l |
| |
| |
| DEVICE MP(phvesd) phvesdwaffleCap POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLY> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle phvesdwaffleCap pdiffESDtap |
| |
| DEVICE MP(phvesd) phvesdwaffleCap POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLY> <q0phvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_Waffle phvesdwaffleCap pdiffESDtap |
| |
| |
| DEVICE MP(phvesd) phvesdnormGate POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLYgate> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate1 phvesdnormGate PMOSDIFFTAPESDnotPOLYgate pdiffESDtap q1phvesd pv_res |
| |
| DEVICE MP(phvesd) phvesdnormGate POLY_cond(g) PFOM_cond(s) PFOM_cond(d) MosNwell(b) <pdiffESDtap> <q1phvesd> <PMOSDIFFTAPESDnotPOLYgate> <q0phvesd> ("s" "d") BY NET NETLIST ELEMENT "M" TEXT MODEL LAYER polyModel |
| CMACRO MOS_normGate2 phvesdnormGate PMOSDIFFTAPESDnotPOLYgate pdiffESDtap q1phvesd q0phvesd pv_res |
| |
| |
| // TRACE PROPERTY MP(phvesd) w w 1e-10 |
| // TRACE PROPERTY MP(phvesd) l l 1e-10 |
| // TRACE PROPERTY MP(phvesd) m m 0 |
| |
| CMACRO TRACE_MOS_ELEMENT MP phvesd m mult w l |
| |
| |
| condiode = EXPAND TEXT condiode textdraw BY 0.001 |
| condiodeHvPsub = EXPAND TEXT condiodeHvPsub textdraw BY 0.001 |
| extdFets = nfetExtDr20 OR (nfetExtDr20iso OR pfetExtDr20) |
| //exemptDnwell = ENID OR (DiodeID OR (PHdiodeID OR (npn OR (pwres OR pnp)))) |
| exemptDnwell = ENID OR (DiodeID OR (PHdiodeID OR (npn OR (pwres OR (pnp OR extdFets))))) |
| |
| //;;This algorithm is overkill, but need to protect agains outer nwellGR screwing up derivations finds isoPwells and HvDnwell based on nwellRings |
| isoPwellBasic = NOT INTERACT ((INTERACT dnwelldg nwell) NOT nwell) EXTDRAIN20 |
| dnwNOTnw = dnwell NOT nwell |
| nwHoleNoNW = nwellHole NOT nwell |
| nwHoleOutsideDNW = XOR nwHoleNoNW dnwNOTnw |
| dnwToRemoveIsoPW = INTERACT dnwNOTnw nwHoleOutsideDNW |
| isoPwell = isoPwellBasic NOT dnwToRemoveIsoPW |
| |
| isoPwellEdge = COINCIDENT EDGE (nwellHole NOT nwellRing) isoPwellBasic |
| nwellInNWhole = (nwell AND dnwell) AND nwellHole |
| dnwellNotNw = INTERACT (dnwelldg NOT nwell) pwbm |
| dnwellOutsidePw = COINCIDENT EDGE (dnwellNotNw OR nwellHole) isoPwellBasic |
| dnwellOutNotIn = NOT COINCIDENT EDGE dnwellOutsidePw isoPwellEdge |
| dnwellOutNw = EXPAND EDGE dnwellOutNotIn OUTSIDE BY 0.005 |
| dnwellExplicit = dnwell AND (INTERACT pwbm (NOT INTERACT EXTDRAIN20 poly)) |
| |
| //dnwellInsideNwell = dnwelldg INSIDE nwell |
| //isoPwell = (INTERACT dnwelldg nwell) NOT nwell |
| validHvDnwell = INTERACT dnwell (dnwellExplicit OR dnwellOutNw) |
| validDnwell = NOT INTERACT isoPwell exemptDnwell |
| BadDnwell = NOT INTERACT (validDnwell NOT nwell) condiode |
| BadDnwell2 = NOT INTERACT condiode isoPwell |
| BadHvDnwell = NOT INTERACT validHvDnwell condiodeHvPsub |
| BadHvDnwell2 = NOT INTERACT condiodeHvPsub validHvDnwell |
| |
| DEVICE condiode condiode Substrate(pin0) DNWELL_cond(pin1) BY NET [ |
| PROPERTY a , p , m , ahftempperim |
| p = perimeter( condiode ) * L_scale |
| a = area( condiode ) * L_scale2 |
| m = 1 |
| ahftempperim = perimeter( condiode ) * L_scale |
| ] |
| |
| DEVICE condiodeHvPsub condiodeHvPsub SubstrateHVSpecial(pin0) DNWELL_cond(pin1) BY NET [ |
| PROPERTY a , p , m , ahftempperim |
| p = perimeter( condiodeHvPsub ) * L_scale |
| a = area( condiodeHvPsub ) * L_scale2 |
| m = 1 |
| ahftempperim = perimeter( condiodeHvPsub ) * L_scale |
| ] |
| |
| |
| LVS REDUCE condiode PARALLEL YES |
| LVS REDUCE condiodeHvPsub PARALLEL YES |
| |
| "r_561_Illegal condiode device" { |
| @ Illegal condiode device: validDnwell must overlap condiode |
| validDnwell OUTSIDE condiode |
| } |
| "r_562_condiode.err" { |
| @ condiode.err: dnwell must have condiode text |
| COPY BadDnwell |
| } |
| nwellENID = INTERACT nwell ENID |
| poly_hv = POLY_cond AND hvi |
| //allENIDgate = ENID AND (POLY_cond AND hvi) |
| allENIDgate = ENID AND poly_hv |
| pfetExtDrTmp = PUSH (allENIDgate AND dnwell) |
| nfetExtDrTmp = allENIDgate NOT dnwell |
| nfetExtDr = nfetExtDrTmp NOT nwellENID |
| pfetExtDr = PUSH (pfetExtDrTmp AND nwellENID) |
| pwellHole = HOLES nwellENID |
| nfetExtDrChecktmp = allENIDgate NOT nwellENID |
| nfetExtDrCheck = NOT INTERACT nfetExtDrChecktmp pwellHole |
| pfetExtENID = PUSH (ENID AND dnwell) |
| nfetExtENID = ENID NOT dnwell |
| deFETndrain = nwellENID ENCLOSE (NTAP_notbjt AND nfetExtENID) |
| deFETnsource = NDIFF_cond AND nfetExtENID |
| deFETpdrain = pwellHole ENCLOSE (PTAP_notbjt AND pfetExtENID) |
| deFETpsource = PDIFF_cond AND pfetExtENID |
| deFETndrainTerm = deFETndrain AND ENID |
| deFETpdrainTerm = deFETpdrain AND ENID |
| //CONNECT deFETndrain MosNwell |
| //CONNECT nfetExtDr POLY_cond |
| //CONNECT deFETpdrain PTAP_notbjt_cond |
| //CONNECT pfetExtDr POLY_cond |
| |
| //;vun adding 20V devices here |
| //;;base layers |
| extDR20gate = poly_hv AND EXTDRAIN20 |
| |
| pEXTDRAIN20gate = INTERACT extDR20gate pwde |
| nEXTDRAIN20gate = NOT extDR20gate pEXTDRAIN20gate |
| nExtDr20Nativegate = INSIDE nEXTDRAIN20gate lvtn |
| |
| nExtDR20gate = NOT nEXTDRAIN20gate nExtDr20Nativegate |
| //;;seed layers |
| nfetExtDr20Nativeiso = INSIDE nExtDr20Nativegate dnwell |
| nfetExtDr20Nativetmp = NOT nExtDr20Nativegate nfetExtDr20Nativeiso |
| diffInsidePWBMtmp = INSIDE diff pwbm |
| nfetExtDr20Native = NOT INTERACT nfetExtDr20Nativetmp diffInsidePWBMtmp |
| nfetExtDR20Zvt = INTERACT nfetExtDr20Nativetmp diffInsidePWBMtmp |
| nfetExtDr20iso = INSIDE nExtDR20gate dnwell |
| nfetExtDr20 = NOT nExtDR20gate nfetExtDr20iso |
| pfetExtDr20 = INSIDE pEXTDRAIN20gate dnwell |
| |
| //;;source layers |
| pExtDr20source = AND PDIFF_cond (AND EXTDRAIN20 dnwell) |
| nExtDr20source = AND NDIFF_cond EXTDRAIN20 |
| |
| //;;drain layers |
| extDr20drain = AND tap (AND dnwell EXTDRAIN20) |
| nExtDR20Draintmp = AND extDr20drain nwell |
| pExtDR20Draintmp = NOT extDr20drain nExtDR20Draintmp |
| |
| nExtDR20Drain = AND pwbm (INTERACT dnwell nExtDR20Draintmp) |
| pExtDR20Drain = AND pwbm (INTERACT pwde pExtDR20Draintmp) |
| |
| //;;terms for propery extraction |
| nExtDr20term = NOT nfetExtDr20 dnwell |
| nExtDr20Nativeterm = NOT nfetExtDr20Native dnwell |
| nExtDr20Zvtterm = NOT nfetExtDR20Zvt dnwell |
| nExtDr20isoterm = NOT nfetExtDr20iso diff |
| nExtDr20Nativeisoterm = NOT nfetExtDr20Nativeiso diff |
| pExtDr20term = NOT pfetExtDr20 pwde |
| |
| deFET20ndrainTerm = AND nExtDR20Drain EXTDRAIN20 |
| deFET20pdrainTerm = AND pExtDR20Drain EXTDRAIN20 |
| |
| //;;deFET20-niso has a seperat sort-pwell for its body connection |
| nfetExtDr20isolocalBody = AND dnwell (HOLES pwbm) |
| //;;check from the library |
| invalid_n20vhv1 = NOT nfetExtDr20 (EXTENT CELL "s8rf_n20vhv1*") |
| invalid_n20vhviso1 = NOT nfetExtDr20iso (EXTENT CELL "s8rf_n20vhviso1*") |
| invalid_n20vhvnativeiso1 = NOT nfetExtDr20Nativeiso (EXTENT CELL "s8rf_n20vhvnativeiso1*") |
| invalid_n20vhvnative1 = NOT nfetExtDr20Native (EXTENT CELL "s8rf_n20nativevhv1*") |
| invalid_n20vhvzvt1 = NOT nfetExtDr20Zvt (EXTENT CELL "s8rf_n20zvtvhv1*") |
| invalid_p20vhv1 = NOT pfetExtDr20 (EXTENT CELL "s8rf_p20vhv1*") |
| |
| CONNECT deFETndrain MosNwell |
| CONNECT nfetExtDr POLY_cond |
| CONNECT deFETpdrain PTAP_notbjt_cond |
| CONNECT pfetExtDr POLY_cond |
| CONNECT pfetExtDr20 POLY_cond |
| CONNECT nfetExtDr20 POLY_cond |
| CONNECT nfetExtDr20iso POLY_cond |
| CONNECT nfetExtDr20Native POLY_cond |
| CONNECT nfetExtDr20Zvt POLY_cond |
| CONNECT nfetExtDr20Nativeiso POLY_cond |
| CONNECT nfetExtDr20isolocalBody PTAP_defet20_cond |
| CONNECT nExtDr20drain MosNwell |
| CONNECT pExtDr20drain PTAP_defet20_cond |
| |
| |
| // ;ss match lvsRules |
| |
| "r_563_Illegal nvhv device nfetExtDrCheck must not overlap dnwell" { |
| @ Illegal nvhv device: nfetExtDrCheck must not overlap dnwell |
| nfetExtDrCheck AND dnwell |
| } |
| "r_564_Illegal nvhv device nfetExtDr must not overlap ncm" { |
| @ Illegal nvhv device: nfetExtDr must not overlap ncm |
| nfetExtDr AND ncm |
| } |
| "r_565_Illegal nvhv device nfetExtDr must not overlap dnwell" { |
| @ Illegal nvhv device: nfetExtDr must not overlap dnwell |
| nfetExtDr AND dnwell |
| } |
| "r_566_Illegal nvhv device nfetExtDr must not overlap tunm" { |
| @ Illegal nvhv device: nfetExtDr must not overlap tunm |
| nfetExtDr AND tunm |
| } |
| "r_567_Illegal nvhv device nfetExtDr must not overlap diffres" { |
| @ Illegal nvhv device: nfetExtDr must not overlap diffres |
| nfetExtDr AND diffres |
| } |
| "r_568_Illegal nvhv device nfetExtDr must not overlap diffcut" { |
| @ Illegal nvhv device: nfetExtDr must not overlap diffcut |
| nfetExtDr AND diffcut |
| } |
| "r_569_Illegal nvhv device nfetExtDr must not overlap npc" { |
| @ Illegal nvhv device: nfetExtDr must not overlap npc |
| nfetExtDr AND npc |
| } |
| "r_570_Illegal nvhv device nfetExtDr must not overlap polyres" { |
| @ Illegal nvhv device: nfetExtDr must not overlap polyres |
| nfetExtDr AND polyres |
| } |
| "r_571_Illegal nvhv device nfetExtDr must not overlap polycut" { |
| @ Illegal nvhv device: nfetExtDr must not overlap polycut |
| nfetExtDr AND polycut |
| } |
| "r_572_Illegal nvhv device nfetExtDr must not overlap li1res" { |
| @ Illegal nvhv device: nfetExtDr must not overlap li1res |
| nfetExtDr AND li1res |
| } |
| "r_573_Illegal nvhv device nfetExtDr must not overlap li1cut" { |
| @ Illegal nvhv device: nfetExtDr must not overlap li1cut |
| nfetExtDr AND li1cut |
| } |
| "r_574_Illegal nvhv device nfetExtDr must not overlap fuse" { |
| @ Illegal nvhv device: nfetExtDr must not overlap fuse |
| nfetExtDr AND fuse |
| } |
| "r_575_Illegal nvhv device nfetExtDr must not overlap psdm" { |
| @ Illegal nvhv device: nfetExtDr must not overlap psdm |
| nfetExtDr AND psdm |
| } |
| "r_576_Illegal nvhv device nfetExtDr must not overlap capacitor" { |
| @ Illegal nvhv device: nfetExtDr must not overlap capacitor |
| nfetExtDr AND capacitor |
| } |
| "r_577_Illegal nvhv device nfetExtDr must not overlap LVID" { |
| @ Illegal nvhv device: nfetExtDr must not overlap LVID |
| nfetExtDr AND LVID |
| } |
| "r_578_Illegal nvhv device nfetExtDr must not overlap hvtp" { |
| @ Illegal nvhv device: nfetExtDr must not overlap hvtp |
| nfetExtDr AND hvtp |
| } |
| "r_579_Illegal nvhv device nfetExtDr must not overlap lvtn" { |
| @ Illegal nvhv device: nfetExtDr must not overlap lvtn |
| nfetExtDr AND lvtn |
| } |
| "r_580_Illegal nvhv device nfetExtDr must not overlap pnp" { |
| @ Illegal nvhv device: nfetExtDr must not overlap pnp |
| nfetExtDr AND pnp |
| } |
| "r_581_Illegal nvhv device nfetExtDr must not overlap DiodeID" { |
| @ Illegal nvhv device: nfetExtDr must not overlap DiodeID |
| nfetExtDr AND DiodeID |
| } |
| "r_582_Illegal nvhv device nfetExtDr must not overlap COREID" { |
| @ Illegal nvhv device: nfetExtDr must not overlap COREID |
| nfetExtDr AND COREID |
| } |
| "r_583_Illegal nvhv device nfetExtDr must not overlap ESDID" { |
| @ Illegal nvhv device: nfetExtDr must not overlap ESDID |
| nfetExtDr AND ESDID |
| } |
| "r_584_Illegal nvhv device nfetExtDr must not overlap PHdiodeID" { |
| @ Illegal nvhv device: nfetExtDr must not overlap PHdiodeID |
| nfetExtDr AND PHdiodeID |
| } |
| "r_585_Illegal pvhv device pfetExtDr must not overlap ncm" { |
| @ Illegal pvhv device: pfetExtDr must not overlap ncm |
| pfetExtDr AND ncm |
| } |
| "r_586_Illegal pvhv device pfetExtDr must not overlap tunm" { |
| @ Illegal pvhv device: pfetExtDr must not overlap tunm |
| pfetExtDr AND tunm |
| } |
| "r_587_Illegal pvhv device pfetExtDr must not overlap diffres" { |
| @ Illegal pvhv device: pfetExtDr must not overlap diffres |
| pfetExtDr AND diffres |
| } |
| "r_588_Illegal pvhv device pfetExtDr must not overlap diffcut" { |
| @ Illegal pvhv device: pfetExtDr must not overlap diffcut |
| pfetExtDr AND diffcut |
| } |
| "r_589_Illegal pvhv device pfetExtDr must not overlap npc" { |
| @ Illegal pvhv device: pfetExtDr must not overlap npc |
| pfetExtDr AND npc |
| } |
| "r_590_Illegal pvhv device pfetExtDr must not overlap polyres" { |
| @ Illegal pvhv device: pfetExtDr must not overlap polyres |
| pfetExtDr AND polyres |
| } |
| "r_591_Illegal pvhv device pfetExtDr must not overlap polycut" { |
| @ Illegal pvhv device: pfetExtDr must not overlap polycut |
| pfetExtDr AND polycut |
| } |
| "r_592_Illegal pvhv device pfetExtDr must not overlap li1res" { |
| @ Illegal pvhv device: pfetExtDr must not overlap li1res |
| pfetExtDr AND li1res |
| } |
| "r_593_Illegal pvhv device pfetExtDr must not overlap li1cut" { |
| @ Illegal pvhv device: pfetExtDr must not overlap li1cut |
| pfetExtDr AND li1cut |
| } |
| "r_594_Illegal pvhv device pfetExtDr must not overlap fuse" { |
| @ Illegal pvhv device: pfetExtDr must not overlap fuse |
| pfetExtDr AND fuse |
| } |
| "r_595_Illegal pvhv device pfetExtDr must not overlap nsdm" { |
| @ Illegal pvhv device: pfetExtDr must not overlap nsdm |
| pfetExtDr AND nsdm |
| } |
| "r_596_Illegal pvhv device pfetExtDr must not overlap capacitor" { |
| @ Illegal pvhv device: pfetExtDr must not overlap capacitor |
| pfetExtDr AND capacitor |
| } |
| "r_597_Illegal pvhv device pfetExtDr must not overlap LVID" { |
| @ Illegal pvhv device: pfetExtDr must not overlap LVID |
| pfetExtDr AND LVID |
| } |
| "r_598_Illegal pvhv device pfetExtDr must not overlap hvtp" { |
| @ Illegal pvhv device: pfetExtDr must not overlap hvtp |
| pfetExtDr AND hvtp |
| } |
| "r_599_Illegal pvhv device pfetExtDr must not overlap lvtn" { |
| @ Illegal pvhv device: pfetExtDr must not overlap lvtn |
| pfetExtDr AND lvtn |
| } |
| "r_600_Illegal pvhv device pfetExtDr must not overlap pnp" { |
| @ Illegal pvhv device: pfetExtDr must not overlap pnp |
| pfetExtDr AND pnp |
| } |
| "r_601_Illegal pvhv device pfetExtDr must not overlap DiodeID" { |
| @ Illegal pvhv device: pfetExtDr must not overlap DiodeID |
| pfetExtDr AND DiodeID |
| } |
| "r_602_Illegal pvhv device pfetExtDr must not overlap COREID" { |
| @ Illegal pvhv device: pfetExtDr must not overlap COREID |
| pfetExtDr AND COREID |
| } |
| "r_603_Illegal pvhv device pfetExtDr must not overlap ESDID" { |
| @ Illegal pvhv device: pfetExtDr must not overlap ESDID |
| pfetExtDr AND ESDID |
| } |
| "r_604_Illegal pvhv device pfetExtDr must not overlap PHdiodeID" { |
| @ Illegal pvhv device: pfetExtDr must not overlap PHdiodeID |
| pfetExtDr AND PHdiodeID |
| } |
| |
| |
| // ;ss nvhv & pvhv: Just these 2 so no MACRO |
| // original lvsRules had no parasitcs for these two devices (which seems wrong) |
| |
| DEVICE nvhv nfetExtDr deFETndrain(pin0) nfetExtDr(pin1) deFETnsource(pin2) Substrate(pin3) <diff> <deFETndrainTerm> BY NET NETLIST MODEL nvhv NETLIST ELEMENT "X" [ |
| #IFDEF PEX |
| PROPERTY m, l, w, AS, AD, PS, PD, nrd, nrs, sa, sb , mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr , deFETnsource ) * L_scale |
| l = area( nfetExtDr ) * L_scale2 / w |
| coincidentWidth = perimeter_coincide( nfetExtDr , deFETnsource ) * L_scale |
| perimInsideS = perimeter_inside( deFETnsource , diff ) * L_scale |
| perimInsideD = perimeter_coincide( deFETndrain , deFETndrainTerm ) * L_scale |
| if (perimInsideS == 0) { |
| AS = 0 |
| PS = 0 |
| } else { |
| AS = (area( deFETnsource ) * L_scale2 * coincidentWidth) / perimInsideS |
| PS = (perimeter( deFETnsource ) * L_scale * coincidentWidth) / perimInsideS |
| } |
| if (perimInsideD == 0) { |
| AD = 0 |
| PD = 0 |
| } else { |
| AD = (area( deFETndrain ) * L_scale2 * coincidentWidth) / perimInsideD |
| PD = (perimeter( deFETndrain ) * L_scale * coincidentWidth) / perimInsideD |
| } |
| nrs = 0 |
| nrd = 0 |
| LODtmp = enclosure_vector( diff , 20.0 ) |
| SA = (SUM( LODtmp::A ) + SUM( LODtmp::B )) - (0.225) |
| SB = 1.585 |
| #ELSE |
| PROPERTY m, l, w, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr , deFETnsource ) * L_scale |
| l = area( nfetExtDr ) * L_scale2 / w |
| #ENDIF |
| ] |
| |
| // TRACE PROPERTY nvhv m m 0 |
| // TRACE PROPERTY nvhv l l 1 |
| // TRACE PROPERTY nvhv w w 1 |
| |
| CMACRO TRACE_MOS nvhv m mult w l |
| //gate_count = diff INTERACT nfetExtDr20 |
| gate_count = DFM PROPERTY nfetExtDr20 extDR20gate overlap ABUT ALSO MULTI |
| [num= 2] |
| |
| |
| DEVICE n20vhv1 nfetExtDr20 nExtDr20drain(pin0) nfetExtDr20(pin1) nExtDr20source(pin2) Substrate(pin3) <gate_count> <diff> <deFET20ndrainTerm> <nExtDr20term> BY NET NETLIST MODEL n20vhv1 NETLIST ELEMENT "X" [ |
| #IFDEF PEX |
| PROPERTY m, l, w, AS, AD, PS, PD, nrd, nrs, mult |
| m = 1 |
| mult = 1 |
| //mult = dfm_numeric_value(gate_count, num) |
| w = perimeter_coincide( nfetExtDr20 , nExtDr20source ) * L_scale |
| l = area( nExtDr20term ) * L_scale2 / w |
| coincidentWidth = perimeter_coincide( nfetExtDr20 , nExtDr20source ) * L_scale |
| perimInsideS = perimeter_inside( nExtDr20source , diff ) * L_scale |
| perimInsideD = perimeter_coincide( nExtDr20drain , deFET20ndrainTerm) * L_scale |
| if (perimInsideS == 0) { |
| AS = 0 |
| PS = 0 |
| } else { |
| AS = (area( nExtDr20source ) * L_scale2 * coincidentWidth) / perimInsideS |
| PS = (perimeter( nExtDr20source ) * L_scale * coincidentWidth) / perimInsideS |
| } |
| if (perimInsideD == 0) { |
| AD = 0 |
| PD = 0 |
| } else { |
| AD = (area( nExtDr20drain ) * L_scale2 * coincidentWidth) / perimInsideD |
| PD = (perimeter( nExtDr20drain ) * L_scale * coincidentWidth) / perimInsideD |
| } |
| nrs = 0 |
| nrd = 0 |
| #ELSE |
| PROPERTY m, l, w, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr20 , nExtDr20source ) * L_scale |
| l = area( nExtDr20term ) * L_scale2 / w |
| #ENDIF |
| ] |
| |
| CMACRO TRACE_MOS n20vhv1 m mult w l |
| |
| DEVICE n20nativevhv1 nfetExtDr20Native nExtDr20drain(pin0) nfetExtDr20Native(pin1) nExtDr20source(pin2) Substrate(pin3) <diff> <deFET20ndrainTerm> <nExtDr20Nativeterm> BY NET NETLIST MODEL n20nativevhv1 NETLIST ELEMENT "X" [ |
| #IFDEF PEX |
| PROPERTY m, l, w, AS, AD, PS, PD, nrd, nrs, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr20Native , nExtDr20source ) * L_scale |
| l = area( nExtDr20Nativeterm ) * L_scale2 / w |
| coincidentWidth = perimeter_coincide( nfetExtDr20Native , nExtDr20source ) * L_scale |
| perimInsideS = perimeter_inside( nExtDr20source , diff ) * L_scale |
| perimInsideD = perimeter_coincide( nExtDr20drain , deFET20ndrainTerm) * L_scale |
| if (perimInsideS == 0) { |
| AS = 0 |
| PS = 0 |
| } else { |
| AS = (area( nExtDr20source ) * L_scale2 * coincidentWidth) / perimInsideS |
| PS = (perimeter( nExtDr20source ) * L_scale * coincidentWidth) / perimInsideS |
| } |
| if (perimInsideD == 0) { |
| AD = 0 |
| PD = 0 |
| } else { |
| AD = (area( nExtDr20drain ) * L_scale2 * coincidentWidth) / perimInsideD |
| PD = (perimeter( nExtDr20drain ) * L_scale * coincidentWidth) / perimInsideD |
| } |
| nrs = 0 |
| nrd = 0 |
| #ELSE |
| PROPERTY m, l, w, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr20Native , nExtDr20source ) * L_scale |
| l = area( nExtDr20Nativeterm ) * L_scale2 / w |
| #ENDIF |
| ] |
| |
| CMACRO TRACE_MOS n20nativevhv1 m mult w l |
| |
| DEVICE n20vhviso1 nfetExtDr20iso nExtDr20drain(pin0) nfetExtDr20iso(pin1) nExtDr20source(pin2) nfetExtDr20isolocalBody(pin3) Substrate(pin4) <diff> <deFET20ndrainTerm> <nExtDr20isoterm> BY NET NETLIST MODEL n20vhviso1 NETLIST ELEMENT "X" [ |
| #IFDEF PEX |
| PROPERTY m, l, w, AS, AD, PS, PD, nrd, nrs, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr20iso , nExtDr20source ) * L_scale |
| l = area( nExtDr20isoterm ) * L_scale2 / w |
| coincidentWidth = perimeter_coincide( nfetExtDr20iso , nExtDr20source ) * L_scale |
| perimInsideS = perimeter_inside( nExtDr20source , diff ) * L_scale |
| perimInsideD = perimeter_coincide( nExtDr20drain , deFET20ndrainTerm) * L_scale |
| if (perimInsideS == 0) { |
| AS = 0 |
| PS = 0 |
| } else { |
| AS = (area( nExtDr20source ) * L_scale2 * coincidentWidth) / perimInsideS |
| PS = (perimeter( nExtDr20source ) * L_scale * coincidentWidth) / perimInsideS |
| } |
| if (perimInsideD == 0) { |
| AD = 0 |
| PD = 0 |
| } else { |
| AD = (area( nExtDr20drain ) * L_scale2 * coincidentWidth) / perimInsideD |
| PD = (perimeter( nExtDr20drain ) * L_scale * coincidentWidth) / perimInsideD |
| } |
| nrs = 0 |
| nrd = 0 |
| #ELSE |
| PROPERTY m, l, w, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr20iso , nExtDr20source ) * L_scale |
| l = area( nExtDr20isoterm ) * L_scale2 / w |
| #ENDIF |
| ] |
| |
| CMACRO TRACE_MOS n20vhviso1 m mult w l |
| |
| DEVICE n20nativevhviso1 nfetExtDr20Nativeiso nExtDr20drain(pin0) nfetExtDr20Nativeiso(pin1) nExtDr20source(pin2) nfetExtDr20isolocalBody(pin3) Substrate(pin4) <diff> <deFET20ndrainTerm> <nExtDr20Nativeisoterm> BY NET NETLIST MODEL n20nativevhviso1 NETLIST ELEMENT "X" [ |
| #IFDEF PEX |
| PROPERTY m, l, w, AS, AD, PS, PD, nrd, nrs, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr20Nativeiso , nExtDr20source ) * L_scale |
| l = area( nExtDr20Nativeisoterm ) * L_scale2 / w |
| coincidentWidth = perimeter_coincide( nfetExtDr20Nativeiso , nExtDr20source ) * L_scale |
| perimInsideS = perimeter_inside( nExtDr20source , diff ) * L_scale |
| perimInsideD = perimeter_coincide( nExtDr20drain , deFET20ndrainTerm) * L_scale |
| if (perimInsideS == 0) { |
| AS = 0 |
| PS = 0 |
| } else { |
| AS = (area( nExtDr20source ) * L_scale2 * coincidentWidth) / perimInsideS |
| PS = (perimeter( nExtDr20source ) * L_scale * coincidentWidth) / perimInsideS |
| } |
| if (perimInsideD == 0) { |
| AD = 0 |
| PD = 0 |
| } else { |
| AD = (area( nExtDr20drain ) * L_scale2 * coincidentWidth) / perimInsideD |
| PD = (perimeter( nExtDr20drain ) * L_scale * coincidentWidth) / perimInsideD |
| } |
| nrs = 0 |
| nrd = 0 |
| #ELSE |
| PROPERTY m, l, w, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( nfetExtDr20Nativeiso , nExtDr20source ) * L_scale |
| l = area( nExtDr20Nativeisoterm ) * L_scale2 / w |
| #ENDIF |
| ] |
| |
| CMACRO TRACE_MOS n20nativevhviso1 m mult w l |
| |
| DEVICE pvhv pfetExtDr deFETpdrain(pin0) pfetExtDr(pin1) deFETpsource(pin2) MosNwell(pin3) <diff> <deFETpdrainTerm> BY NET NETLIST MODEL pvhv NETLIST ELEMENT "X" [ |
| #IFDEF PEX |
| PROPERTY m, l, w, AS, AD, PS, PD, nrd, nrs, sa, sb , mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( pfetExtDr , deFETpsource ) * L_scale |
| l = area( pfetExtDr ) * L_scale2 / w |
| coincidentWidth = perimeter_coincide( pfetExtDr , deFETpsource ) * L_scale |
| perimInsideS = perimeter_inside( deFETpsource , diff ) * L_scale |
| perimInsideD = perimeter_coincide( deFETpdrain , deFETpdrainTerm ) * L_scale |
| if (perimInsideS == 0) { |
| AS = 0 |
| PS = 0 |
| } else { |
| AS = (area( deFETpsource ) * L_scale2 * coincidentWidth) / perimInsideS |
| PS = (perimeter( deFETpsource ) * L_scale * coincidentWidth) / perimInsideS |
| } |
| if (perimInsideD == 0) { |
| AD = 0 |
| PD = 0 |
| } else { |
| AD = (area( deFETpdrain ) * L_scale2 * coincidentWidth) / perimInsideD |
| PD = (perimeter( deFETpdrain ) * L_scale * coincidentWidth) / perimInsideD |
| } |
| nrs = 0 |
| nrd = 0 |
| LODtmp = enclosure_vector( diff , 20.0 ) |
| SA = (SUM( LODtmp::A ) + SUM( LODtmp::B )) - (0.26) |
| SB = 1.19 |
| #ELSE |
| PROPERTY m, l, w, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( pfetExtDr , deFETpsource ) * L_scale |
| l = area( pfetExtDr ) * L_scale2 / w |
| #ENDIF |
| ] |
| |
| // TRACE PROPERTY pvhv m m 0 |
| // TRACE PROPERTY pvhv l l 1 |
| // TRACE PROPERTY pvhv w w 1 |
| |
| CMACRO TRACE_MOS pvhv m mult w l |
| |
| DEVICE p20vhv1 pfetExtDr20 pExtDr20drain(pin0) pfetExtDr20(pin1) pExtDr20source(pin2) MosNwell(pin3) <diff> <deFET20pdrainTerm> <pExtDr20term> BY NET NETLIST MODEL p20vhv1 NETLIST ELEMENT "X" [ |
| #IFDEF PEX |
| PROPERTY m, l, w, AS, AD, PS, PD, nrd, nrs, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( pfetExtDr20 , pExtDr20source ) * L_scale |
| l = area( pExtDr20term ) * L_scale2 / w |
| coincidentWidth = perimeter_coincide( pfetExtDr20 , pExtDr20source ) * L_scale |
| perimInsideS = perimeter_inside( pExtDr20source , diff ) * L_scale |
| perimInsideD = perimeter_coincide( pExtDr20drain , deFET20pdrainTerm ) * L_scale |
| if (perimInsideS == 0) { |
| AS = 0 |
| PS = 0 |
| } else { |
| AS = (area( pExtDr20source ) * L_scale2 * coincidentWidth) / perimInsideS |
| PS = (perimeter( pExtDr20source ) * L_scale * coincidentWidth) / perimInsideS |
| } |
| if (perimInsideD == 0) { |
| AD = 0 |
| PD = 0 |
| } else { |
| AD = (area( pExtDr20drain ) * L_scale2 * coincidentWidth) / perimInsideD |
| PD = (perimeter( pExtDr20drain ) * L_scale * coincidentWidth) / perimInsideD |
| } |
| nrs = 0 |
| nrd = 0 |
| #ELSE |
| PROPERTY m, l, w, mult |
| m = 1 |
| mult = 1 |
| w = perimeter_coincide( pfetExtDr20 , pExtDr20source ) * L_scale |
| l = area( pExtDr20term ) * L_scale2 / w |
| #ENDIF |
| ] |
| |
| // TRACE PROPERTY pvhv m m 0 |
| // TRACE PROPERTY pvhv l l 1 |
| // TRACE PROPERTY pvhv w w 1 |
| |
| CMACRO TRACE_MOS p20vhv1 m mult w l |
| |
| |
| |
| INCLUDE "$PDK_HOME/PEX/xRC/s8_lvs_macros" |
| |
| |
| // ;sspex |
| |
| #IFDEF PEX |
| |
| CMACRO REDUCE_MOS_PEX p20vhv1 m w l AS AD PS PD NRD NRS mult |
| CMACRO REDUCE_MOS_PEX n20vhv1 m w l AS AD PS PD NRD NRS mult |
| CMACRO REDUCE_MOS_PEX n20vhviso1 m w l AS AD PS PD NRD NRS mult |
| CMACRO REDUCE_MOS_PEX nvhv m w l AS AD PS PD NRD NRS mult |
| CMACRO REDUCE_MOS_PEX pvhv m w l AS AD PS PD NRD NRS mult |
| CMACRO REDUCE_MOS_PEX MP m w l AS AD PS PD NRD NRS mult |
| CMACRO REDUCE_MOS_PEX M m w l AS AD PS PD NRD NRS mult |
| CMACRO REDUCE_MOS_PEX MN m w l AS AD PS PD NRD NRS mult |
| |
| LVS REDUCE SPLIT GATES YES [ |
| TOLERANCE l 1.0 |
| w 1.0 |
| EFFECTIVE m , w , l , AS , AD , PS , PD , NRD , NRS , mult |
| |
| new_m = SUM( m * mult ) |
| w = SUM( (w * m * mult) ) / new_m |
| l = SUM( (l * m * mult) ) / new_m |
| mult = 1 |
| m = new_m |
| |
| AS = SUM( (AS * m * mult) ) / new_m |
| AD = SUM( (AD * m * mult) ) / new_m |
| PS = SUM( (PS * m * mult) ) / new_m |
| PD = SUM( (PD * m * mult) ) / new_m |
| NRD = SUM( (NRD * m * mult) ) / new_m |
| NRS = SUM( (NRS * m * mult) ) / new_m |
| |
| ] |
| |
| #ELSE |
| |
| CMACRO REDUCE_MOS p20vhv1 m w l mult |
| CMACRO REDUCE_MOS n20vhv1 m w l mult |
| CMACRO REDUCE_MOS n20vhviso1 m w l mult |
| CMACRO REDUCE_MOS nvhv m w l mult |
| CMACRO REDUCE_MOS pvhv m w l mult |
| CMACRO REDUCE_MOS MP m w l mult |
| CMACRO REDUCE_MOS M m w l mult |
| CMACRO REDUCE_MOS MN m w l mult |
| |
| |
| LVS REDUCE SPLIT GATES YES [ |
| TOLERANCE l 1.0 |
| w 1.0 |
| EFFECTIVE m , w , l , mult |
| new_m = SUM( m * mult ) |
| w = SUM( (w * m * mult) ) / new_m |
| l = SUM( (l * m * mult) ) / new_m |
| mult = 1 |
| m = new_m |
| ] |
| |
| #ENDIF // PEX |
| |
| |
| DEVICE xcnwvc xcnwvc POLY_cond_nrc(pin0) NTAP_notbjt_cond(pin1) Substrate(pin2) <NTAP_notbjt> BY NET [ |
| PROPERTY w , l , m |
| m = 1 |
| a = area( xcnwvc ) * L_scale2 |
| p = perimeter( xcnwvc ) * L_scale |
| l = perimeter_coincide( xcnwvc , NTAP_notbjt ) * 0.5 * L_scale |
| w = a / l |
| ] |
| |
| TRACE PROPERTY xcnwvc m m 0 |
| TRACE PROPERTY xcnwvc w w 0 |
| TRACE PROPERTY xcnwvc l l 0 |
| |
| |
| DEVICE xcnwvc2 xcnwvc2 POLY_cond_nrc(pin0) NTAP_notbjt_cond(pin1) Substrate(pin2) <NTAP_notbjt> BY NET [ |
| PROPERTY w , l , m |
| m = 1 |
| a = area( xcnwvc2 ) * L_scale2 |
| p = perimeter( xcnwvc2 ) * L_scale |
| l = perimeter_coincide( xcnwvc2 , NTAP_notbjt ) * 0.5 * L_scale |
| w = a / l |
| ] |
| |
| TRACE PROPERTY xcnwvc2 m m 0 |
| TRACE PROPERTY xcnwvc2 w w 0 |
| TRACE PROPERTY xcnwvc2 l l 0 |
| |
| |
| DEVICE xchvnwc xchvnwc POLY_cond_nrc(pin0) NTAP_notbjt_cond(pin1) Substrate(pin2) <NTAP_notbjt> BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( xchvnwc ) * L_scale2 |
| p = perimeter( xchvnwc ) * L_scale |
| ] |
| |
| TRACE PROPERTY xchvnwc m m 0 |
| |
| |
| npnpar1x2 = INTERACT npn (AREA NPNDIFF_cond == 2) |
| npnpar1x1 = INTERACT npn (AREA NPNDIFF_cond == 1) |
| npn_1x1_2p0_HV = INTERACT npn (INSIDE CELL diff s8rf_npn_1x1_2p0_HV) |
| pnppar1x = INTERACT pnp (RECTANGLE PNPDIFF_COND == 0.68 ASPECT == 1) |
| pnppar5x = INTERACT pnp (RECTANGLE PNPDIFF_COND == 3.4 ASPECT == 1) |
| bad_npn1 = NOT INTERACT npn (npnpar1x2 OR |
| (npnpar1x1 OR npn_1x1_2p0_HV)) |
| bad_pnp1 = NOT INTERACT pnp (pnppar1x OR pnppar5x) |
| bad_npn2 = INTERACT npn NPNDIFF_cond > 1 |
| npncell = (EXTENT CELL "s8rf_npn_1x1") OR |
| ((EXTENT CELL "s8rf_npn_1x2") OR (EXTENT CELL "s8rf_npn_1x1_2p0_HV")) |
| SubstrateNpn = (nwell AND npncell) NOT npn |
| npn_not_s8rf_npn_1x1_2p0_HV = npn NOT (EXTENT CELL "s8rf_npn_1x1_2p0_HV") |
| npn_and_s8rf_npn_1x1_2p0_HV = npn AND (EXTENT CELL "s8rf_npn_1x1_2p0_HV") |
| CONNECT Substrate SubstrateNpn |
| |
| DEVICE Q(npnpar1x1) npnpar1x1 NTAP_npn_cond(C) PTAP_npn_cond(B) NPNDIFF_cond(E) SubstrateNpn(S) BY NET [ |
| PROPERTY m |
| m = 1 |
| ] |
| |
| LVS REDUCE Q(npnpar1x1) PARALLEL YES [ |
| EFFECTIVE m |
| m = SUM( m ) |
| ] |
| |
| TRACE PROPERTY Q(npnpar1x1) m m 0 |
| |
| DEVICE Q(npnpar1x2) npnpar1x2 NTAP_npn_cond(C) PTAP_npn_cond(B) NPNDIFF_cond(E) SubstrateNpn(S) BY NET [ |
| PROPERTY m |
| m = 1 |
| ] |
| |
| LVS REDUCE Q(npnpar1x2) PARALLEL YES [ |
| EFFECTIVE m |
| m = SUM( m ) |
| ] |
| |
| TRACE PROPERTY Q(npnpar1x2) m m 0 |
| |
| DEVICE Q(npn_1x1_2p0_hv) npn_1x1_2p0_HV NTAP_npn_cond(C) PTAP_npn_cond(B) NPNDIFF_cond(E) SubstrateNpn(S) BY NET [ |
| PROPERTY m |
| m = 1 |
| ] |
| |
| LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL YES [ |
| EFFECTIVE m |
| m = SUM( m ) |
| ] |
| |
| TRACE PROPERTY Q(npn_1x1_2p0_hv) m m 0 |
| |
| DEVICE Q(pnppar) pnppar1x PTAP_pnp_cond(C) PnpNwell(B) PNPDIFF_cond(E) Substrate(S) BY NET [ |
| PROPERTY bArea , bPeri , eArea , ePeri , m |
| m = 1 |
| eArea = area( E ) * L_scale2 |
| ePeri = perimeter( E ) * L_scale |
| bArea = area( B ) * L_scale2 |
| bPeri = perimeter( B ) * L_scale |
| ] |
| |
| // ;ss |
| // BJT devices have no default parameters |
| // need to tell what parameters to combine |
| |
| LVS REDUCE Q(pnppar) PARALLEL YES [ |
| TOLERANCE bArea 1 |
| bPeri 1 |
| eArea 1 |
| ePeri 1 |
| EFFECTIVE bArea , bPeri , eArea , ePeri , m |
| m = SUM( m ) |
| bArea = SUM( (bArea * m) ) / m |
| bPeri = SUM( (bPeri * m) ) / m |
| eArea = SUM( (eArea * m) ) / m |
| ePeri = SUM( (ePeri * m) ) / m |
| ] //LVS REDUCE PARALLEL BIPOLAR YES |
| |
| TRACE PROPERTY Q(pnppar) bArea bArea 0 |
| TRACE PROPERTY Q(pnppar) bPeri bPeri 0 |
| TRACE PROPERTY Q(pnppar) eArea eArea 0 |
| TRACE PROPERTY Q(pnppar) ePeri ePeri 0 |
| TRACE PROPERTY Q(pnppar) m m 0 |
| |
| DEVICE Q(pnppar5x) pnppar5x PTAP_pnp_cond(C) PnpNwell(B) PNPDIFF_cond(E) Substrate(S) BY NET [ |
| PROPERTY bArea , bPeri , eArea , ePeri , m |
| m = 1 |
| eArea = area( E ) * L_scale2 |
| ePeri = perimeter( E ) * L_scale |
| bArea = area( B ) * L_scale2 |
| bPeri = perimeter( B ) * L_scale |
| ] |
| |
| LVS REDUCE Q(pnppar5x) PARALLEL YES [ |
| TOLERANCE bArea 1 |
| bPeri 1 |
| eArea 1 |
| ePeri 1 |
| EFFECTIVE bArea , bPeri , eArea , ePeri , m |
| m = SUM( m ) |
| bArea = SUM( (bArea * m) ) / m |
| bPeri = SUM( (bPeri * m) ) / m |
| eArea = SUM( (eArea * m) ) / m |
| ePeri = SUM( (ePeri * m) ) / m |
| ] //LVS REDUCE PARALLEL BIPOLAR YES |
| |
| TRACE PROPERTY Q(pnppar5x) bArea bArea 0 |
| TRACE PROPERTY Q(pnppar5x) bPeri bPeri 0 |
| TRACE PROPERTY Q(pnppar5x) eArea eArea 0 |
| TRACE PROPERTY Q(pnppar5x) ePeri ePeri 0 |
| TRACE PROPERTY Q(pnppar5x) m m 0 |
| |
| |
| |
| // ;ss match lvsRules |
| |
| "r_605_bad npn" { |
| @ bad npn: unidentifiable npn device |
| COPY bad_npn1 |
| } |
| "r_606_bad pnp" { |
| @ bad pnp: unidentifiable pnp device |
| COPY bad_pnp1 |
| } |
| "r_607_bad npn" { |
| @ bad npn: npn ID layer cannot touch more than one npn device |
| COPY bad_npn2 |
| } |
| "r_608_Illegal pnppar device pnp must not overlap ncm" { |
| @ Illegal pnppar device: pnp must not overlap ncm |
| pnp AND ncm |
| } |
| "r_609_Illegal pnppar device pnp must not overlap dnwell" { |
| @ Illegal pnppar device: pnp must not overlap dnwell |
| pnp AND dnwell |
| } |
| "r_610_Illegal pnppar device pnp must not overlap diffres" { |
| @ Illegal pnppar device: pnp must not overlap diffres |
| pnp AND diffres |
| } |
| "r_611_Illegal pnppar device pnp must not overlap diffcut" { |
| @ Illegal pnppar device: pnp must not overlap diffcut |
| pnp AND diffcut |
| } |
| "r_612_Illegal pnppar device pnp must not overlap poly" { |
| @ Illegal pnppar device: pnp must not overlap poly |
| pnp AND poly |
| } |
| "r_613_Illegal pnppar device pnp must not overlap polyres" { |
| @ Illegal pnppar device: pnp must not overlap polyres |
| pnp AND polyres |
| } |
| "r_614_Illegal pnppar device pnp must not overlap polycut" { |
| @ Illegal pnppar device: pnp must not overlap polycut |
| pnp AND polycut |
| } |
| "r_615_Illegal pnppar device pnp must not overlap li1res" { |
| @ Illegal pnppar device: pnp must not overlap li1res |
| pnp AND li1res |
| } |
| "r_616_Illegal pnppar device pnp must not overlap li1cut" { |
| @ Illegal pnppar device: pnp must not overlap li1cut |
| pnp AND li1cut |
| } |
| "r_617_Illegal pnppar device pnp must not overlap fuse" { |
| @ Illegal pnppar device: pnp must not overlap fuse |
| pnp AND fuse |
| } |
| "r_618_Illegal pnppar device pnp must not overlap capacitor" { |
| @ Illegal pnppar device: pnp must not overlap capacitor |
| pnp AND capacitor |
| } |
| "r_619_Illegal pnppar device pnp must not overlap LVID" { |
| @ Illegal pnppar device: pnp must not overlap LVID |
| pnp AND LVID |
| } |
| "r_620_Illegal pnppar device pnp must not overlap ENID" { |
| @ Illegal pnppar device: pnp must not overlap ENID |
| pnp AND ENID |
| } |
| "r_621_Illegal pnppar device pnp must not overlap lvtn" { |
| @ Illegal pnppar device: pnp must not overlap lvtn |
| pnp AND lvtn |
| } |
| "r_622_Illegal pnppar device pnp must not overlap hvi" { |
| @ Illegal pnppar device: pnp must not overlap hvi |
| pnp AND hvi |
| } |
| "r_623_Illegal pnppar device pnp must not overlap DiodeID" { |
| @ Illegal pnppar device: pnp must not overlap DiodeID |
| pnp AND DiodeID |
| } |
| "r_624_Illegal pnppar device pnp must not overlap COREID" { |
| @ Illegal pnppar device: pnp must not overlap COREID |
| pnp AND COREID |
| } |
| "r_625_Illegal pnppar device pnp must not overlap ESDID" { |
| @ Illegal pnppar device: pnp must not overlap ESDID |
| pnp AND ESDID |
| } |
| "r_626_Illegal pnppar device pnp must not overlap PHdiodeID" { |
| @ Illegal pnppar device: pnp must not overlap PHdiodeID |
| pnp AND PHdiodeID |
| } |
| "r_627_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap ncm" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap ncm |
| npn_not_s8rf_npn_1x1_2p0_HV AND ncm |
| } |
| "r_628_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap diffres" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap diffres |
| npn_not_s8rf_npn_1x1_2p0_HV AND diffres |
| } |
| "r_629_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap diffcut" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap diffcut |
| npn_not_s8rf_npn_1x1_2p0_HV AND diffcut |
| } |
| "r_630_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap poly" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap poly |
| npn_not_s8rf_npn_1x1_2p0_HV AND poly |
| } |
| "r_631_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap polyres" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap polyres |
| npn_not_s8rf_npn_1x1_2p0_HV AND polyres |
| } |
| "r_632_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap polycut" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap polycut |
| npn_not_s8rf_npn_1x1_2p0_HV AND polycut |
| } |
| "r_633_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap li1res" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap li1res |
| npn_not_s8rf_npn_1x1_2p0_HV AND li1res |
| } |
| "r_634_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap li1cut" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap li1cut |
| npn_not_s8rf_npn_1x1_2p0_HV AND li1cut |
| } |
| "r_635_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap fuse" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap fuse |
| npn_not_s8rf_npn_1x1_2p0_HV AND fuse |
| } |
| "r_636_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap capacitor" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap capacitor |
| npn_not_s8rf_npn_1x1_2p0_HV AND capacitor |
| } |
| "r_637_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap LVID" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap LVID |
| npn_not_s8rf_npn_1x1_2p0_HV AND LVID |
| } |
| "r_638_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap ENID" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap ENID |
| npn_not_s8rf_npn_1x1_2p0_HV AND ENID |
| } |
| "r_639_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap lvtn" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap lvtn |
| npn_not_s8rf_npn_1x1_2p0_HV AND lvtn |
| } |
| "r_640_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap hvi" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap hvi |
| npn_not_s8rf_npn_1x1_2p0_HV AND hvi |
| } |
| "r_641_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap DiodeID" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap DiodeID |
| npn_not_s8rf_npn_1x1_2p0_HV AND DiodeID |
| } |
| "r_642_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap COREID" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap COREID |
| npn_not_s8rf_npn_1x1_2p0_HV AND COREID |
| } |
| "r_643_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap ESDID" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap ESDID |
| npn_not_s8rf_npn_1x1_2p0_HV AND ESDID |
| } |
| "r_644_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap PHdiodeID" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap PHdiodeID |
| npn_not_s8rf_npn_1x1_2p0_HV AND PHdiodeID |
| } |
| "r_645_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap pnp" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap pnp |
| npn_not_s8rf_npn_1x1_2p0_HV AND pnp |
| } |
| "r_646_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap pwres" { |
| @ Illegal npnpar device: npn_not_s8rf_npn_1x1_2p0_HV must not overlap pwres |
| npn_not_s8rf_npn_1x1_2p0_HV AND pwres |
| } |
| "r_647_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap ncm" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap ncm |
| npn_and_s8rf_npn_1x1_2p0_HV AND ncm |
| } |
| "r_648_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap diffres" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap diffres |
| npn_and_s8rf_npn_1x1_2p0_HV AND diffres |
| } |
| "r_649_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap diffcut" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap diffcut |
| npn_and_s8rf_npn_1x1_2p0_HV AND diffcut |
| } |
| "r_650_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap polyres" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap polyres |
| npn_and_s8rf_npn_1x1_2p0_HV AND polyres |
| } |
| "r_651_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap polycut" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap polycut |
| npn_and_s8rf_npn_1x1_2p0_HV AND polycut |
| } |
| "r_652_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap li1res" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap li1res |
| npn_and_s8rf_npn_1x1_2p0_HV AND li1res |
| } |
| "r_653_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap li1cut" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap li1cut |
| npn_and_s8rf_npn_1x1_2p0_HV AND li1cut |
| } |
| "r_654_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap fuse" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap fuse |
| npn_and_s8rf_npn_1x1_2p0_HV AND fuse |
| } |
| "r_655_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap capacitor" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap capacitor |
| npn_and_s8rf_npn_1x1_2p0_HV AND capacitor |
| } |
| "r_656_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap LVID" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap LVID |
| npn_and_s8rf_npn_1x1_2p0_HV AND LVID |
| } |
| "r_657_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap ENID" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap ENID |
| npn_and_s8rf_npn_1x1_2p0_HV AND ENID |
| } |
| "r_658_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap lvtn" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap lvtn |
| npn_and_s8rf_npn_1x1_2p0_HV AND lvtn |
| } |
| "r_659_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap DiodeID" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap DiodeID |
| npn_and_s8rf_npn_1x1_2p0_HV AND DiodeID |
| } |
| "r_660_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap COREID" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap COREID |
| npn_and_s8rf_npn_1x1_2p0_HV AND COREID |
| } |
| "r_661_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap ESDID" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap ESDID |
| npn_and_s8rf_npn_1x1_2p0_HV AND ESDID |
| } |
| "r_662_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap PHdiodeID" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap PHdiodeID |
| npn_and_s8rf_npn_1x1_2p0_HV AND PHdiodeID |
| } |
| "r_663_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap pnp" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap pnp |
| npn_and_s8rf_npn_1x1_2p0_HV AND pnp |
| } |
| "r_664_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap pwres" { |
| @ Illegal npnpar device: npn_and_s8rf_npn_1x1_2p0_HV must not overlap pwres |
| npn_and_s8rf_npn_1x1_2p0_HV AND pwres |
| } |
| |
| nDiodeLvs = NMOSDIFFnotPOLY AND DiodeID |
| nDiode_hvi = nDiodeLvs AND hvi |
| nDiodeHV_ESD = nDiode_hvi AND ESDID |
| nDiodeHV = nDiode_hvi NOT (nDioHV100 OR |
| (nDioHV200 OR |
| (nDioHV300 OR |
| (pwDioHV100 OR |
| (pwDioHV200 OR pwDioHV300))))) |
| nDioHV100 = nDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2gnd_100_hv" ORIGINAL) |
| nDioHV200 = SIZE (nDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2gnd_200_hv" ORIGINAL)) BY (1.65 / 2.0) |
| nDioHV300 = SIZE (nDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2gnd_300_hv" ORIGINAL)) BY (1.65 / 2.0) |
| diode_pw2nd_05v5 = nDiodeLvs NOT nDiode_hvi |
| pwDioHV100 = nDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2gnd_100_dnwl_hv" ORIGINAL) |
| pwDioHV200 = SIZE (nDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2gnd_200_dnwl_hv" ORIGINAL)) BY (1.65 / 2.0) |
| pwDioHV300 = SIZE (nDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2gnd_300_dnwl_hv" ORIGINAL)) BY (1.65 / 2.0) |
| pDiodeLvs = PMOSDIFFnotPOLY AND DiodeID |
| pDiode_hvi = pDiodeLvs AND hvi |
| pDiodeHV_ESD = pDiode_hvi AND ESDID |
| pDiodeHV = pDiode_hvi NOT (pDioHV100 OR |
| (pDioHV200 OR pDioHV300)) |
| pDioHV100 = pDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2pwr_100_hv" ORIGINAL) |
| pDioHV200 = SIZE (pDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2pwr_200_hv" ORIGINAL)) BY (1.71 / 2.0) |
| pDioHV300 = SIZE (pDiodeHV_ESD AND (EXTENT CELL "s8_esd_paddiode2pwr_300_hv" ORIGINAL)) BY (1.71 / 2.0) |
| pDiode = pDiodeLvs NOT pDiode_hvi |
| RFESDcell1 = (EXTENT CELL "s8_esd_paddiode2gnd_100_hv" ORIGINAL) OR |
| ((EXTENT CELL "s8_esd_paddiode2gnd_200_hv" ORIGINAL) OR |
| ((EXTENT CELL "s8_esd_paddiode2gnd_300_hv" ORIGINAL) OR |
| ((EXTENT CELL "s8_esd_paddiode2gnd_100_dnwl_hv" ORIGINAL) OR |
| ((EXTENT CELL "s8_esd_paddiode2gnd_200_dnwl_hv" ORIGINAL) OR (EXTENT CELL "s8_esd_paddiode2gnd_300_dnwl_hv" ORIGINAL))))) |
| RFESDcell2 = (EXTENT CELL "s8_esd_paddiode2pwr_100_hv" ORIGINAL) OR |
| ((EXTENT CELL "s8_esd_paddiode2pwr_200_hv" ORIGINAL) OR (EXTENT CELL "s8_esd_paddiode2pwr_300_hv" ORIGINAL)) |
| rcxDioESDblk1 = pDioHV100 OR |
| (pDioHV200 OR |
| (pDioHV300 OR |
| (nDioHV100 OR |
| (nDioHV200 OR |
| (nDioHV300 OR |
| (pwDioHV100 OR |
| (pwDioHV200 OR pwDioHV300))))))) |
| rcxDioESDblk2 = ((tap AND RFESDcell1) NOT nwell) OR ((tap AND RFESDcell2) AND nwell) |
| rcxDioESDblk3 = rcxDioESDblk2 OR rcxDioESDblk1 |
| rcxDioESDblk4 = rcxDioESDblk3 OR (HOLES rcxDioESDblk3) |
| rcxDioESDblk = SIZE rcxDioESDblk4 BY 0.4 |
| photoDiode = INTERACT dnwell (dnwell AND (NTAP AND PHDiodeID)) |
| diode_diff = ((MOSDIFF NOT (INTERACT (MOSDIFF NOT diffcut) poly)) NOT diffcut) NOT DiodeID |
| diode_ndiff = diode_diff NOT nwell |
| ndiode_par_hv_lvtn = (diode_ndiff AND hvi) AND lvtn |
| ndiode_par_hvTmp = (diode_ndiff AND hvi) NOT ndiode_par_hv_lvtn |
| ndiode_par_hvESD = ndiode_par_hvTmp AND ESDID |
| ndiode_par_hv = ndiode_par_hvTmp NOT (ndiode_par_hvESD100 OR |
| (ndiode_par_hvESD200 OR |
| (ndiode_par_hvESD300 OR |
| (pwdiode_par_hvESD100 OR |
| (pwdiode_par_hvESD200 OR pwdiode_par_hvESD300))))) |
| ndiode_par_hvESD100 = ndiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2gnd_100_hv" ORIGINAL) |
| ndiode_par_hvESD200 = ndiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2gnd_200_hv" ORIGINAL) |
| ndiode_par_hvESD300 = ndiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2gnd_300_hv" ORIGINAL) |
| pwdiode_par_hvESD100 = ndiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2gnd_100_dnwl_hv" ORIGINAL) |
| pwdiode_par_hvESD200 = ndiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2gnd_200_dnwl_hv" ORIGINAL) |
| pwdiode_par_hvESD300 = ndiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2gnd_300_dnwl_hv" ORIGINAL) |
| ndiode_par_lvtn = (diode_ndiff AND lvtn) NOT ndiode_par_hv_lvtn |
| ndiode_par = diode_ndiff NOT (ndiode_par_hv_lvtn OR |
| (ndiode_par_hvTmp OR ndiode_par_lvtn)) |
| diode_pdiff = diode_diff AND nwell |
| pdiode_par_highvt = diode_pdiff AND hvtp |
| pdiode_par_hvTmp = diode_pdiff AND hvi |
| pdiode_par_hvESD = pdiode_par_hvTmp AND ESDID |
| pdiode_par_hv = pdiode_par_hvTmp NOT (pdiode_par_hvESD100 OR |
| (pdiode_par_hvESD200 OR pdiode_par_hvESD300)) |
| pdiode_par_hvESD100 = pdiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2pwr_100_hv" ORIGINAL) |
| pdiode_par_hvESD200 = pdiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2pwr_200_hv" ORIGINAL) |
| pdiode_par_hvESD300 = pdiode_par_hvESD AND (EXTENT CELL "s8_esd_paddiode2pwr_300_hv" ORIGINAL) |
| pdiode_par_lvtn = diode_pdiff AND lvtn |
| pdiode_par_lv = diode_pdiff NOT (pdiode_par_highvt OR |
| (pdiode_par_hvTmp OR pdiode_par_lvtn)) |
| //nwdio_par_tmp = INTERACT MosNwell dnwelldg |
| nwdio_par_tmp = NOT (INTERACT MosNwell dnwelldg) (uhvi OR LOWVTID) |
| diodeENIDxmt = (SIZE ENID BY 0.665) AND nwell |
| nwdio_par_noDnwell = NOT (NOT INTERACT (MosNwell NOT diodeENIDxmt) dnwelldg) (uhvi OR LOWVTID) |
| nwdio_par_iso = nwdio_par_tmp AND (SIZE dnwelldg BY 0.4) |
| //nwdio_par = nwdio_par_tmp NOT (PHdiodeID OR nwdio_par_iso) |
| nwdio_par = nwdio_par_tmp NOT (PHdiodeID OR (nwdio_par_iso OR uhvi)) |
| dnwellSize = SIZE dnwelldg BY 0.4 |
| diodeENIDxmt2 = (SIZE ENID BY 0.865) AND dnwelldg |
| //pw_dnw_par = dnwelldg NOT (nwell OR (PHDiodeID OR (pwcut OR diodeENIDxmt2 ))) |
| pw_dnw_par = (dnwelldg NOT pwbm) NOT (nwell OR (PHDiodeID OR (pwcut OR (diodeENIDxmt2 OR uhvi)))) |
| dnw_psub_par = dnwelldg NOT (PHDiodeID OR (LOWVTID OR uhvi)) |
| dnwhv_psub_tmp = INTERACT dnwelldg (AND pwbm (pfetExtDr20 OR (dnwellExplicit OR LOWVTID))) |
| dnwhv_psub_par = NOT dnwhv_psub_tmp PHDiodeID |
| |
| DEVICE D(diode_pw2nd_05v5) diode_pw2nd_05v5 Substrate(POS) NDIFF_cond(NEG) BY NET |
| CMACRO DIODE diode_pw2nd_05v5 |
| |
| // PROPERTY a , p , m , ahftempperim |
| // p = perimeter( diode_pw2nd_05v5 ) |
| // a = area( diode_pw2nd_05v5 ) |
| // m = 1 |
| // ahftempperim = perimeter( diode_pw2nd_05v5 ) |
| |
| TRACE PROPERTY D(diode_pw2nd_05v5) a a 1 |
| TRACE PROPERTY D(diode_pw2nd_05v5) p p 1 |
| TRACE PROPERTY D(diode_pw2nd_05v5) m m 0 |
| |
| |
| DEVICE D(ndiode_h) nDiodeHV Substrate(POS) NDIFF_cond(NEG) BY NET |
| CMACRO DIODE nDiodeHV |
| |
| TRACE PROPERTY D(ndiode_h) a a 1 |
| TRACE PROPERTY D(ndiode_h) p p 1 |
| TRACE PROPERTY D(ndiode_h) m m 0 |
| |
| DEVICE D(xesd_ndiode_h_100) nDioHV100 Substrate(POS) NDIFF_cond(NEG) BY NET |
| CMACRO DIODE nDioHV100 |
| |
| TRACE PROPERTY D(xesd_ndiode_h_100) a a 1 |
| TRACE PROPERTY D(xesd_ndiode_h_100) p p 1 |
| TRACE PROPERTY D(xesd_ndiode_h_100) m m 0 |
| |
| DEVICE D(xesd_ndiode_h_200) nDioHV200 Substrate(POS) NDIFF_cond(NEG) BY NET [ |
| PROPERTY a , p , m , ahftempperim |
| p = 203.12 |
| a = 92.721 |
| m = 1 |
| ahftempperim = perimeter( nDioHV200 ) |
| ] |
| |
| TRACE PROPERTY D(xesd_ndiode_h_200) a a 1 |
| TRACE PROPERTY D(xesd_ndiode_h_200) p p 1 |
| TRACE PROPERTY D(xesd_ndiode_h_200) m m 0 |
| |
| DEVICE D(xesd_ndiode_h_300) nDioHV300 Substrate(POS) NDIFF_cond(NEG) BY NET [ |
| PROPERTY a , p , m , ahftempperim |
| p = 304.68 |
| a = 139.0815 |
| m = 1 |
| ahftempperim = perimeter( nDioHV300 ) |
| ] |
| |
| TRACE PROPERTY D(xesd_ndiode_h_300) a a 1 |
| TRACE PROPERTY D(xesd_ndiode_h_300) p p 1 |
| TRACE PROPERTY D(xesd_ndiode_h_300) m m 0 |
| |
| DEVICE D(pdiode) pDiode PDIFF_cond(POS) MosNwell(NEG) BY NET |
| CMACRO DIODE pDiode |
| |
| TRACE PROPERTY D(pdiode) a a 1 |
| TRACE PROPERTY D(pdiode) p p 1 |
| TRACE PROPERTY D(pdiode) m m 0 |
| |
| DEVICE D(pdiode_h) pDiodeHV PDIFF_cond(POS) MosNwell(NEG) BY NET |
| CMACRO DIODE pDiodeHV |
| |
| TRACE PROPERTY D(pdiode_h) a a 1 |
| TRACE PROPERTY D(pdiode_h) p p 1 |
| TRACE PROPERTY D(pdiode_h) m m 0 |
| |
| DEVICE D(xesd_pdiode_h_100) pDioHV100 PDIFF_cond(POS) MosNwell(NEG) BY NET |
| CMACRO DIODE pDioHV100 |
| |
| TRACE PROPERTY D(xesd_pdiode_h_100) a a 1 |
| TRACE PROPERTY D(xesd_pdiode_h_100) p p 1 |
| TRACE PROPERTY D(xesd_pdiode_h_100) m m 0 |
| |
| DEVICE D(xesd_pdiode_h_200) pDioHV200 PDIFF_cond(POS) MosNwell(NEG) BY NET [ |
| PROPERTY a , p , m , ahftempperim |
| p = 203.28 |
| a = 96.709 |
| m = 1 |
| ahftempperim = perimeter( pDioHV200 ) |
| ] |
| |
| TRACE PROPERTY D(xesd_pdiode_h_200) a a 1 |
| TRACE PROPERTY D(xesd_pdiode_h_200) p p 1 |
| TRACE PROPERTY D(xesd_pdiode_h_200) m m 0 |
| |
| DEVICE D(xesd_pdiode_h_300) pDioHV300 PDIFF_cond(POS) MosNwell(NEG) BY NET [ |
| PROPERTY a , p , m , ahftempperim |
| p = 304.92 |
| a = 145.0635 |
| m = 1 |
| ahftempperim = perimeter( pDioHV300 ) |
| ] |
| |
| TRACE PROPERTY D(xesd_pdiode_h_300) a a 1 |
| TRACE PROPERTY D(xesd_pdiode_h_300) p p 1 |
| TRACE PROPERTY D(xesd_pdiode_h_300) m m 0 |
| |
| DEVICE D(dnwdiode_psub) photoDiode SubstrateSpecial(POS) DNWELL_cond(NEG) BY NET |
| CMACRO DIODE photoDiode |
| |
| TRACE PROPERTY D(dnwdiode_psub) a a 1 |
| TRACE PROPERTY D(dnwdiode_psub) p p 1 |
| TRACE PROPERTY D(dnwdiode_psub) m m 0 |
| |
| DEVICE D(xesd_ndiode_h_dnwl_100) pwDioHV100 SubstrateIso(POS) NDIFF_cond(NEG) BY NET |
| CMACRO DIODE pwDioHV100 |
| |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_100) a a 1 |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_100) p p 1 |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_100) m m 0 |
| |
| DEVICE D(xesd_ndiode_h_dnwl_200) pwDioHV200 SubstrateIso(POS) NDIFF_cond(NEG) BY NET [ |
| PROPERTY a , p , m , ahftempperim |
| p = 203.12 |
| a = 92.721 |
| m = 1 |
| ahftempperim = perimeter( pwDioHV200 ) |
| ] |
| |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_200) a a 1 |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_200) p p 1 |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_200) m m 0 |
| |
| DEVICE D(xesd_ndiode_h_dnwl_300) pwDioHV300 SubstrateIso(POS) NDIFF_cond(NEG) BY NET [ |
| PROPERTY a , p , m , ahftempperim |
| p = 304.68 |
| a = 139.0815 |
| m = 1 |
| ahftempperim = perimeter( pwDioHV300 ) |
| ] |
| |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_300) a a 1 |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_300) p p 1 |
| TRACE PROPERTY D(xesd_ndiode_h_dnwl_300) m m 0 |
| |
| // ;ss match lvsRules |
| |
| "r_665_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap ncm" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap ncm |
| diode_pw2nd_05v5 AND ncm |
| } |
| "r_666_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap nwell" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap nwell |
| diode_pw2nd_05v5 AND nwell |
| } |
| "r_667_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap tap" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap tap |
| diode_pw2nd_05v5 AND tap |
| } |
| "r_668_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap diffres" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap diffres |
| diode_pw2nd_05v5 AND diffres |
| } |
| "r_669_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap diffcut" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap diffcut |
| diode_pw2nd_05v5 AND diffcut |
| } |
| "r_670_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap poly" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap poly |
| diode_pw2nd_05v5 AND poly |
| } |
| "r_671_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap polyres" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap polyres |
| diode_pw2nd_05v5 AND polyres |
| } |
| "r_672_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap polycut" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap polycut |
| diode_pw2nd_05v5 AND polycut |
| } |
| "r_673_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap fuse" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap fuse |
| diode_pw2nd_05v5 AND fuse |
| } |
| "r_674_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap li1res" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap li1res |
| diode_pw2nd_05v5 AND li1res |
| } |
| "r_675_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap li1cut" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap li1cut |
| diode_pw2nd_05v5 AND li1cut |
| } |
| "r_676_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap psdm" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap psdm |
| diode_pw2nd_05v5 AND psdm |
| } |
| "r_677_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap capacitor" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap capacitor |
| diode_pw2nd_05v5 AND capacitor |
| } |
| "r_678_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap LVID" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap LVID |
| diode_pw2nd_05v5 AND LVID |
| } |
| "r_679_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap hvtp" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap hvtp |
| diode_pw2nd_05v5 AND hvtp |
| } |
| "r_680_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap lvtn" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap lvtn |
| diode_pw2nd_05v5 AND lvtn |
| } |
| "r_681_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap hvi" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap hvi |
| diode_pw2nd_05v5 AND hvi |
| } |
| "r_682_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap pnp" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap pnp |
| diode_pw2nd_05v5 AND pnp |
| } |
| "r_683_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap PHdiodeID" { |
| @ Illegal diode_pw2nd_05v5 device: diode_pw2nd_05v5 must not overlap PHdiodeID |
| diode_pw2nd_05v5 AND PHdiodeID |
| } |
| "r_684_Illegal nDiode_hvi device nDiode_hvi must not overlap ncm" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap ncm |
| nDiode_hvi AND ncm |
| } |
| "r_685_Illegal nDiode_hvi device nDiode_hvi must not overlap nwell" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap nwell |
| nDiode_hvi AND nwell |
| } |
| "r_686_Illegal nDiode_hvi device nDiode_hvi must not overlap tap" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap tap |
| nDiode_hvi AND tap |
| } |
| "r_687_Illegal nDiode_hvi device nDiode_hvi must not overlap diffres" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap diffres |
| nDiode_hvi AND diffres |
| } |
| "r_688_Illegal nDiode_hvi device nDiode_hvi must not overlap diffcut" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap diffcut |
| nDiode_hvi AND diffcut |
| } |
| "r_689_Illegal nDiode_hvi device nDiode_hvi must not overlap poly" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap poly |
| nDiode_hvi AND poly |
| } |
| "r_690_Illegal nDiode_hvi device nDiode_hvi must not overlap polyres" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap polyres |
| nDiode_hvi AND polyres |
| } |
| "r_691_Illegal nDiode_hvi device nDiode_hvi must not overlap polycut" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap polycut |
| nDiode_hvi AND polycut |
| } |
| "r_692_Illegal nDiode_hvi device nDiode_hvi must not overlap fuse" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap fuse |
| nDiode_hvi AND fuse |
| } |
| "r_693_Illegal nDiode_hvi device nDiode_hvi must not overlap li1res" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap li1res |
| nDiode_hvi AND li1res |
| } |
| "r_694_Illegal nDiode_hvi device nDiode_hvi must not overlap li1cut" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap li1cut |
| nDiode_hvi AND li1cut |
| } |
| "r_695_Illegal nDiode_hvi device nDiode_hvi must not overlap psdm" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap psdm |
| nDiode_hvi AND psdm |
| } |
| "r_696_Illegal nDiode_hvi device nDiode_hvi must not overlap capacitor" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap capacitor |
| nDiode_hvi AND capacitor |
| } |
| "r_697_Illegal nDiode_hvi device nDiode_hvi must not overlap LVID" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap LVID |
| nDiode_hvi AND LVID |
| } |
| "r_698_Illegal nDiode_hvi device nDiode_hvi must not overlap hvtp" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap hvtp |
| nDiode_hvi AND hvtp |
| } |
| "r_699_Illegal nDiode_hvi device nDiode_hvi must not overlap lvtn" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap lvtn |
| nDiode_hvi AND lvtn |
| } |
| "r_700_Illegal nDiode_hvi device nDiode_hvi must not overlap pnp" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap pnp |
| nDiode_hvi AND pnp |
| } |
| "r_701_Illegal nDiode_hvi device nDiode_hvi must not overlap COREID" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap COREID |
| nDiode_hvi AND COREID |
| } |
| "r_702_Illegal nDiode_hvi device nDiode_hvi must not overlap PHdiodeID" { |
| @ Illegal nDiode_hvi device: nDiode_hvi must not overlap PHdiodeID |
| nDiode_hvi AND PHdiodeID |
| } |
| "r_703_Illegal pDiode device pDiode must not overlap tap" { |
| @ Illegal pDiode device: pDiode must not overlap tap |
| pDiode AND tap |
| } |
| "r_704_Illegal pDiode device pDiode must not overlap diffres" { |
| @ Illegal pDiode device: pDiode must not overlap diffres |
| pDiode AND diffres |
| } |
| "r_705_Illegal pDiode device pDiode must not overlap diffcut" { |
| @ Illegal pDiode device: pDiode must not overlap diffcut |
| pDiode AND diffcut |
| } |
| "r_706_Illegal pDiode device pDiode must not overlap poly" { |
| @ Illegal pDiode device: pDiode must not overlap poly |
| pDiode AND poly |
| } |
| "r_707_Illegal pDiode device pDiode must not overlap polyres" { |
| @ Illegal pDiode device: pDiode must not overlap polyres |
| pDiode AND polyres |
| } |
| "r_708_Illegal pDiode device pDiode must not overlap polycut" { |
| @ Illegal pDiode device: pDiode must not overlap polycut |
| pDiode AND polycut |
| } |
| "r_709_Illegal pDiode device pDiode must not overlap fuse" { |
| @ Illegal pDiode device: pDiode must not overlap fuse |
| pDiode AND fuse |
| } |
| "r_710_Illegal pDiode device pDiode must not overlap li1res" { |
| @ Illegal pDiode device: pDiode must not overlap li1res |
| pDiode AND li1res |
| } |
| "r_711_Illegal pDiode device pDiode must not overlap li1cut" { |
| @ Illegal pDiode device: pDiode must not overlap li1cut |
| pDiode AND li1cut |
| } |
| "r_712_Illegal pDiode device pDiode must not overlap nsdm" { |
| @ Illegal pDiode device: pDiode must not overlap nsdm |
| pDiode AND nsdm |
| } |
| "r_713_Illegal pDiode device pDiode must not overlap capacitor" { |
| @ Illegal pDiode device: pDiode must not overlap capacitor |
| pDiode AND capacitor |
| } |
| "r_714_Illegal pDiode device pDiode must not overlap LVID" { |
| @ Illegal pDiode device: pDiode must not overlap LVID |
| pDiode AND LVID |
| } |
| "r_715_Illegal pDiode device pDiode must not overlap hvtp" { |
| @ Illegal pDiode device: pDiode must not overlap hvtp |
| pDiode AND hvtp |
| } |
| "r_716_Illegal pDiode device pDiode must not overlap lvtn" { |
| @ Illegal pDiode device: pDiode must not overlap lvtn |
| pDiode AND lvtn |
| } |
| "r_717_Illegal pDiode device pDiode must not overlap hvi" { |
| @ Illegal pDiode device: pDiode must not overlap hvi |
| pDiode AND hvi |
| } |
| "r_718_Illegal pDiode device pDiode must not overlap pnp" { |
| @ Illegal pDiode device: pDiode must not overlap pnp |
| pDiode AND pnp |
| } |
| "r_719_Illegal pDiode device pDiode must not overlap PHdiodeID" { |
| @ Illegal pDiode device: pDiode must not overlap PHdiodeID |
| pDiode AND PHdiodeID |
| } |
| "r_720_Illegal pDiode_hvi device pDiode_hvi must not overlap ncm" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap ncm |
| pDiode_hvi AND ncm |
| } |
| "r_721_Illegal pDiode_hvi device pDiode_hvi must not overlap tap" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap tap |
| pDiode_hvi AND tap |
| } |
| "r_722_Illegal pDiode_hvi device pDiode_hvi must not overlap diffres" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap diffres |
| pDiode_hvi AND diffres |
| } |
| "r_723_Illegal pDiode_hvi device pDiode_hvi must not overlap diffcut" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap diffcut |
| pDiode_hvi AND diffcut |
| } |
| "r_724_Illegal pDiode_hvi device pDiode_hvi must not overlap poly" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap poly |
| pDiode_hvi AND poly |
| } |
| "r_725_Illegal pDiode_hvi device pDiode_hvi must not overlap polyres" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap polyres |
| pDiode_hvi AND polyres |
| } |
| "r_726_Illegal pDiode_hvi device pDiode_hvi must not overlap polycut" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap polycut |
| pDiode_hvi AND polycut |
| } |
| "r_727_Illegal pDiode_hvi device pDiode_hvi must not overlap fuse" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap fuse |
| pDiode_hvi AND fuse |
| } |
| "r_728_Illegal pDiode_hvi device pDiode_hvi must not overlap li1res" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap li1res |
| pDiode_hvi AND li1res |
| } |
| "r_729_Illegal pDiode_hvi device pDiode_hvi must not overlap li1cut" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap li1cut |
| pDiode_hvi AND li1cut |
| } |
| "r_730_Illegal pDiode_hvi device pDiode_hvi must not overlap nsdm" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap nsdm |
| pDiode_hvi AND nsdm |
| } |
| "r_731_Illegal pDiode_hvi device pDiode_hvi must not overlap capacitor" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap capacitor |
| pDiode_hvi AND capacitor |
| } |
| "r_732_Illegal pDiode_hvi device pDiode_hvi must not overlap LVID" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap LVID |
| pDiode_hvi AND LVID |
| } |
| "r_733_Illegal pDiode_hvi device pDiode_hvi must not overlap hvtp" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap hvtp |
| pDiode_hvi AND hvtp |
| } |
| "r_734_Illegal pDiode_hvi device pDiode_hvi must not overlap lvtn" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap lvtn |
| pDiode_hvi AND lvtn |
| } |
| "r_735_Illegal pDiode_hvi device pDiode_hvi must not overlap pnp" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap pnp |
| pDiode_hvi AND pnp |
| } |
| "r_736_Illegal pDiode_hvi device pDiode_hvi must not overlap COREID" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap COREID |
| pDiode_hvi AND COREID |
| } |
| "r_737_Illegal pDiode_hvi device pDiode_hvi must not overlap PHdiodeID" { |
| @ Illegal pDiode_hvi device: pDiode_hvi must not overlap PHdiodeID |
| pDiode_hvi AND PHdiodeID |
| } |
| "r_738_Illegal photoDiode device photoDiode must not overlap ncm" { |
| @ Illegal photoDiode device: photoDiode must not overlap ncm |
| photoDiode AND ncm |
| } |
| "r_739_Illegal photoDiode device photoDiode must not overlap diff" { |
| @ Illegal photoDiode device: photoDiode must not overlap diff |
| photoDiode AND diff |
| } |
| "r_740_Illegal photoDiode device photoDiode must not overlap diffres" { |
| @ Illegal photoDiode device: photoDiode must not overlap diffres |
| photoDiode AND diffres |
| } |
| "r_741_Illegal photoDiode device photoDiode must not overlap diffcut" { |
| @ Illegal photoDiode device: photoDiode must not overlap diffcut |
| photoDiode AND diffcut |
| } |
| "r_742_Illegal photoDiode device photoDiode must not overlap hvtp" { |
| @ Illegal photoDiode device: photoDiode must not overlap hvtp |
| photoDiode AND hvtp |
| } |
| "r_743_Illegal photoDiode device photoDiode must not overlap lvtn" { |
| @ Illegal photoDiode device: photoDiode must not overlap lvtn |
| photoDiode AND lvtn |
| } |
| "r_744_Illegal photoDiode device photoDiode must not overlap tunm" { |
| @ Illegal photoDiode device: photoDiode must not overlap tunm |
| photoDiode AND tunm |
| } |
| "r_745_Illegal photoDiode device photoDiode must not overlap hvi" { |
| @ Illegal photoDiode device: photoDiode must not overlap hvi |
| photoDiode AND hvi |
| } |
| "r_746_Illegal photoDiode device photoDiode must not overlap poly" { |
| @ Illegal photoDiode device: photoDiode must not overlap poly |
| photoDiode AND poly |
| } |
| "r_747_Illegal photoDiode device photoDiode must not overlap polyres" { |
| @ Illegal photoDiode device: photoDiode must not overlap polyres |
| photoDiode AND polyres |
| } |
| "r_748_Illegal photoDiode device photoDiode must not overlap polycut" { |
| @ Illegal photoDiode device: photoDiode must not overlap polycut |
| photoDiode AND polycut |
| } |
| "r_749_Illegal photoDiode device photoDiode must not overlap polyModel" { |
| @ Illegal photoDiode device: photoDiode must not overlap polyModel |
| photoDiode AND polyModel |
| } |
| "r_750_Illegal photoDiode device photoDiode must not overlap npc" { |
| @ Illegal photoDiode device: photoDiode must not overlap npc |
| photoDiode AND npc |
| } |
| "r_751_Illegal photoDiode device photoDiode must not overlap psdm" { |
| @ Illegal photoDiode device: photoDiode must not overlap psdm |
| photoDiode AND psdm |
| } |
| "r_752_Illegal photoDiode device photoDiode must not overlap li1res" { |
| @ Illegal photoDiode device: photoDiode must not overlap li1res |
| photoDiode AND li1res |
| } |
| "r_753_Illegal photoDiode device photoDiode must not overlap li1cut" { |
| @ Illegal photoDiode device: photoDiode must not overlap li1cut |
| photoDiode AND li1cut |
| } |
| "r_754_Illegal photoDiode device photoDiode must not overlap fuse" { |
| @ Illegal photoDiode device: photoDiode must not overlap fuse |
| photoDiode AND fuse |
| } |
| "r_755_Illegal photoDiode device photoDiode must not overlap capacitor" { |
| @ Illegal photoDiode device: photoDiode must not overlap capacitor |
| photoDiode AND capacitor |
| } |
| "r_756_Illegal photoDiode device photoDiode must not overlap LVID" { |
| @ Illegal photoDiode device: photoDiode must not overlap LVID |
| photoDiode AND LVID |
| } |
| "r_757_Illegal photoDiode device photoDiode must not overlap pnp" { |
| @ Illegal photoDiode device: photoDiode must not overlap pnp |
| photoDiode AND pnp |
| } |
| "r_758_Illegal photoDiode device photoDiode must not overlap COREID" { |
| @ Illegal photoDiode device: photoDiode must not overlap COREID |
| photoDiode AND COREID |
| } |
| "r_759_Illegal photoDiode device photoDiode must not overlap ESDID" { |
| @ Illegal photoDiode device: photoDiode must not overlap ESDID |
| photoDiode AND ESDID |
| } |
| |
| LVS REDUCE D PARALLEL YES [ |
| TOLERANCE a 1.0 |
| p 1.0 |
| |
| EFFECTIVE m , a , p |
| m = SUM( m ) |
| a = SUM( (a * m) ) / m |
| p = SUM( (p * m) ) / m |
| ] |
| |
| LVS REDUCE D SERIES POS NEG NO |
| |
| DEVICE Dpar(diode_pw2nd_05v5) ndiode_par Substrate(d0) NDIFF_cond(d1) <diff> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR ndiode_par diff |
| |
| // PROPERTY a , p , m |
| // p = perimeter_coincide_inside( ndiode_par , diff ) |
| // a = area( ndiode_par ) |
| // m = 1 |
| |
| |
| DEVICE Dpar(ndiode_h) ndiode_par_hv Substrate(d0) NDIFF_cond(d1) <diff> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR ndiode_par_hv diff |
| |
| |
| DEVICE Dpar(ndiode_lvt) ndiode_par_lvtn Substrate(d0) NDIFF_cond(d1) <diff> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR ndiode_par_lvtn diff |
| |
| |
| DEVICE Dpar(ndiode_native) ndiode_par_hv_lvtn Substrate(d0) NDIFF_cond(d1) <diff> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR ndiode_par_hv_lvtn diff |
| |
| |
| DEVICE Dpar(pdiode) pdiode_par_lv PDIFF_cond(d0) MosNwell(d1) <diff> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR pdiode_par_lv diff |
| |
| |
| DEVICE Dpar(pdiode_h) pdiode_par_hv PDIFF_cond(d0) MosNwell(d1) <diff> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR pdiode_par_hv diff |
| |
| |
| DEVICE Dpar(pdiode_lvt) pdiode_par_lvtn PDIFF_cond(d0) MosNwell(d1) <diff> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR pdiode_par_lvtn diff |
| |
| |
| DEVICE Dpar(pdiode_hvt) pdiode_par_highvt PDIFF_cond(d0) MosNwell(d1) <diff> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR pdiode_par_highvt diff |
| |
| |
| DEVICE Dpar(nwdiode) nwdio_par Substrate(d0) MosNwell(d1) <dnwellSize> BY NET NETLIST ELEMENT "D" |
| CMACRO DPAR nwdio_par dnwellSize |
| |
| |
| q6nwdio_par_noDnwell = DONUT nwdio_par_noDnwell |
| q5nwdio_par_noDnwell = (HOLES q6nwdio_par_noDnwell) NOT nwdio_par_noDnwell |
| q3nwdio_par_noDnwell = (SIZE q5nwdio_par_noDnwell BY 0.28) AND q6nwdio_par_noDnwell |
| q4nwdio_par_noDnwell = nwdio_par_noDnwell NOT q3nwdio_par_noDnwell |
| q7nwdio_par_noDnwell = NOT INTERACT q4nwdio_par_noDnwell Substrate |
| q1nwdio_par_noDnwell = q4nwdio_par_noDnwell NOT q7nwdio_par_noDnwell |
| q8nwdio_par_noDnwell = SIZE q7nwdio_par_noDnwell BY 0.28 |
| SCONNECT Substrate q8nwdio_par_noDnwell ABUT ALSO |
| q9nwdio_par_noDnwell = EXPAND EDGE (EXTERNAL [q8nwdio_par_noDnwell] Substrate == 0 CONNECTED ABUT) INSIDE BY 0.28 |
| q2nwdio_par_noDnwell = q7nwdio_par_noDnwell OR (INTERACT q3nwdio_par_noDnwell q9nwdio_par_noDnwell) |
| q0nwdio_par_noDnwell = q3nwdio_par_noDnwell NOT q2nwdio_par_noDnwell |
| |
| DEVICE Dpar(nwdiode) q0nwdio_par_noDnwell Substrate(d0) MosNwell(d1) <nwdio_par_noDnwell> BY NET NETLIST ELEMENT "D" [ |
| PROPERTY a , p , m |
| p = perimeter_coincide( q0nwdio_par_noDnwell , nwdio_par_noDnwell ) * L_scale |
| a = area( q0nwdio_par_noDnwell ) * L_scale2 |
| m = 1 |
| ] |
| |
| |
| DEVICE Dpar(nwdiode) q1nwdio_par_noDnwell Substrate(d0) MosNwell(d1) <nwdio_par_noDnwell> BY NET NETLIST ELEMENT "D" [ |
| PROPERTY a , p , m |
| p = perimeter_coincide( q1nwdio_par_noDnwell , nwdio_par_noDnwell ) * L_scale |
| a = area( q1nwdio_par_noDnwell ) * L_scale2 |
| m = 1 |
| ] |
| |
| |
| DEVICE Dpar(nwdiode) q2nwdio_par_noDnwell Substrate(d0) MosNwell(d1) <nwdio_par_noDnwell> BY NET NETLIST ELEMENT "D" [ |
| PROPERTY a , p , m |
| p = perimeter_coincide( q2nwdio_par_noDnwell , nwdio_par_noDnwell ) * L_scale |
| a = area( q2nwdio_par_noDnwell ) * L_scale2 |
| m = 1 |
| ] |
| |
| |
| DEVICE Dpar(dnwdiode_psub) dnw_psub_par SubstrateSpecial(d0) DNWELL_cond(d1) BY NET NETLIST ELEMENT "D" [ |
| PROPERTY a , p , m |
| p = perimeter( dnw_psub_par ) * L_scale |
| a = area( dnw_psub_par ) * L_scale2 |
| m = 1 |
| ] |
| |
| |
| DEVICE Dpar(dnwdiode_pw) pw_dnw_par SubstrateIso(d0) DNWELL_cond(d1) BY NET NETLIST ELEMENT "D" [ |
| PROPERTY a , p , m |
| p = perimeter( pw_dnw_par ) * L_scale |
| a = area( pw_dnw_par ) * L_scale2 |
| m = 1 |
| ] |
| |
| DEVICE Dpar(dnwhvdiode_psub) dnwhv_psub_par SubstrateHVSpecial(d0) DNWELL_cond(d1) BY NET NETLIST ELEMENT "D" [ |
| PROPERTY a , p , m |
| p = perimeter( dnwhv_psub_par ) * L_scale |
| a = area( dnwhv_psub_par ) * L_scale2 |
| m = 1 |
| ] |
| |
| DEVICE Dpar(reslocsub) localSub PTAP_NotDnwell_cond(d0) PTAP_NotDnwell_cond(d1) BY NET NETLIST ELEMENT "D" [ |
| PROPERTY a , p , m |
| p = perimeter( localSub ) * L_scale |
| a = area( localSub ) * L_scale2 |
| m = 1 |
| ] |
| |
| // ;ss match lvsRules |
| |
| "r_760_Illegal pdiode_hvt device pdiode_par_highvt must not overlap hvi" { |
| @ Illegal pdiode_hvt device: pdiode_par_highvt must not overlap hvi |
| pdiode_par_highvt AND hvi |
| } |
| "r_761_Illegal pdiode_hvt device pdiode_par_highvt must not overlap PHdiodeID" { |
| @ Illegal pdiode_hvt device: pdiode_par_highvt must not overlap PHdiodeID |
| pdiode_par_highvt AND PHdiodeID |
| } |
| "r_762_Illegal nwdiode device nwdio_par must not overlap dnwell" { |
| @ Illegal nwdiode device: nwdio_par must not overlap dnwell |
| nwdio_par AND dnwell |
| } |
| "r_763_Illegal nwdiode device nwdio_par must not overlap PHdiodeID" { |
| @ Illegal nwdiode device: nwdio_par must not overlap PHdiodeID |
| nwdio_par AND PHdiodeID |
| } |
| "r_764_Illegal dnwdiode_pw device pw_dnw_par must not overlap nwell" { |
| @ Illegal dnwdiode_pw device: pw_dnw_par must not overlap nwell |
| pw_dnw_par AND nwell |
| } |
| "r_765_Illegal dnwdiode_pw device pw_dnw_par must not overlap PHdiodeID" { |
| @ Illegal dnwdiode_pw device: pw_dnw_par must not overlap PHdiodeID |
| pw_dnw_par AND PHdiodeID |
| } |
| "r_766_Illegal pdiode_lvt device pdiode_par_lvtn must not overlap hvtp" { |
| @ Illegal pdiode_lvt device: pdiode_par_lvtn must not overlap hvtp |
| pdiode_par_lvtn AND hvtp |
| } |
| "r_767_Illegal pdiode_lvt device pdiode_par_lvtn must not overlap PHdiodeID" { |
| @ Illegal pdiode_lvt device: pdiode_par_lvtn must not overlap PHdiodeID |
| pdiode_par_lvtn AND PHdiodeID |
| } |
| |
| vppcap_hd5_s = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_atlas_fingercap2_l5" |
| vppcap_hd5_r = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_atlas_wafflecap2" |
| vppcap_hd5_q = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_atlas_wafflecap1" |
| vppcap_hd5_p = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_atlas_fingercap_l40" |
| vppcap_hd5_o = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_atlas_fingercap_l20" |
| vppcap_hd5_n = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_atlas_fingercap_l10" |
| vppcap_hd5_m = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_atlas_fingercap_l5" |
| vppcap_hd5_l = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_5x2_met5pullin" |
| vppcap_hd5_k = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_5x2" |
| vppcap_hd5_j = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_5x1_met5pullin" |
| vppcap_hd5_i = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_5x1" |
| vppcap_hd5_h = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_4x2" |
| vppcap_hd5_g = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_4x1" |
| vppcap_hd5_f = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_3x2" |
| vppcap_hd5_e = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_3x1" |
| vppcap_hd5_d = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_2x2" |
| vppcap_hd5_c = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_2x1" |
| vppcap_hd5_b = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_1x2" |
| vppcap_hd5_a = INSIDE CELL capdraw "s8rf2_xcmvpp_hd5_1x1" |
| vppcapNHVnative = INSIDE CELL capdraw "s8rf2_xcmvppx4_2xnhvnative10x4" |
| cap140fF_7 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_polym50p4shield" |
| cap140fF_6 = INSIDE CELL capdraw "s8rf2_xcmvpp4p4x4p6_m3_lim5shield" |
| cap140fF_5 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_m3_lim5shield" |
| cap140fF_4 = INSIDE CELL capdraw "s8rf2_xcmvpp8p6x7p9_m3_lim5shield" |
| cap140fF_3 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_lim5shield" |
| cap140fF_2 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_polym5shield" |
| cap140fF_1 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_m5shield" |
| vppM4shield4 = INSIDE CELL capdraw "s8rf2_xcmvpp6p8x6p1_lim4shield" |
| vppM4shield3 = INSIDE CELL capdraw "s8rf2_xcmvpp6p8x6p1_polym4shield" |
| vppM4shield2 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_polym4shield" |
| vppM4shield1 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_m4shield" |
| cap1fF_liShield = INSIDE CELL capdraw "s8rf_xcmvpp1p8x1p8_lishield" |
| cap12fF_liShield = INSIDE CELL capdraw "s8rf_xcmvpp4p4x4p6_m3_lishield" |
| cap50fF_liShield = INSIDE CELL capdraw "s8rf_xcmvpp8p6x7p9_m3_lishield" |
| cap100fF_liShield = INSIDE CELL capdraw "s8rf_xcmvpp11p5x11p7_m3_lishield" |
| cap100fF = INSIDE CELL capdraw "s8rf_xcmvpp11p5x11p7_m3shield" |
| cap50fF = INSIDE CELL capdraw "s8rf_xcmvpp8p6x7p9_m3shield" |
| cap12fF = INSIDE CELL capdraw "s8rf_xcmvpp4p4x4p6_m3shield" |
| cap1fF = INSIDE CELL capdraw "s8rf_xcmvpp1p8x1p8_m3shield" |
| cap100fF_mm5shield = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_m1m4m5shield" |
| cap100fF_m3m4 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_m1m4" |
| cap100fF_m1m2 = INSIDE CELL capdraw "s8rf2_xcmvpp11p5x11p7_m1m2" |
| cap12fF_noShield = INSIDE CELL capdraw "s8rf2_xcmvpp4p4x4p6_m1m2" |
| cap5fF = INSIDE CELL capdraw "s8rf2_xcmvpp5" |
| cap10fF = INSIDE CELL capdraw "s8rf2_xcmvpp4" |
| cap35fF = INSIDE CELL capdraw "s8rf2_xcmvpp3" |
| caps_w_noli = cap35fF OR |
| (cap10fF OR |
| (cap5fF OR |
| (cap12fF_noShield OR |
| (cap100fF_m1m2 OR cap100fF_m3m4)))) |
| vppcap_hd5_org = vppcap_hd5_a OR |
| (vppcap_hd5_b OR |
| (vppcap_hd5_c OR |
| (vppcap_hd5_d OR |
| (vppcap_hd5_e OR |
| (vppcap_hd5_f OR |
| (vppcap_hd5_g OR |
| (vppcap_hd5_h OR |
| (vppcap_hd5_i OR |
| (vppcap_hd5_j OR |
| (vppcap_hd5_k OR vppcap_hd5_l)))))))))) |
| vppcap_hd5_atlas = vppcap_hd5_m OR |
| (vppcap_hd5_n OR |
| (vppcap_hd5_o OR |
| (vppcap_hd5_p OR |
| (vppcap_hd5_q OR |
| (vppcap_hd5_r OR vppcap_hd5_s))))) |
| vppcap_hd5 = vppcap_hd5_org OR vppcap_hd5_atlas |
| xcmvpp = AREA capdraw == 67.2672 |
| xcmvpp_2all = AREA capdraw == 20.1042 |
| xcmvpp_2 = NOT INTERACT xcmvpp_2all (vppcapNHVnative OR diff) |
| xcmvpp_2nhvnative = INTERACT xcmvpp_2all nhvnative10x4 |
| xcmvpp_2phv = INTERACT xcmvpp_2all (phv5x4 OR |
| (pshort5x4 OR |
| (plowvt5x4 OR phighvt5x4))) |
| xcmvpp_2RCX = capdraw AND (EXTENT CELL "s8rf_xcmvpp2*" ORIGINAL) |
| vppTermBB = NOT INTERACT (met2 AND capdraw) diff |
| vppTermBBMos = INTERACT (met2 AND (xcmvpp_2nhvnative OR xcmvpp_2phv)) diff |
| BulkTermCap = xcmvpp OR xcmvpp_2 |
| BulkTermCapMos = poly AND (xcmvpp_2nhvnative OR xcmvpp_2phv) |
| BulkTermCapVpp = cap1fF OR |
| (cap12fF OR |
| (cap50fF OR |
| (cap100fF OR (cap100fF_liShield OR |
| (cap50fF_liShield OR |
| (cap12fF_liShield OR |
| (cap1fF_liShield OR caps_w_noli))))))) |
| BulkTermCapVpp_tmp = cap1fF OR |
| (cap12fF OR |
| (cap50fF OR cap100fF)) |
| BulkTermCapVpp_tmp2 = cap100fF_liShield OR |
| (cap50fF_liShield OR |
| (cap12fF_liShield OR cap1fF_liShield)) |
| capdrawSz = SIZE BulkTermCapVpp BY 0.165 |
| capdrawSz_tmp2 = SIZE BulkTermCapVpp_tmp2 BY 0.165 |
| capdrawRCSz = SIZE BulkTermCapVpp BY 0.17 |
| topMetVpp = INTERACT met3 BulkTermCapVpp_tmp |
| polyBulkTerm = poly AND BulkTermCapVpp |
| li1BulkTerm = li1 AND BulkTermCapVpp |
| met1BulkTerm = met1 AND BulkTermCapVpp |
| met2BulkTerm = met2 AND BulkTermCapVpp |
| li1poly = INTERACT li1BulkTerm (polyBulkTerm AND licon1) |
| met1poly = INTERACT met1BulkTerm (li1poly AND mcon) |
| met2met1 = INTERACT met2BulkTerm (met1poly AND via) |
| vppTermpoly = met2met1 AND BulkTermCapVpp |
| vppTermNopoly = met2BulkTerm NOT met2met1 |
| met1li1 = INTERACT met1BulkTerm (li1BulkTerm AND mcon) |
| met2li1 = INTERACT met2BulkTerm (met1li1 AND via) |
| vppTermli1 = met2li1 AND BulkTermCapVpp |
| vppTermNoli1 = met2BulkTerm NOT met2li1 |
| BulkTermCapVpp_M4 = vppM4shield1 OR |
| (vppM4shield2 OR |
| (vppM4shield3 OR vppM4shield4)) |
| capdrawSz_M4 = SIZE BulkTermCapVpp_M4 BY 0.165 |
| capdrawRCSz_M4 = SIZE BulkTermCapVpp_M4 BY 0.17 |
| topMetVpp_M4 = INTERACT met4 BulkTermCapVpp_M4 |
| polyBulkTerm_M4 = poly AND BulkTermCapVpp_M4 |
| li1BulkTerm_M4 = li1 AND BulkTermCapVpp_M4 |
| met1BulkTerm_M4 = met1 AND BulkTermCapVpp_M4 |
| met2BulkTerm_M4 = met2 AND BulkTermCapVpp_M4 |
| met3BulkTerm_M4 = met3 AND BulkTermCapVpp_M4 |
| li1poly_M4 = INTERACT li1BulkTerm_M4 (polyBulkTerm_M4 AND licon1) |
| met1poly_M4 = INTERACT met1BulkTerm_M4 (li1poly_M4 AND mcon) |
| met2met1_M4 = INTERACT met2BulkTerm_M4 (met1poly_M4 AND via) |
| met3met2_M4 = INTERACT met3BulkTerm_M4 (met2met1_M4 AND via2) |
| vppTermpoly_M4 = met3met2_M4 AND BulkTermCapVpp_M4 |
| vppTermNopoly_M4 = met3BulkTerm_M4 NOT met3met2_M4 |
| met1li1_M4 = INTERACT met1BulkTerm_M4 (li1BulkTerm_M4 AND mcon) |
| met2li1_M4 = INTERACT met2BulkTerm_M4 (met1li1_M4 AND via) |
| met3li1_M4 = INTERACT met3BulkTerm_M4 (met2li1_M4 AND via2) |
| vppTermli1_M4 = met3li1_M4 AND BulkTermCapVpp_M4 |
| met2met1_M4_noLi1 = INTERACT met2BulkTerm_M4 ((met1BulkTerm_m4 NOT met1li1_M4) AND via) |
| met3met1_M4_noLi1 = INTERACT met3BulkTerm_M4 (met2met1_M4_noLi1 AND via2) |
| vppTermM1_M4 = met3met1_M4_noLi1 AND BulkTermCapVpp_M4 |
| BulkTermCapVpp_M5 = cap140fF_1 OR |
| (cap140fF_2 OR |
| (cap140fF_7 OR |
| (cap140fF_3 OR |
| (cap140fF_4 OR |
| (cap140fF_5 OR |
| (cap140fF_6 OR |
| (vppcapNHVnative OR |
| (cap100fF_mm5shield OR |
| (cap100fF_m3m4 OR vppcap_hd5))))))))) |
| capdrawBulkTermM5 = BulkTermCapVpp_M5 NOT vppcap_hd5_atlas |
| capdrawSz_M5 = BulkTermCapVpp_M5 OR (SIZE capdrawBulkTermM5 BY 0.165) |
| capdrawSz_M5_noshrink = SIZE (capdrawBulkTermM5 NOT cap140fF_7) BY 0.165 |
| capdrawRCSz_M5 = BulkTermCapVpp_M5 OR (SIZE capdrawBulkTermM5 BY 0.17) |
| topMetVpp_M5 = INTERACT met5 BulkTermCapVpp_M5 |
| topMetVpp_M5_shrunk = INTERACT (met5 NOT m5_short) cap140fF_7 |
| polyBulkTerm_M5 = poly AND BulkTermCapVpp_M5 |
| all_capdrawSz = capdrawSz OR |
| (capdrawSz_tmp2 OR |
| (capdrawSz_M5 OR capdrawSz_M4)) |
| li1BulkTerm_M5 = li1 AND BulkTermCapVpp_M5 |
| met1BulkTerm_M5 = met1 AND BulkTermCapVpp_M5 |
| met2BulkTerm_M5 = met2 AND BulkTermCapVpp_M5 |
| met3BulkTerm_M5 = met3 AND BulkTermCapVpp_M5 |
| met4BulkTerm_M5 = met4 AND BulkTermCapVpp_M5 |
| li1poly_M5 = INTERACT li1BulkTerm_M5 (polyBulkTerm_M5 AND licon1) |
| met1poly_M5 = INTERACT met1BulkTerm_M5 (li1poly_M5 AND mcon) |
| met2met1_M5 = INTERACT met2BulkTerm_M5 (met1poly_M5 AND via) |
| met3met2_M5 = INTERACT met3BulkTerm_M5 (met2met1_M5 AND via2) |
| met4met3_M5 = INTERACT met4BulkTerm_M5 (met3met2_M5 AND via3) |
| vppTermpoly_M5 = met4met3_M5 AND BulkTermCapVpp_M5 |
| vppTermNopoly_M5 = met4BulkTerm_M5 NOT met4met3_M5 |
| met1li1_M5 = INTERACT met1BulkTerm_M5 (li1BulkTerm_M5 AND mcon) |
| met2li1_M5 = INTERACT met2BulkTerm_M5 (met1li1_M5 AND via) |
| met3li1_M5 = INTERACT met3BulkTerm_M5 (met2li1_M5 AND via2) |
| met4li1_M5 = INTERACT met4BulkTerm_M5 (met3li1_M5 AND via3) |
| vppTermli1_M5 = met4li1_M5 AND BulkTermCapVpp_M5 |
| vppTermli1_M5_noM4 = (NOT INTERACT met3li1_M5 met4li1_M5) AND BulkTermCapVpp_M5 |
| met2met1_M5_noLi1 = INTERACT met2BulkTerm_M5 ((met1BulkTerm_m5 NOT met1li1_M5) AND via) |
| met3met1_M5_noLi1 = INTERACT met3BulkTerm_M5 (met2met1_M5_noLi1 AND via2) |
| met4met1_M5_noLi1 = INTERACT met4BulkTerm_M5 (met3met1_M5_noLi1 AND via3) |
| vppTermM1_M5 = met4met1_M5_noLi1 AND BulkTermCapVpp_M5 |
| vppTermM1_M5_noM4 = (NOT INTERACT met3met1_M5_noLi1 met4met1_M5_noLi1) AND BulkTermCapVpp_M5 |
| classN_met1li1 = INTERACT li1BulkTerm_M5 (met1BulkTerm_M5 AND mcon) |
| classN_li1poly = INTERACT polyBulkTerm_M5 (classN_met1li1 AND licon1) |
| classN_met1met2 = INTERACT met2BulkTerm_M5 (met1BulkTerm_M5 AND via) |
| classN_met2met3 = INTERACT met3BulkTerm_M5 (classN_met1met2 AND via2) |
| vppTerm_classN = INTERACT met4BulkTerm_M5 (classN_met2met3 AND via3) |
| |
| DEVICE xcmvpp xcmvpp vppTermBB(pin0) vppTermBB(pin1) BulkTermCap_cond(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( xcmvpp ) * L_scale2 |
| p = perimeter( xcmvpp ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp m m 0 |
| |
| DEVICE xcmvpp_2 xcmvpp_2 vppTermBB(pin0) vppTermBB(pin1) BulkTermCap_cond(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( xcmvpp_2 ) * L_scale2 |
| p = perimeter( xcmvpp_2 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_2 m m 0 |
| |
| DEVICE xcmvpp2_nhvnative10x4 xcmvpp_2nhvnative vppTermBBMos(pin0) vppTermBBMos(pin1) BulkTermCapMos_cond(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( xcmvpp_2nhvnative ) * L_scale2 |
| p = perimeter( xcmvpp_2nhvnative ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 |
| |
| DEVICE xcmvpp2_phv5x4 xcmvpp_2phv vppTermBBMos(pin0) vppTermBBMos(pin1) BulkTermCapMos_cond(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( xcmvpp_2phv ) * L_scale2 |
| p = perimeter( xcmvpp_2phv ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp2_phv5x4 m m 0 |
| |
| DEVICE xcmvpp_hd5_atlas_fingercap2_l5 vppcap_hd5_s vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_s ) * L_scale2 |
| p = perimeter( vppcap_hd5_s ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 |
| |
| DEVICE xcmvpp_hd5_atlas_wafflecap2 vppcap_hd5_r vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_r ) * L_scale2 |
| p = perimeter( vppcap_hd5_r ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 |
| |
| DEVICE xcmvpp_hd5_atlas_wafflecap1 vppcap_hd5_q vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_q ) * L_scale2 |
| p = perimeter( vppcap_hd5_q ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 |
| |
| DEVICE xcmvpp_hd5_atlas_fingercap_l40 vppcap_hd5_p vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_p ) * L_scale2 |
| p = perimeter( vppcap_hd5_p ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 |
| |
| DEVICE xcmvpp_hd5_atlas_fingercap_l20 vppcap_hd5_o vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_o ) * L_scale2 |
| p = perimeter( vppcap_hd5_o ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 |
| |
| DEVICE xcmvpp_hd5_atlas_fingercap_l10 vppcap_hd5_n vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_n ) * L_scale2 |
| p = perimeter( vppcap_hd5_n ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 |
| |
| DEVICE xcmvpp_hd5_atlas_fingercap_l5 vppcap_hd5_m vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_m ) * L_scale2 |
| p = perimeter( vppcap_hd5_m ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 |
| |
| DEVICE xcmvpp_hd5_5x2_met5pullin vppcap_hd5_l vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_l ) * L_scale2 |
| p = perimeter( vppcap_hd5_l ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 |
| |
| DEVICE xcmvpp_hd5_5x2 vppcap_hd5_k vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_k ) * L_scale2 |
| p = perimeter( vppcap_hd5_k ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 |
| |
| DEVICE xcmvpp_hd5_5x1_met5pullin vppcap_hd5_j vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_j ) * L_scale2 |
| p = perimeter( vppcap_hd5_j ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 |
| |
| DEVICE xcmvpp_hd5_5x1 vppcap_hd5_i vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_i ) * L_scale2 |
| p = perimeter( vppcap_hd5_i ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 |
| |
| DEVICE xcmvpp_hd5_4x2 vppcap_hd5_h vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_h ) * L_scale2 |
| p = perimeter( vppcap_hd5_h ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 |
| |
| DEVICE xcmvpp_hd5_4x1 vppcap_hd5_g vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_g ) * L_scale2 |
| p = perimeter( vppcap_hd5_g ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 |
| |
| DEVICE xcmvpp_hd5_3x2 vppcap_hd5_f vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_f ) * L_scale2 |
| p = perimeter( vppcap_hd5_f ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 |
| |
| DEVICE xcmvpp_hd5_3x1 vppcap_hd5_e vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_e ) * L_scale2 |
| p = perimeter( vppcap_hd5_e ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 |
| |
| DEVICE xcmvpp_hd5_2x2 vppcap_hd5_d vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_d ) * L_scale2 |
| p = perimeter( vppcap_hd5_d ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 |
| |
| DEVICE xcmvpp_hd5_2x1 vppcap_hd5_c vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_c ) * L_scale2 |
| p = perimeter( vppcap_hd5_c ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 |
| |
| DEVICE xcmvpp_hd5_1x2 vppcap_hd5_b vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_b ) * L_scale2 |
| p = perimeter( vppcap_hd5_b ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 |
| |
| DEVICE xcmvpp_hd5_1x1 vppcap_hd5_a vppTerm_classN(pin0) vppTerm_classN(pin1) BulkTermCap_condVpp_M5(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcap_hd5_a ) * L_scale2 |
| p = perimeter( vppcap_hd5_a ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 |
| |
| DEVICE xcmvppx4_2xnhvnative10x4 vppcapNHVnative vppTermpoly_M5(pin0) vppTermNopoly_M5(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppcapNHVnative ) * L_scale2 |
| p = perimeter( vppcapNHVnative ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_polym50p4shield cap140fF_7 vppTermpoly_M5(pin0) vppTermNoPoly_M5(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5_shrunk(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap140fF_7 ) * L_scale2 |
| p = perimeter( cap140fF_7 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 |
| |
| DEVICE xcmvpp4p4x4p6_m3_lim5shield cap140fF_6 vppTermli1_M5_noM4(pin0) vppTermM1_M5_noM4(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap140fF_6 ) * L_scale2 |
| p = perimeter( cap140fF_6 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_m3_lim5shield cap140fF_5 vppTermli1_M5_noM4(pin0) vppTermM1_M5_noM4(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap140fF_5 ) * L_scale2 |
| p = perimeter( cap140fF_5 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 |
| |
| DEVICE xcmvpp8p6x7p9_m3_lim5shield cap140fF_4 vppTermli1_M5_noM4(pin0) vppTermM1_M5_noM4(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap140fF_4 ) * L_scale2 |
| p = perimeter( cap140fF_4 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_lim5shield cap140fF_3 vppTermli1_M5(pin0) vppTermM1_M5(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap140fF_3 ) * L_scale2 |
| p = perimeter( cap140fF_3 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_polym5shield cap140fF_2 vppTermpoly_M5(pin0) vppTermNopoly_M5(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap140fF_2 ) * L_scale2 |
| p = perimeter( cap140fF_2 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_m5shield cap140fF_1 vppTermli1_M5(pin0) vppTermli1_M5(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap140fF_1 ) * L_scale2 |
| p = perimeter( cap140fF_1 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 |
| |
| DEVICE xcmvpp6p8x6p1_lim4shield vppM4shield4 vppTermli1_M4(pin0) vppTermM1_M4(pin1) BulkTermCap_condVpp_M4(pin2) topMetVpp_M4(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppM4shield4 ) * L_scale2 |
| p = perimeter( vppM4shield4 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 |
| |
| DEVICE xcmvpp6p8x6p1_polym4shield vppM4shield3 vppTermpoly_M4(pin0) vppTermNopoly_M4(pin1) BulkTermCap_condVpp_M4(pin2) topMetVpp_M4(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppM4shield3 ) * L_scale2 |
| p = perimeter( vppM4shield3 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_polym4shield vppM4shield2 vppTermpoly_M4(pin0) vppTermNopoly_M4(pin1) BulkTermCap_condVpp_M4(pin2) topMetVpp_M4(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppM4shield2 ) * L_scale2 |
| p = perimeter( vppM4shield2 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_m4shield vppM4shield1 vppTermli1_M4(pin0) vppTermli1_M4(pin1) BulkTermCap_condVpp_M4(pin2) topMetVpp_M4(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( vppM4shield1 ) * L_scale2 |
| p = perimeter( vppM4shield1 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 |
| |
| DEVICE xcmvpp1p8x1p8 cap1fF_liShield vppTermli1(pin0) vppTermNoli1(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap1fF_liShield ) * L_scale2 |
| p = perimeter( cap1fF_liShield ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp1p8x1p8 m m 0 |
| |
| DEVICE xcmvpp4p4x4p6_m3_lishield cap12fF_liShield vppTermli1(pin0) vppTermNoli1(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap12fF_liShield ) * L_scale2 |
| p = perimeter( cap12fF_liShield ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 |
| |
| DEVICE xcmvpp8p6x7p9_m3_lishield cap50fF_liShield vppTermli1(pin0) vppTermNoli1(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap50fF_liShield ) * L_scale2 |
| p = perimeter( cap50fF_liShield ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_m3_lishield cap100fF_liShield vppTermli1(pin0) vppTermNoli1(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap100fF_liShield ) * L_scale2 |
| p = perimeter( cap100fF_liShield ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_m3shield cap100fF vppTermpoly(c0) vppTermNopoly(c1) BulkTermCap_condVpp(b) topMetVpp(term4) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap100fF ) * L_scale2 |
| p = perimeter( cap100fF ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 |
| |
| DEVICE xcmvpp8p6x7p9_m3shield cap50fF vppTermpoly(c0) vppTermNopoly(c1) BulkTermCap_condVpp(b) topMetVpp(term4) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap50fF ) * L_scale2 |
| p = perimeter( cap50fF ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 |
| |
| DEVICE xcmvpp4p4x4p6_m3shield cap12fF vppTermpoly(c0) vppTermNopoly(c1) BulkTermCap_condVpp(b) topMetVpp(term4) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap12fF ) * L_scale2 |
| p = perimeter( cap12fF ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 |
| |
| DEVICE xcmvpp1p8x1p8_m3shield cap1fF vppTermli1(c0) vppTermNoli1(c1) BulkTermCap_condVpp(b) topMetVpp(term4) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap1fF ) * L_scale2 |
| p = perimeter( cap1fF ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_m1m4m5shield cap100fF_mm5shield vppTermM1_M5(pin0) vppTermM1_M5(pin1) BulkTermCap_condVpp_M5(pin2) topMetVpp_M5(pin3) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap100fF_mm5shield ) * L_scale2 |
| p = perimeter( cap100fF_mm5shield ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_m1m4 cap100fF_m3m4 vppTermM1_M5(pin0) vppTermM1_M5(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap100fF_m3m4 ) * L_scale2 |
| p = perimeter( cap100fF_m3m4 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 |
| |
| DEVICE xcmvpp11p5x11p7_m1m2 cap100fF_m1m2 vppTermBB(pin0) vppTermBB(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap100fF_m1m2 ) * L_scale2 |
| p = perimeter( cap100fF_m1m2 ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 |
| |
| DEVICE xcmvpp4p4x4p6_m1m2 cap12fF_noShield vppTermBB(pin0) vppTermBB(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap12fF_noShield ) * L_scale2 |
| p = perimeter( cap12fF_noShield ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 |
| |
| DEVICE xcmvpp5 cap5fF vppTermBB(pin0) vppTermBB(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap5fF ) * L_scale2 |
| p = perimeter( cap5fF ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp5 m m 0 |
| |
| DEVICE xcmvpp4 cap10fF vppTermBB(pin0) vppTermBB(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap10fF ) * L_scale2 |
| p = perimeter( cap10fF ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp4 m m 0 |
| |
| DEVICE xcmvpp3 cap35fF vppTermBB(pin0) vppTermBB(pin1) BulkTermCap_condVpp(pin2) BY NET [ |
| PROPERTY m |
| m = 1 |
| a = area( cap35fF ) * L_scale2 |
| p = perimeter( cap35fF ) * L_scale |
| ] |
| |
| |
| TRACE PROPERTY xcmvpp3 m m 0 |
| |
| // ;ss |
| |
| "r_768_Illegal vppcaps capdraw must not overlap fuse" { |
| @ Illegal vppcaps: capdraw must not overlap fuse |
| capdraw AND fuse |
| } |
| "r_769_Illegal vppcaps capdraw must not overlap LVID" { |
| @ Illegal vppcaps: capdraw must not overlap LVID |
| capdraw AND LVID |
| } |
| "r_770_Illegal vppcaps capdraw must not overlap ENID" { |
| @ Illegal vppcaps: capdraw must not overlap ENID |
| capdraw AND ENID |
| } |
| "r_771_Illegal vppcaps capdraw must not overlap COREID" { |
| @ Illegal vppcaps: capdraw must not overlap COREID |
| capdraw AND COREID |
| } |
| "r_772_Illegal vppcaps capdraw must not overlap PHdiodeID" { |
| @ Illegal vppcaps: capdraw must not overlap PHdiodeID |
| capdraw AND PHdiodeID |
| } |
| |
| // ;ss added bump to match lvsRules |
| // indRDL = rdl AND inductor |
| |
| indRDL = (NOT INTERACT rdl bump) AND inductor |
| |
| indMET5 = met5 AND inductor |
| indMET3 = met3 AND inductor |
| indMcon = (mcon AND inductor) NOT tap |
| xind4 = inductor AND (EXTENT CELL "*xind4*") |
| ind4T1_rdl = xind4 AND (indTerm1 AND indRDL) |
| ind4T2_rdl = xind4 AND (indTerm2 AND indRDL) |
| ind4Center_met5 = xind4 AND (indTerm3 AND indMET5) |
| ind4Center_rdl = NOT INTERACT (xind4 AND (indTerm3 AND indRDL)) ind4Center_met5 |
| ind4T1_met5 = xind4 AND (indTerm1 AND indMET5) |
| ind4T2_met5 = xind4 AND (indTerm2 AND indMET5) |
| ind4Center_met3 = xind4 AND (indTerm3 AND indMET3) |
| ind4Shield_outer_met1 = (met1 NOT inductor) TOUCH (xind4 AND met1) |
| ind4Shield_gnd_met1 = INTERACT ind4shield_outer_met1 (mcon AND tap) |
| ind4Shield = (xind4 AND met1) TOUCH ind4shield_gnd_met1 |
| balun = inductor AND (EXTENT CELL "*balun*") |
| balunT1 = balun AND (indTerm1 AND indMET5) |
| balunT2 = balun AND (indTerm2 AND indMET5) |
| balunT3 = balun AND (indTerm1 AND indRDL) |
| balunT4 = balun AND (indTerm2 AND indRDL) |
| balunCenter = balun AND (indTerm3 AND indMET5) |
| balunShield = INTERACT (balun AND met1) indMcon |
| met5_inductor = (INTERACT inductor ind4T1_met5) AND |
| ((INTERACT inductor ind4T2_met5) AND (INTERACT inductor ind4Center_met3)) |
| rdl_inductor = (INTERACT inductor ind4T1_rdl) AND |
| ((INTERACT inductor ind4T2_rdl) AND (INTERACT inductor ind4Center_met5)) |
| |
| DEVICE balun(balun) balun balunT1(pin0) balunT2(pin1) balunT3(pin2) balunT4(pin3) balunCenter(pin4) balunShield(pin5) BY NET NETLIST MODEL balun TEXT MODEL LAYER textdraw |
| |
| |
| DEVICE ind4(xind4) xind4 ind4T1_rdl(pin0) ind4T2_rdl(pin1) ind4Center_rdl(pin2) ind4Shield(pin3) BY NET TEXT MODEL LAYER textdraw |
| |
| |
| DEVICE ind4(xind4) xind4 ind4T1_rdl(pin0) ind4T2_rdl(pin1) ind4Center_met5(pin2) ind4Shield(pin3) BY NET TEXT MODEL LAYER textdraw |
| |
| |
| DEVICE ind4(xind4) xind4 ind4T1_met5(pin0) ind4T2_met5(pin1) ind4Center_met3(pin2) ind4Shield(pin3) BY NET TEXT MODEL LAYER textdraw |
| |
| // ;ss match lvsRules |
| |
| "r_773_Illegal inductor device xind4 must not overlap capacitor" { |
| @ Illegal inductor device: xind4 must not overlap capacitor |
| xind4 AND capacitor |
| } |
| "r_774_Illegal inductor device xind4 must not overlap LVID" { |
| @ Illegal inductor device: xind4 must not overlap LVID |
| xind4 AND LVID |
| } |
| "r_775_Illegal inductor device xind4 must not overlap ENID" { |
| @ Illegal inductor device: xind4 must not overlap ENID |
| xind4 AND ENID |
| } |
| "r_776_Illegal inductor device xind4 must not overlap localSub" { |
| @ Illegal inductor device: xind4 must not overlap localSub |
| xind4 AND localSub |
| } |
| "r_777_Illegal inductor device xind4 must not overlap pnp" { |
| @ Illegal inductor device: xind4 must not overlap pnp |
| xind4 AND pnp |
| } |
| "r_778_Illegal inductor device xind4 must not overlap npn" { |
| @ Illegal inductor device: xind4 must not overlap npn |
| xind4 AND npn |
| } |
| "r_779_Illegal inductor device xind4 must not overlap DiodeID" { |
| @ Illegal inductor device: xind4 must not overlap DiodeID |
| xind4 AND DiodeID |
| } |
| "r_780_Illegal inductor device xind4 must not overlap PHdiodeID" { |
| @ Illegal inductor device: xind4 must not overlap PHdiodeID |
| xind4 AND PHdiodeID |
| } |
| "r_781_Illegal inductor device xind4 must not overlap COREID" { |
| @ Illegal inductor device: xind4 must not overlap COREID |
| xind4 AND COREID |
| } |
| "r_782_Illegal met5 cu device balun must not overlap capacitor" { |
| @ Illegal met5 cu device: balun must not overlap capacitor |
| balun AND capacitor |
| } |
| "r_783_Illegal met5 cu device balun must not overlap LVID" { |
| @ Illegal met5 cu device: balun must not overlap LVID |
| balun AND LVID |
| } |
| "r_784_Illegal met5 cu device balun must not overlap ENID" { |
| @ Illegal met5 cu device: balun must not overlap ENID |
| balun AND ENID |
| } |
| "r_785_Illegal met5 cu device balun must not overlap localSub" { |
| @ Illegal met5 cu device: balun must not overlap localSub |
| balun AND localSub |
| } |
| "r_786_Illegal met5 cu device balun must not overlap pnp" { |
| @ Illegal met5 cu device: balun must not overlap pnp |
| balun AND pnp |
| } |
| "r_787_Illegal met5 cu device balun must not overlap npn" { |
| @ Illegal met5 cu device: balun must not overlap npn |
| balun AND npn |
| } |
| "r_788_Illegal met5 cu device balun must not overlap DiodeID" { |
| @ Illegal met5 cu device: balun must not overlap DiodeID |
| balun AND DiodeID |
| } |
| "r_789_Illegal met5 cu device balun must not overlap PHdiodeID" { |
| @ Illegal met5 cu device: balun must not overlap PHdiodeID |
| balun AND PHdiodeID |
| } |
| "r_790_Illegal met5 cu device balun must not overlap COREID" { |
| @ Illegal met5 cu device: balun must not overlap COREID |
| balun AND COREID |
| } |
| "r_791_Illegal met5 cu inductor device met5_inductor must not overlap ind4Center_met5" { |
| @ Illegal met5 cu inductor device: met5_inductor must not overlap ind4Center_met5 |
| met5_inductor AND ind4Center_met5 |
| } |
| "r_792_Illegal rdl cu inductor device rdl_inductor must not overlap ind4Center_met3" { |
| @ Illegal rdl cu inductor device: rdl_inductor must not overlap ind4Center_met3 |
| rdl_inductor AND ind4Center_met3 |
| } |
| |
| //adding capm and cap2m here |
| capm_mimcap = INTERACT (capm AND met3) ((capm AND met3) AND via3) |
| cap2m_mimcap = INTERACT (cap2m AND met4) ((cap2m AND met4) AND via4) |
| capmvia3 = via3 AND capm |
| cap2mvia4 = via4 AND cap2m |
| via3_notcapm = via3 NOT capm |
| via4_notcap2m = via4 NOT cap2m |
| q2capm = COPY 3000 |
| q3capm = COPY capm |
| capm_cond = q3capm NOT q2capm |
| q2cap2m = COPY 3001 |
| q3cap2m = COPY cap2m |
| cap2m_cond = q3cap2m NOT q2cap2m |
| |
| DEVICE C(xcmimc1) capm_mimcap capm_cond(POS) MET3_cond(NEG) BY NET [ |
| PROPERTY w , l , m |
| m = 1 |
| a = area( capm_mimcap ) * L_scale2 |
| p = perimeter( capm_mimcap ) * L_scale |
| determinant = (p * p) - (16.0 * a) |
| if (abs(determinant) < 1e-8) { |
| determinant = 0 |
| } |
| if (determinant >= 0 && a != 0) { |
| l = (p - sqrt(determinant)) / 4.0 |
| } else { |
| l = p / 6.0 |
| } |
| w = a / l |
| ] |
| |
| CMACRO TRACE_CAP C xcmimc1 w l m |
| CMACRO TRACE_CAP C xcmimc2 w l m |
| |
| //TRACE PROPERTY C(xcmimc1) w w 1 |
| //TRACE PROPERTY C(xcmimc1) l l 1 |
| //TRACE PROPERTY C(xcmimc1) m m 0 |
| |
| |
| LVS REDUCE C(xcmimc1) PARALLEL YES [ |
| TOLERANCE w 1 |
| l 1 |
| EFFECTIVE w , l , m |
| m = SUM( m ) |
| w = SUM( (w) ) / m |
| l = SUM( (l) ) / m |
| ] |
| |
| |
| |
| DEVICE C(xcmimc2) cap2m_mimcap cap2m_cond(POS) MET4_cond(NEG) BY NET [ |
| PROPERTY w , l , m |
| m = 1 |
| a = area( cap2m_mimcap ) * L_scale2 |
| p = perimeter( cap2m_mimcap ) * L_scale |
| determinant = (p * p) - (16.0 * a) |
| if (abs(determinant) < 1e-8) { |
| determinant = 0 |
| } |
| if (determinant >= 0 && a != 0) { |
| l = (p - sqrt(determinant)) / 4.0 |
| } else { |
| l = p / 6.0 |
| } |
| w = a / l |
| ] |
| |
| |
| //TRACE PROPERTY C(xcmimc2) w w 1 |
| //TRACE PROPERTY C(xcmimc2) l l 1 |
| //TRACE PROPERTY C(xcmimc2) m m 0 |
| |
| LVS REDUCE C(xcmimc2) PARALLEL YES [ |
| TOLERANCE w 1 |
| l 1 |
| EFFECTIVE w , l , m |
| m = SUM( m ) |
| w = SUM( (w) ) / m |
| l = SUM( (l) ) / m |
| ] |
| |
| /// |
| |
| mrdn_lv = NMOSDIFFnotHVInotPOLY AND diffres |
| q1mrdn_lv = mrdn_lv AND diffcut |
| q2mrdn_lv = mrdn_lv NOT (mrdn_lv ENCLOSE (mrdn_lv NOT diffcut) == 2) |
| "r_793_resistorError" { |
| @ resistorError: diffcut does not divide NMOSDIFFnotHVInotPOLY in two |
| COPY q2mrdn_lv |
| } |
| q6mrdn_lv = mrdn_lv INSIDE EDGE NMOSDIFFnotHVInotPOLY |
| q7mrdn_lv = q6mrdn_lv NOT OUTSIDE EDGE q1mrdn_lv |
| q5mrdn_lv = q7mrdn_lv NOT COINCIDENT OUTSIDE EDGE q1mrdn_lv |
| q8mrdn_lv = EXPAND EDGE q5mrdn_lv INSIDE BY 0.005 |
| q3mrdn_lv = NOT TOUCH (INTERACT mrdn_lv q8mrdn_lv) q8mrdn_lv |
| q4mrdn_lv = q2mrdn_lv OR q3mrdn_lv |
| q9mrdn_lv = q1mrdn_lv NOT q4mrdn_lv |
| "r_794_resistorError" { |
| @ resistorError: badd diffcut use/orientation, must not touch the terminal |
| COPY q3mrdn_lv |
| } |
| mrdn_hv = NMOSDIFFandHVInotPOLY AND diffres |
| q1mrdn_hv = mrdn_hv AND diffcut |
| q2mrdn_hv = mrdn_hv NOT (mrdn_hv ENCLOSE (mrdn_hv NOT diffcut) == 2) |
| "r_795_resistorError" { |
| @ resistorError: diffcut does not divide NMOSDIFFandHVInotPOLY in two |
| COPY q2mrdn_hv |
| } |
| q6mrdn_hv = mrdn_hv INSIDE EDGE NMOSDIFFandHVInotPOLY |
| q7mrdn_hv = q6mrdn_hv NOT OUTSIDE EDGE q1mrdn_hv |
| q5mrdn_hv = q7mrdn_hv NOT COINCIDENT OUTSIDE EDGE q1mrdn_hv |
| q8mrdn_hv = EXPAND EDGE q5mrdn_hv INSIDE BY 0.005 |
| q3mrdn_hv = (INTERACT mrdn_hv q8mrdn_hv) NOT TOUCH q8mrdn_hv |
| q4mrdn_hv = q2mrdn_hv OR q3mrdn_hv |
| q9mrdn_hv = q1mrdn_hv NOT q4mrdn_hv |
| "r_796_resistorError" { |
| @ resistorError: badd diffcut use/orientation, must not touch the terminal |
| COPY q3mrdn_hv |
| } |
| mrdp_lv = PMOSDIFFnotHVInotPOLY AND diffres |
| q1mrdp_lv = mrdp_lv AND diffcut |
| q2mrdp_lv = mrdp_lv NOT (mrdp_lv ENCLOSE (mrdp_lv NOT diffcut) == 2) |
| "r_797_resistorError" { |
| @ resistorError: diffcut does not divide PMOSDIFFnotHVInotPOLY in two |
| COPY q2mrdp_lv |
| } |
| q6mrdp_lv = mrdp_lv INSIDE EDGE PMOSDIFFnotHVInotPOLY |
| q7mrdp_lv = q6mrdp_lv NOT OUTSIDE EDGE q1mrdp_lv |
| q5mrdp_lv = q7mrdp_lv NOT COINCIDENT OUTSIDE EDGE q1mrdp_lv |
| q8mrdp_lv = EXPAND EDGE q5mrdp_lv INSIDE BY 0.005 |
| q3mrdp_lv = (INTERACT mrdp_lv q8mrdp_lv) NOT TOUCH q8mrdp_lv |
| q4mrdp_lv = q2mrdp_lv OR q3mrdp_lv |
| q9mrdp_lv = q1mrdp_lv NOT q4mrdp_lv |
| "r_798_resistorError" { |
| @ resistorError: badd diffcut use/orientation, must not touch the terminal |
| COPY q3mrdp_lv |
| } |
| mrdp_hv = PMOSDIFFandHVInotPOLY AND diffres |
| q1mrdp_hv = mrdp_hv AND diffcut |
| q2mrdp_hv = mrdp_hv NOT (mrdp_hv ENCLOSE (mrdp_hv NOT diffcut) == 2) |
| "r_799_resistorError" { |
| @ resistorError: diffcut does not divide PMOSDIFFandHVInotPOLY in two |
| COPY q2mrdp_hv |
| } |
| q6mrdp_hv = mrdp_hv INSIDE EDGE PMOSDIFFandHVInotPOLY |
| q7mrdp_hv = q6mrdp_hv NOT OUTSIDE EDGE q1mrdp_hv |
| q5mrdp_hv = q7mrdp_hv NOT COINCIDENT OUTSIDE EDGE q1mrdp_hv |
| q8mrdp_hv = EXPAND EDGE q5mrdp_hv INSIDE BY 0.005 |
| q3mrdp_hv = (INTERACT mrdp_hv q8mrdp_hv) NOT TOUCH q8mrdp_hv |
| q4mrdp_hv = q2mrdp_hv OR q3mrdp_hv |
| q9mrdp_hv = q1mrdp_hv NOT q4mrdp_hv |
| "r_800_resistorError" { |
| @ resistorError: badd diffcut use/orientation, must not touch the terminal |
| COPY q3mrdp_hv |
| } |
| |
| //DEVICE R(mrdn) mrdn_lv NDIFF_cond(POS) NDIFF_cond(NEG) <NMOSDIFFnotHVInotPOLY> ("POS" "NEG") BY NET [ |
| DEVICE mrdn mrdn_lv NDIFF_cond(POS) NDIFF_cond(NEG) Substrate(SUB) <NMOSDIFFnotHVInotPOLY> ("POS" "NEG") BY NET [ |
| PROPERTY w , l , m |
| dev_perim = perimeter( mrdn_lv ) * 0.5 * L_scale |
| w = perimeter_inside( mrdn_lv , NMOSDIFFnotHVInotPOLY ) * 0.5 * L_scale |
| nbend = bends( mrdn_lv ) |
| l = dev_perim - (w * (1 + (nbend * 0.5))) |
| m = 1 |
| ] |
| |
| LVS DEVICE TYPE RESISTOR mrdn |
| CMACRO TRACE_PARAM mrdn m w l |
| //TRACE PROPERTY R(mrdn) w w 1 |
| //TRACE PROPERTY R(mrdn) l l 1 |
| //TRACE PROPERTY R(mrdn) m m 0 |
| |
| //DEVICE R(mrdn_hv) mrdn_hv NDIFF_cond(POS) NDIFF_cond(NEG) Substrate(SUB) <NMOSDIFFandHVInotPOLY> ("POS" "NEG") BY NET [ |
| DEVICE mrdn_hv mrdn_hv NDIFF_cond(POS) NDIFF_cond(NEG) Substrate(SUB) <NMOSDIFFandHVInotPOLY> ("POS" "NEG") BY NET [ |
| PROPERTY w , l , m |
| dev_perim = perimeter( mrdn_hv ) * 0.5 * L_scale |
| w = perimeter_inside( mrdn_hv , NMOSDIFFandHVInotPOLY ) * 0.5 * L_scale |
| nbend = bends( mrdn_hv ) |
| l = dev_perim - (w * (1 + (nbend * 0.5))) |
| m = 1 |
| ] |
| |
| LVS DEVICE TYPE RESISTOR mrdn_hv |
| CMACRO TRACE_PARAM mrdn_hv m w l |
| //TRACE PROPERTY R(mrdn_hv) w w 1 |
| //TRACE PROPERTY R(mrdn_hv) l l 1 |
| //TRACE PROPERTY R(mrdn_hv) m m 0 |
| |
| //DEVICE R(mrdp) mrdp_lv PDIFF_cond(POS) PDIFF_cond(NEG) <PMOSDIFFnotHVInotPOLY> ("POS" "NEG") BY NET [ |
| DEVICE mrdp mrdp_lv PDIFF_cond(POS) PDIFF_cond(NEG) MosNwell(SUB) <PMOSDIFFnotHVInotPOLY> ("POS" "NEG") BY NET [ |
| PROPERTY w , l , m |
| dev_perim = perimeter( mrdp_lv ) * 0.5 * L_scale |
| w = perimeter_inside( mrdp_lv , PMOSDIFFnotHVInotPOLY ) * 0.5 * L_scale |
| nbend = bends( mrdp_lv ) |
| l = dev_perim - (w * (1 + (nbend * 0.5))) |
| m = 1 |
| ] |
| |
| LVS DEVICE TYPE RESISTOR mrdp |
| CMACRO TRACE_PARAM mrdp m w l |
| //TRACE PROPERTY R(mrdp) w w 1 |
| //TRACE PROPERTY R(mrdp) l l 1 |
| //TRACE PROPERTY R(mrdp) m m 0 |
| |
| //DEVICE R(mrdp_hv) mrdp_hv PDIFF_cond(POS) PDIFF_cond(NEG) <PMOSDIFFandHVInotPOLY> ("POS" "NEG") BY NET [ |
| DEVICE mrdp_hv mrdp_hv PDIFF_cond(POS) PDIFF_cond(NEG) MosNwell(SUB) <PMOSDIFFandHVInotPOLY> ("POS" "NEG") BY NET [ |
| PROPERTY w , l , m |
| dev_perim = perimeter( mrdp_hv ) * 0.5 * L_scale |
| w = perimeter_inside( mrdp_hv , PMOSDIFFandHVInotPOLY ) * 0.5 * L_scale |
| nbend = bends( mrdp_hv ) |
| l = dev_perim - (w * (1 + (nbend * 0.5))) |
| m = 1 |
| ] |
| |
| LVS DEVICE TYPE RESISTOR mrdp_hv |
| CMACRO TRACE_PARAM mrdp_hv m w l |
| //TRACE PROPERTY R(mrdp_hv) w w 1 |
| //TRACE PROPERTY R(mrdp_hv) l l 1 |
| //TRACE PROPERTY R(mrdp_hv) m m 0 |
| |
| mrp1 = poly AND polyresNorm |
| q1mrp1 = mrp1 AND polycut |
| q2mrp1 = mrp1 NOT (mrp1 ENCLOSE (mrp1 NOT polycut) == 2) |
| "r_801_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2mrp1 |
| } |
| q6mrp1 = mrp1 INSIDE EDGE poly |
| q7mrp1 = q6mrp1 NOT OUTSIDE EDGE q1mrp1 |
| q5mrp1 = q7mrp1 NOT COINCIDENT OUTSIDE EDGE q1mrp1 |
| q8mrp1 = EXPAND EDGE q5mrp1 INSIDE BY 0.005 |
| q3mrp1 = (INTERACT mrp1 q8mrp1) NOT TOUCH q8mrp1 |
| q4mrp1 = q2mrp1 OR q3mrp1 |
| q9mrp1 = q1mrp1 NOT q4mrp1 |
| "r_802_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3mrp1 |
| } |
| |
| //DEVICE R(mrp1) mrp1 POLY_cond(POS) POLY_cond(NEG) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // dev_perim = perimeter( mrp1 ) * 0.5 * 1e-6 |
| // w = perimeter_inside( mrp1 , poly ) * 0.5 * 1e-6 |
| // nbend = bends( mrp1 ) |
| // l = dev_perim - (w * (1 + (nbend * 0.5))) |
| // m = 1 |
| // ] |
| |
| DEVICE R(mrp1) mrp1 POLY_cond(POS) POLY_cond(NEG) <poly> ("POS" "NEG") BY NET |
| CMACRO RES mrp1 poly "mrp1" |
| CMACRO TRACE_PARAM_MODEL R mrp1 m w l |
| CMACRO REDUCE_PARALLEL_R mrp1 m w l |
| //TRACE PROPERTY R(mrp1) w w 1 |
| //TRACE PROPERTY R(mrp1) l l 1 |
| //TRACE PROPERTY R(mrp1) m m 0 |
| |
| mrl1 = li1 AND li1res |
| q1mrl1 = mrl1 AND li1cut |
| q2mrl1 = mrl1 NOT (mrl1 ENCLOSE (mrl1 NOT li1cut) == 2) |
| "r_803_resistorError" { |
| @ resistorError: li1cut does not divide li1 in two |
| COPY q2mrl1 |
| } |
| q6mrl1 = mrl1 INSIDE EDGE li1 |
| q7mrl1 = q6mrl1 NOT OUTSIDE EDGE q1mrl1 |
| q5mrl1 = q7mrl1 NOT COINCIDENT OUTSIDE EDGE q1mrl1 |
| q8mrl1 = EXPAND EDGE q5mrl1 INSIDE BY 0.005 |
| q3mrl1 = (INTERACT mrl1 q8mrl1) NOT TOUCH q8mrl1 |
| q4mrl1 = q2mrl1 OR q3mrl1 |
| q9mrl1 = q1mrl1 NOT q4mrl1 |
| "r_804_resistorError" { |
| @ resistorError: badd li1cut use/orientation, must not touch the terminal |
| COPY q3mrl1 |
| } |
| |
| DEVICE R(mrl1) mrl1 LI1_cond(POS) LI1_cond(NEG) <li1> ("POS" "NEG") BY NET [ |
| PROPERTY w , l , m |
| dev_perim = perimeter( mrl1 ) * 0.5 * L_scale |
| w = perimeter_inside( mrl1 , li1 ) * 0.5 * L_scale |
| nbend = bends( mrl1 ) |
| l = dev_perim - (w * (1 + (nbend * 0.5))) |
| m = 1 |
| ] |
| |
| TRACE PROPERTY R(mrl1) w w 1 |
| TRACE PROPERTY R(mrl1) l l 1 |
| TRACE PROPERTY R(mrl1) m m 0 |
| |
| //polyresPrec = polyres AND rpm |
| polyresPrec = polyres AND (rpm NOT urpm) |
| upolyresPrec = polyres AND (urpm NOT rpm) |
| polyresNorm = polyres NOT ((rpm OR urpm) OR contResID) |
| precisionPolyRes = ((polyresPrec NOT upolyresPrec) AND poly) NOT contResID |
| uprecisionPolyRes = ((upolyresPrec NOT polyresPrec) AND poly) NOT contResID |
| precisionPolyTerm = (INTERACT poly precisionPolyRes) NOT precisionPolyRes |
| uprecisionPolyTerm = (INTERACT poly uprecisionPolyRes) NOT uprecisionPolyRes |
| polyXmtPrec = poly NOT (polyresPrec OR upolyresPrec) |
| xhrpoly_0p35 = INTERACT (precisionPolyRes WITH EDGE ((INTERNAL [precisionPolyRes] == 0.35) NOT TOUCH EDGE licon1)) (INTERACT precisionPolyTerm licon1 == 1) == 2 |
| xuhrpoly_0p35 = INTERACT (uprecisionPolyRes WITH EDGE ((INTERNAL [uprecisionPolyRes] == 0.35) NOT TOUCH EDGE licon1)) (INTERACT uprecisionPolyTerm licon1 == 1) == 2 |
| xhrpoly_0p69 = INTERACT (precisionPolyRes WITH EDGE ((INTERNAL [precisionPolyRes] == 0.69) NOT TOUCH EDGE licon1)) (INTERACT precisionPolyTerm licon1 == 1) == 2 |
| xuhrpoly_0p69 = INTERACT (uprecisionPolyRes WITH EDGE ((INTERNAL [uprecisionPolyRes] == 0.69) NOT TOUCH EDGE licon1)) (INTERACT uprecisionPolyTerm licon1 == 1) == 2 |
| xhrpoly_1p41 = INTERACT (precisionPolyRes WITH EDGE ((INTERNAL [precisionPolyRes] == 1.41) NOT TOUCH EDGE licon1)) (INTERACT precisionPolyTerm licon1 == 2) == 2 |
| xuhrpoly_1p41 = INTERACT (uprecisionPolyRes WITH EDGE ((INTERNAL [uprecisionPolyRes] == 1.41) NOT TOUCH EDGE licon1)) (INTERACT uprecisionPolyTerm licon1 == 2) == 2 |
| xhrpoly_2p85 = INTERACT (precisionPolyRes WITH EDGE ((INTERNAL [precisionPolyRes] == 2.85) NOT TOUCH EDGE licon1)) (INTERACT precisionPolyTerm licon1 == 4) == 2 |
| xuhrpoly_2p85 = INTERACT (uprecisionPolyRes WITH EDGE ((INTERNAL [uprecisionPolyRes] == 2.85) NOT TOUCH EDGE licon1)) (INTERACT uprecisionPolyTerm licon1 == 4) == 2 |
| xhrpoly_5p73 = INTERACT (precisionPolyRes WITH EDGE ((INTERNAL [precisionPolyRes] == 5.73) NOT TOUCH EDGE licon1)) (INTERACT precisionPolyTerm licon1 == 8) == 2 |
| xuhrpoly_5p73 = INTERACT (uprecisionPolyRes WITH EDGE ((INTERNAL [uprecisionPolyRes] == 5.73) NOT TOUCH EDGE licon1)) (INTERACT uprecisionPolyTerm licon1 == 8) == 2 |
| |
| precisionPolyRes_cont = ((polyresPrec NOT upolyresPrec) AND poly) AND contResID |
| xhrpoly_base = COPY precisionPolyRes_cont |
| xhrpoly_base_sub = precisionPolyRes_cont NOT MosNwell |
| q1xhrpoly_base_sub = xhrpoly_base_sub AND polycut |
| q2xhrpoly_base_sub = xhrpoly_base_sub NOT (xhrpoly_base_sub ENCLOSE (xhrpoly_base_sub NOT polycut) == 2) |
| q6xhrpoly_base_sub = xhrpoly_base_sub INSIDE EDGE poly |
| q7xhrpoly_base_sub = q6xhrpoly_base_sub NOT OUTSIDE EDGE q1xhrpoly_base_sub |
| q5xhrpoly_base_sub = q7xhrpoly_base_sub NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_base_sub |
| q8xhrpoly_base_sub = EXPAND EDGE q5xhrpoly_base_sub INSIDE BY 0.005 |
| q3xhrpoly_base_sub = (INTERACT xhrpoly_base_sub q8xhrpoly_base_sub) NOT TOUCH q8xhrpoly_base_sub |
| q4xhrpoly_base_sub = q2xhrpoly_base_sub OR q3xhrpoly_base_sub |
| q9xhrpoly_base_sub = q1xhrpoly_base_sub NOT q4xhrpoly_base_sub |
| |
| xhrpoly_base_nwell = precisionPolyRes_cont AND MosNwell |
| q1xhrpoly_base_nwell = xhrpoly_base_nwell AND polycut |
| q2xhrpoly_base_nwell = xhrpoly_base_nwell NOT (xhrpoly_base_nwell ENCLOSE (xhrpoly_base_nwell NOT polycut) == 2) |
| q6xhrpoly_base_nwell = xhrpoly_base_nwell INSIDE EDGE poly |
| q7xhrpoly_base_nwell = q6xhrpoly_base_nwell NOT OUTSIDE EDGE q1xhrpoly_base_nwell |
| q5xhrpoly_base_nwell = q7xhrpoly_base_nwell NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_base_nwell |
| q8xhrpoly_base_nwell = EXPAND EDGE q5xhrpoly_base_nwell INSIDE BY 0.005 |
| q3xhrpoly_base_nwell = NOT TOUCH (INTERACT xhrpoly_base_nwell q8xhrpoly_base_nwell) q8xhrpoly_base_nwell |
| q4xhrpoly_base_nwell = q2xhrpoly_base_nwell OR q3xhrpoly_base_nwell |
| q9xhrpoly_base_nwell = q1xhrpoly_base_nwell NOT q4xhrpoly_base_nwell |
| |
| |
| uprecisionPolyRes_cont = ((upolyresPrec NOT polyresPrec) AND poly) AND contResID |
| xuhrpoly_base = COPY uprecisionPolyRes_cont |
| xuhrpoly_base_sub = uprecisionPolyRes_cont NOT MosNwell |
| q1xuhrpoly_base_sub = xuhrpoly_base_sub AND polycut |
| q2xuhrpoly_base_sub = xuhrpoly_base_sub NOT (xuhrpoly_base_sub ENCLOSE (xuhrpoly_base_sub NOT polycut) == 2) |
| q6xuhrpoly_base_sub = xuhrpoly_base_sub INSIDE EDGE poly |
| q7xuhrpoly_base_sub = q6xuhrpoly_base_sub NOT OUTSIDE EDGE q1xuhrpoly_base_sub |
| q5xuhrpoly_base_sub = q7xuhrpoly_base_sub NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_base_sub |
| q8xuhrpoly_base_sub = EXPAND EDGE q5xuhrpoly_base_sub INSIDE BY 0.005 |
| q3xuhrpoly_base_sub = (INTERACT xuhrpoly_base_sub q8xuhrpoly_base_sub) NOT TOUCH q8xuhrpoly_base_sub |
| q4xuhrpoly_base_sub = q2xuhrpoly_base_sub OR q3xuhrpoly_base_sub |
| q9xuhrpoly_base_sub = q1xuhrpoly_base_sub NOT q4xuhrpoly_base_sub |
| |
| |
| |
| xuhrpoly_base_nwell = uprecisionPolyRes_cont AND MosNwell |
| q1xuhrpoly_base_nwell = xuhrpoly_base_nwell AND polycut |
| q2xuhrpoly_base_nwell = xuhrpoly_base_nwell NOT (xuhrpoly_base_nwell ENCLOSE (xuhrpoly_base_nwell NOT polycut) == 2) |
| q6xuhrpoly_base_nwell = xuhrpoly_base_nwell INSIDE EDGE poly |
| q7xuhrpoly_base_nwell = q6xuhrpoly_base_nwell NOT OUTSIDE EDGE q1xuhrpoly_base_nwell |
| q5xuhrpoly_base_nwell = q7xuhrpoly_base_nwell NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_base_nwell |
| q8xuhrpoly_base_nwell = EXPAND EDGE q5xuhrpoly_base_nwell INSIDE BY 0.005 |
| q3xuhrpoly_base_nwell = NOT TOUCH (INTERACT xuhrpoly_base_nwell q8xuhrpoly_base_nwell) q8xuhrpoly_base_nwell |
| q4xuhrpoly_base_nwell = q2xuhrpoly_base_nwell OR q3xuhrpoly_base_nwell |
| q9xuhrpoly_base_nwell = q1xuhrpoly_base_nwell NOT q4xuhrpoly_base_nwell |
| //"r_806_resistorError" { |
| // @ resistorError: bad polycut use/orientation, must not touch the terminal |
| // COPY q3xhrpoly_0p35_nwell |
| // } |
| |
| |
| xhrpoly_0p35_nwell = xhrpoly_0p35 AND MosNwell |
| q1xhrpoly_0p35_nwell = xhrpoly_0p35_nwell AND polycut |
| q2xhrpoly_0p35_nwell = xhrpoly_0p35_nwell NOT (xhrpoly_0p35_nwell ENCLOSE (xhrpoly_0p35_nwell NOT polycut) == 2) |
| |
| xuhrpoly_0p35_nwell = xuhrpoly_0p35 AND MosNwell |
| q1xuhrpoly_0p35_nwell = xuhrpoly_0p35_nwell AND polycut |
| q2xuhrpoly_0p35_nwell = xuhrpoly_0p35_nwell NOT (xuhrpoly_0p35_nwell ENCLOSE (xuhrpoly_0p35_nwell NOT polycut) == 2) |
| "r_805_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_0p35_nwell |
| } |
| q6xhrpoly_0p35_nwell = xhrpoly_0p35_nwell INSIDE EDGE poly |
| q7xhrpoly_0p35_nwell = q6xhrpoly_0p35_nwell NOT OUTSIDE EDGE q1xhrpoly_0p35_nwell |
| q5xhrpoly_0p35_nwell = q7xhrpoly_0p35_nwell NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_0p35_nwell |
| q8xhrpoly_0p35_nwell = EXPAND EDGE q5xhrpoly_0p35_nwell INSIDE BY 0.005 |
| q3xhrpoly_0p35_nwell = NOT TOUCH (INTERACT xhrpoly_0p35_nwell q8xhrpoly_0p35_nwell) q8xhrpoly_0p35_nwell |
| q4xhrpoly_0p35_nwell = q2xhrpoly_0p35_nwell OR q3xhrpoly_0p35_nwell |
| q9xhrpoly_0p35_nwell_a = q1xhrpoly_0p35_nwell NOT q4xhrpoly_0p35_nwell |
| |
| q9xhrpoly_0p35_nwell = q9xhrpoly_0p35_nwell_a OR q9xuhrpoly_base_nwell |
| |
| q6xuhrpoly_0p35_nwell = xuhrpoly_0p35_nwell INSIDE EDGE poly |
| q7xuhrpoly_0p35_nwell = q6xuhrpoly_0p35_nwell NOT OUTSIDE EDGE q1xuhrpoly_0p35_nwell |
| q5xuhrpoly_0p35_nwell = q7xuhrpoly_0p35_nwell NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_0p35_nwell |
| q8xuhrpoly_0p35_nwell = EXPAND EDGE q5xuhrpoly_0p35_nwell INSIDE BY 0.005 |
| q3xuhrpoly_0p35_nwell = NOT TOUCH (INTERACT xuhrpoly_0p35_nwell q8xuhrpoly_0p35_nwell) q8xuhrpoly_0p35_nwell |
| q4xuhrpoly_0p35_nwell = q2xuhrpoly_0p35_nwell OR q3xuhrpoly_0p35_nwell |
| q9xuhrpoly_0p35_nwell = q1xuhrpoly_0p35_nwell NOT q4xuhrpoly_0p35_nwell |
| |
| "r_806_resistorError" { |
| @ resistorError: bad polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_0p35_nwell |
| } |
| |
| //DEVICE xhrpoly_0p35 xhrpoly_0p35_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_0p35_nwell ) * L_scale2 |
| // l = a / 3.5e-01 |
| // w = 3.5e-01 |
| // ] |
| DEVICE xhrpoly_0p35 xhrpoly_0p35_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_0p35_nwell 0.35 "xhrpoly_0p35" |
| DEVICE xhrpoly xhrpoly_base_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN2 xhrpoly_base_nwell "xhrpoly" |
| |
| DEVICE xuhrpoly_0p35 xuhrpoly_0p35_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_0p35_nwell 0.35 "xuhrpoly_0p35" |
| DEVICE xuhrpoly xuhrpoly_base_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN2 xuhrpoly_base_nwell "xuhrpoly" |
| |
| |
| LVS DEVICE TYPE RESISTOR xhrpoly_0p35 |
| CMACRO TRACE_PARAM xhrpoly_0p35 m w l |
| LVS DEVICE TYPE RESISTOR xuhrpoly_0p35 |
| CMACRO TRACE_PARAM xuhrpoly_0p35 m w l |
| //TRACE PROPERTY R(xhrpoly_0p35) w w 1 |
| //TRACE PROPERTY R(xhrpoly_0p35) l l 1 |
| //TRACE PROPERTY R(xhrpoly_0p35) m m 0 |
| |
| xhrpoly_0p69_nwell = xhrpoly_0p69 AND MosNwell |
| q1xhrpoly_0p69_nwell = xhrpoly_0p69_nwell AND polycut |
| q2xhrpoly_0p69_nwell = xhrpoly_0p69_nwell NOT (xhrpoly_0p69_nwell ENCLOSE (xhrpoly_0p69_nwell NOT polycut) == 2) |
| |
| xuhrpoly_0p69_nwell = xuhrpoly_0p69 AND MosNwell |
| q1xuhrpoly_0p69_nwell = xuhrpoly_0p69_nwell AND polycut |
| q2xuhrpoly_0p69_nwell = xuhrpoly_0p69_nwell NOT (xuhrpoly_0p69_nwell ENCLOSE (xuhrpoly_0p69_nwell NOT polycut) == 2) |
| "r_807_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_0p69_nwell |
| } |
| |
| q6xhrpoly_0p69_nwell = xhrpoly_0p69_nwell INSIDE EDGE poly |
| q7xhrpoly_0p69_nwell = q6xhrpoly_0p69_nwell NOT OUTSIDE EDGE q1xhrpoly_0p69_nwell |
| q5xhrpoly_0p69_nwell = q7xhrpoly_0p69_nwell NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_0p69_nwell |
| q8xhrpoly_0p69_nwell = EXPAND EDGE q5xhrpoly_0p69_nwell INSIDE BY 0.005 |
| q3xhrpoly_0p69_nwell = (INTERACT xhrpoly_0p69_nwell q8xhrpoly_0p69_nwell) NOT TOUCH q8xhrpoly_0p69_nwell |
| q4xhrpoly_0p69_nwell = q2xhrpoly_0p69_nwell OR q3xhrpoly_0p69_nwell |
| q9xhrpoly_0p69_nwell = q1xhrpoly_0p69_nwell NOT q4xhrpoly_0p69_nwell |
| |
| q6xuhrpoly_0p69_nwell = xuhrpoly_0p69_nwell INSIDE EDGE poly |
| q7xuhrpoly_0p69_nwell = q6xuhrpoly_0p69_nwell NOT OUTSIDE EDGE q1xuhrpoly_0p69_nwell |
| q5xuhrpoly_0p69_nwell = q7xuhrpoly_0p69_nwell NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_0p69_nwell |
| q8xuhrpoly_0p69_nwell = EXPAND EDGE q5xuhrpoly_0p69_nwell INSIDE BY 0.005 |
| q3xuhrpoly_0p69_nwell = (INTERACT xuhrpoly_0p69_nwell q8xuhrpoly_0p69_nwell) NOT TOUCH q8xuhrpoly_0p69_nwell |
| q4xuhrpoly_0p69_nwell = q2xuhrpoly_0p69_nwell OR q3xuhrpoly_0p69_nwell |
| q9xuhrpoly_0p69_nwell = q1xuhrpoly_0p69_nwell NOT q4xuhrpoly_0p69_nwell |
| "r_808_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_0p69_nwell |
| } |
| //DEVICE R(xhrpoly_0p69) xhrpoly_0p69_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_0p69_nwell ) * L_scale2 |
| // l = a / 6.9e-01 |
| // w = 6.9e-01 |
| // ] |
| DEVICE xhrpoly_0p69 xhrpoly_0p69_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_0p69_nwell 0.69 "xhrpoly_0p69" |
| |
| DEVICE xuhrpoly_0p69 xuhrpoly_0p69_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_0p69_nwell 0.69 "xuhrpoly_0p69" |
| |
| //LVS DEVICE TYPE RESISTOR xhrpoly_0p69 |
| //CMACRO TRACE_PARAM xhrpoly_0p69 m w l |
| |
| //TRACE PROPERTY R(xhrpoly_0p69) w w 1 |
| //TRACE PROPERTY R(xhrpoly_0p69) l l 1 |
| //TRACE PROPERTY R(xhrpoly_0p69) m m 0 |
| |
| xhrpoly_1p41_nwell = xhrpoly_1p41 AND MosNwell |
| q1xhrpoly_1p41_nwell = xhrpoly_1p41_nwell AND polycut |
| q2xhrpoly_1p41_nwell = xhrpoly_1p41_nwell NOT (xhrpoly_1p41_nwell ENCLOSE (xhrpoly_1p41_nwell NOT polycut) == 2) |
| |
| xuhrpoly_1p41_nwell = xuhrpoly_1p41 AND MosNwell |
| q1xuhrpoly_1p41_nwell = xuhrpoly_1p41_nwell AND polycut |
| q2xuhrpoly_1p41_nwell = xuhrpoly_1p41_nwell NOT (xuhrpoly_1p41_nwell ENCLOSE (xuhrpoly_1p41_nwell NOT polycut) == 2) |
| "r_809_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_1p41_nwell |
| } |
| q6xhrpoly_1p41_nwell = xhrpoly_1p41_nwell INSIDE EDGE poly |
| q7xhrpoly_1p41_nwell = q6xhrpoly_1p41_nwell NOT OUTSIDE EDGE q1xhrpoly_1p41_nwell |
| q5xhrpoly_1p41_nwell = q7xhrpoly_1p41_nwell NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_1p41_nwell |
| q8xhrpoly_1p41_nwell = EXPAND EDGE q5xhrpoly_1p41_nwell INSIDE BY 0.005 |
| q3xhrpoly_1p41_nwell = (INTERACT xhrpoly_1p41_nwell q8xhrpoly_1p41_nwell) NOT TOUCH q8xhrpoly_1p41_nwell |
| q4xhrpoly_1p41_nwell = q2xhrpoly_1p41_nwell OR q3xhrpoly_1p41_nwell |
| q9xhrpoly_1p41_nwell = q1xhrpoly_1p41_nwell NOT q4xhrpoly_1p41_nwell |
| |
| q6xuhrpoly_1p41_nwell = xuhrpoly_1p41_nwell INSIDE EDGE poly |
| q7xuhrpoly_1p41_nwell = q6xuhrpoly_1p41_nwell NOT OUTSIDE EDGE q1xuhrpoly_1p41_nwell |
| q5xuhrpoly_1p41_nwell = q7xuhrpoly_1p41_nwell NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_1p41_nwell |
| q8xuhrpoly_1p41_nwell = EXPAND EDGE q5xuhrpoly_1p41_nwell INSIDE BY 0.005 |
| q3xuhrpoly_1p41_nwell = (INTERACT xuhrpoly_1p41_nwell q8xuhrpoly_1p41_nwell) NOT TOUCH q8xuhrpoly_1p41_nwell |
| q4xuhrpoly_1p41_nwell = q2xuhrpoly_1p41_nwell OR q3xuhrpoly_1p41_nwell |
| q9xuhrpoly_1p41_nwell = q1xuhrpoly_1p41_nwell NOT q4xuhrpoly_1p41_nwell |
| "r_810_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_1p41_nwell |
| } |
| |
| //DEVICE R(xhrpoly_1p41) xhrpoly_1p41_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET [ |
| DEVICE xhrpoly_1p41 xhrpoly_1p41_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_1p41_nwell 1.41 "xhrpoly_1p41" |
| |
| DEVICE xuhrpoly_1p41 xuhrpoly_1p41_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_1p41_nwell 1.41 "xuhrpoly_1p41" |
| /* |
| [ |
| PROPERTY w , l , m |
| m = 1 |
| a = area( xhrpoly_1p41_nwell ) * L_scale2 |
| l = a / 1.41 |
| w = 1.41 |
| ] |
| */ |
| |
| //TRACE PROPERTY R(xhrpoly_1p41) w w 1 |
| //TRACE PROPERTY R(xhrpoly_1p41) l l 1 |
| //TRACE PROPERTY R(xhrpoly_1p41) m m 0 |
| |
| xhrpoly_2p85_nwell = xhrpoly_2p85 AND MosNwell |
| q1xhrpoly_2p85_nwell = xhrpoly_2p85_nwell AND polycut |
| q2xhrpoly_2p85_nwell = xhrpoly_2p85_nwell NOT (xhrpoly_2p85_nwell ENCLOSE (xhrpoly_2p85_nwell NOT polycut) == 2) |
| |
| xuhrpoly_2p85_nwell = xuhrpoly_2p85 AND MosNwell |
| q1xuhrpoly_2p85_nwell = xuhrpoly_2p85_nwell AND polycut |
| q2xuhrpoly_2p85_nwell = xuhrpoly_2p85_nwell NOT (xuhrpoly_2p85_nwell ENCLOSE (xuhrpoly_2p85_nwell NOT polycut) == 2) |
| "r_811_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_2p85_nwell |
| } |
| q6xhrpoly_2p85_nwell = xhrpoly_2p85_nwell INSIDE EDGE poly |
| q7xhrpoly_2p85_nwell = q6xhrpoly_2p85_nwell NOT OUTSIDE EDGE q1xhrpoly_2p85_nwell |
| q5xhrpoly_2p85_nwell = q7xhrpoly_2p85_nwell NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_2p85_nwell |
| q8xhrpoly_2p85_nwell = EXPAND EDGE q5xhrpoly_2p85_nwell INSIDE BY 0.005 |
| q3xhrpoly_2p85_nwell = (INTERACT xhrpoly_2p85_nwell q8xhrpoly_2p85_nwell) NOT TOUCH q8xhrpoly_2p85_nwell |
| q4xhrpoly_2p85_nwell = q2xhrpoly_2p85_nwell OR q3xhrpoly_2p85_nwell |
| q9xhrpoly_2p85_nwell = q1xhrpoly_2p85_nwell NOT q4xhrpoly_2p85_nwell |
| |
| q6xuhrpoly_2p85_nwell = xuhrpoly_2p85_nwell INSIDE EDGE poly |
| q7xuhrpoly_2p85_nwell = q6xuhrpoly_2p85_nwell NOT OUTSIDE EDGE q1xuhrpoly_2p85_nwell |
| q5xuhrpoly_2p85_nwell = q7xuhrpoly_2p85_nwell NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_2p85_nwell |
| q8xuhrpoly_2p85_nwell = EXPAND EDGE q5xuhrpoly_2p85_nwell INSIDE BY 0.005 |
| q3xuhrpoly_2p85_nwell = (INTERACT xuhrpoly_2p85_nwell q8xuhrpoly_2p85_nwell) NOT TOUCH q8xuhrpoly_2p85_nwell |
| q4xuhrpoly_2p85_nwell = q2xuhrpoly_2p85_nwell OR q3xuhrpoly_2p85_nwell |
| q9xuhrpoly_2p85_nwell = q1xuhrpoly_2p85_nwell NOT q4xuhrpoly_2p85_nwell |
| "r_812_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_2p85_nwell |
| } |
| |
| DEVICE xhrpoly_2p85 xhrpoly_2p85_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_2p85_nwell 2.85 "xhrpoly_2p85" |
| |
| DEVICE xuhrpoly_2p85 xuhrpoly_2p85_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_2p85_nwell 2.85 "xuhrpoly_2p85" |
| //DEVICE R(xhrpoly_2p85) xhrpoly_2p85_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_2p85_nwell ) * L_scale2 |
| // l = a / 2.85 |
| // w = 2.85 |
| // ] |
| |
| //TRACE PROPERTY R(xhrpoly_2p85) w w 1 |
| //TRACE PROPERTY R(xhrpoly_2p85) l l 1 |
| //TRACE PROPERTY R(xhrpoly_2p85) m m 0 |
| |
| xhrpoly_5p73_nwell = xhrpoly_5p73 AND MosNwell |
| q1xhrpoly_5p73_nwell = xhrpoly_5p73_nwell AND polycut |
| q2xhrpoly_5p73_nwell = xhrpoly_5p73_nwell NOT (xhrpoly_5p73_nwell ENCLOSE (xhrpoly_5p73_nwell NOT polycut) == 2) |
| |
| xuhrpoly_5p73_nwell = xuhrpoly_5p73 AND MosNwell |
| q1xuhrpoly_5p73_nwell = xuhrpoly_5p73_nwell AND polycut |
| q2xuhrpoly_5p73_nwell = xuhrpoly_5p73_nwell NOT (xuhrpoly_5p73_nwell ENCLOSE (xuhrpoly_5p73_nwell NOT polycut) == 2) |
| "r_813_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_5p73_nwell |
| } |
| q6xhrpoly_5p73_nwell = xhrpoly_5p73_nwell INSIDE EDGE poly |
| q7xhrpoly_5p73_nwell = q6xhrpoly_5p73_nwell NOT OUTSIDE EDGE q1xhrpoly_5p73_nwell |
| q5xhrpoly_5p73_nwell = q7xhrpoly_5p73_nwell NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_5p73_nwell |
| q8xhrpoly_5p73_nwell = EXPAND EDGE q5xhrpoly_5p73_nwell INSIDE BY 0.005 |
| q3xhrpoly_5p73_nwell = (INTERACT xhrpoly_5p73_nwell q8xhrpoly_5p73_nwell) NOT TOUCH q8xhrpoly_5p73_nwell |
| q4xhrpoly_5p73_nwell = q2xhrpoly_5p73_nwell OR q3xhrpoly_5p73_nwell |
| q9xhrpoly_5p73_nwell = q1xhrpoly_5p73_nwell NOT q4xhrpoly_5p73_nwell |
| |
| q6xuhrpoly_5p73_nwell = xuhrpoly_5p73_nwell INSIDE EDGE poly |
| q7xuhrpoly_5p73_nwell = q6xuhrpoly_5p73_nwell NOT OUTSIDE EDGE q1xuhrpoly_5p73_nwell |
| q5xuhrpoly_5p73_nwell = q7xuhrpoly_5p73_nwell NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_5p73_nwell |
| q8xuhrpoly_5p73_nwell = EXPAND EDGE q5xuhrpoly_5p73_nwell INSIDE BY 0.005 |
| q3xuhrpoly_5p73_nwell = (INTERACT xuhrpoly_5p73_nwell q8xuhrpoly_5p73_nwell) NOT TOUCH q8xuhrpoly_5p73_nwell |
| q4xuhrpoly_5p73_nwell = q2xuhrpoly_5p73_nwell OR q3xuhrpoly_5p73_nwell |
| q9xuhrpoly_5p73_nwell = q1xuhrpoly_5p73_nwell NOT q4xuhrpoly_5p73_nwell |
| "r_814_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_5p73_nwell |
| } |
| |
| DEVICE xhrpoly_5p73 xhrpoly_5p73_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_5p73_nwell 5.73 "xhrpoly_5p73" |
| |
| DEVICE xuhrpoly_5p73 xuhrpoly_5p73_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_5p73_nwell 5.73 "xuhrpoly_5p73" |
| //DEVICE R(xhrpoly_5p73) xhrpoly_5p73_nwell POLY_cond_nrc(POS) POLY_cond_nrc(NEG) MosNwell(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_5p73_nwell ) * L_scale2 |
| // l = a / 5.73 |
| // w = 5.73 |
| // ] |
| |
| //TRACE PROPERTY R(xhrpoly_5p73) w w 1 |
| //TRACE PROPERTY R(xhrpoly_5p73) l l 1 |
| //TRACE PROPERTY R(xhrpoly_5p73) m m 0 |
| |
| xuhrpoly_0p35_sub = xuhrpoly_0p35 NOT MosNwell |
| xhrpoly_0p35_sub = xhrpoly_0p35 NOT MosNwell |
| q1xhrpoly_0p35_sub = xhrpoly_0p35_sub AND polycut |
| q1xuhrpoly_0p35_sub = xuhrpoly_0p35_sub AND polycut |
| q2xhrpoly_0p35_sub = xhrpoly_0p35_sub NOT (xhrpoly_0p35_sub ENCLOSE (xhrpoly_0p35_sub NOT polycut) == 2) |
| q2xuhrpoly_0p35_sub = xuhrpoly_0p35_sub NOT (xuhrpoly_0p35_sub ENCLOSE (xuhrpoly_0p35_sub NOT polycut) == 2) |
| "r_815_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_0p35_sub |
| } |
| q6xhrpoly_0p35_sub = xhrpoly_0p35_sub INSIDE EDGE poly |
| q7xhrpoly_0p35_sub = q6xhrpoly_0p35_sub NOT OUTSIDE EDGE q1xhrpoly_0p35_sub |
| q5xhrpoly_0p35_sub = q7xhrpoly_0p35_sub NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_0p35_sub |
| q8xhrpoly_0p35_sub = EXPAND EDGE q5xhrpoly_0p35_sub INSIDE BY 0.005 |
| q3xhrpoly_0p35_sub = (INTERACT xhrpoly_0p35_sub q8xhrpoly_0p35_sub) NOT TOUCH q8xhrpoly_0p35_sub |
| q4xhrpoly_0p35_sub = q2xhrpoly_0p35_sub OR q3xhrpoly_0p35_sub |
| q9xhrpoly_0p35_sub_a = q1xhrpoly_0p35_sub NOT q4xhrpoly_0p35_sub |
| "r_816_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_0p35_sub |
| } |
| q6xuhrpoly_0p35_sub = xuhrpoly_0p35_sub INSIDE EDGE poly |
| q7xuhrpoly_0p35_sub = q6xuhrpoly_0p35_sub NOT OUTSIDE EDGE q1xuhrpoly_0p35_sub |
| q5xuhrpoly_0p35_sub = q7xuhrpoly_0p35_sub NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_0p35_sub |
| q8xuhrpoly_0p35_sub = EXPAND EDGE q5xuhrpoly_0p35_sub INSIDE BY 0.005 |
| q3xuhrpoly_0p35_sub = (INTERACT xuhrpoly_0p35_sub q8xuhrpoly_0p35_sub) NOT TOUCH q8xuhrpoly_0p35_sub |
| q4xuhrpoly_0p35_sub = q2xuhrpoly_0p35_sub OR q3xuhrpoly_0p35_sub |
| q9xuhrpoly_0p35_sub = q1xuhrpoly_0p35_sub NOT q4xuhrpoly_0p35_sub |
| |
| q9xhrpoly_0p35_sub = q9xhrpoly_0p35_sub_a OR (q9xuhrpoly_0p35_sub OR q9xuhrpoly_base_sub) |
| |
| DEVICE xhrpoly_0p35 xhrpoly_0p35_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_0p35_sub 0.35 "xhrpoly_0p35" |
| |
| DEVICE xuhrpoly_0p35 xuhrpoly_0p35_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_0p35_sub 0.35 "xuhrpoly_0p35" |
| //DEVICE R(xhrpoly_0p35) xhrpoly_0p35_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_0p35_sub ) * L_scale |
| // l = a / 3.5e-01 |
| // w = 3.5e-01 |
| // ] |
| |
| xhrpoly_0p69_sub = xhrpoly_0p69 NOT MosNwell |
| q1xhrpoly_0p69_sub = xhrpoly_0p69_sub AND polycut |
| q2xhrpoly_0p69_sub = xhrpoly_0p69_sub NOT (xhrpoly_0p69_sub ENCLOSE (xhrpoly_0p69_sub NOT polycut) == 2) |
| |
| xuhrpoly_0p69_sub = xuhrpoly_0p69 NOT MosNwell |
| q1xuhrpoly_0p69_sub = xuhrpoly_0p69_sub AND polycut |
| q2xuhrpoly_0p69_sub = xuhrpoly_0p69_sub NOT (xuhrpoly_0p69_sub ENCLOSE (xuhrpoly_0p69_sub NOT polycut) == 2) |
| "r_817_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_0p69_sub |
| } |
| q6xhrpoly_0p69_sub = xhrpoly_0p69_sub INSIDE EDGE poly |
| q7xhrpoly_0p69_sub = q6xhrpoly_0p69_sub NOT OUTSIDE EDGE q1xhrpoly_0p69_sub |
| q5xhrpoly_0p69_sub = q7xhrpoly_0p69_sub NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_0p69_sub |
| q8xhrpoly_0p69_sub = EXPAND EDGE q5xhrpoly_0p69_sub INSIDE BY 0.005 |
| q3xhrpoly_0p69_sub = (INTERACT xhrpoly_0p69_sub q8xhrpoly_0p69_sub) NOT TOUCH q8xhrpoly_0p69_sub |
| q4xhrpoly_0p69_sub = q2xhrpoly_0p69_sub OR q3xhrpoly_0p69_sub |
| q9xhrpoly_0p69_sub = q1xhrpoly_0p69_sub NOT q4xhrpoly_0p69_sub |
| |
| q6xuhrpoly_0p69_sub = xuhrpoly_0p69_sub INSIDE EDGE poly |
| q7xuhrpoly_0p69_sub = q6xuhrpoly_0p69_sub NOT OUTSIDE EDGE q1xuhrpoly_0p69_sub |
| q5xuhrpoly_0p69_sub = q7xuhrpoly_0p69_sub NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_0p69_sub |
| q8xuhrpoly_0p69_sub = EXPAND EDGE q5xuhrpoly_0p69_sub INSIDE BY 0.005 |
| q3xuhrpoly_0p69_sub = (INTERACT xuhrpoly_0p69_sub q8xuhrpoly_0p69_sub) NOT TOUCH q8xuhrpoly_0p69_sub |
| q4xuhrpoly_0p69_sub = q2xuhrpoly_0p69_sub OR q3xuhrpoly_0p69_sub |
| q9xuhrpoly_0p69_sub = q1xuhrpoly_0p69_sub NOT q4xuhrpoly_0p69_sub |
| "r_818_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_0p69_sub |
| } |
| |
| DEVICE xhrpoly_0p69 xhrpoly_0p69_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_0p69_sub 0.69 "xhrpoly_0p69" |
| |
| DEVICE xuhrpoly_0p69 xuhrpoly_0p69_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_0p69_sub 0.69 "xuhrpoly_0p69" |
| //DEVICE R(xhrpoly_0p69) xhrpoly_0p69_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_0p69_sub ) * L_scale2 |
| // l = a / 6.9e-01 |
| // w = 6.9e-01 |
| // ] |
| LVS DEVICE TYPE RESISTOR xhrpoly_0p69 |
| LVS DEVICE TYPE RESISTOR xuhrpoly_0p69 |
| CMACRO TRACE_PARAM xhrpoly_0p69 m w l |
| CMACRO TRACE_PARAM xuhrpoly_0p69 m w l |
| |
| xhrpoly_1p41_sub = xhrpoly_1p41 NOT MosNwell |
| q1xhrpoly_1p41_sub = xhrpoly_1p41_sub AND polycut |
| q2xhrpoly_1p41_sub = xhrpoly_1p41_sub NOT (xhrpoly_1p41_sub ENCLOSE (xhrpoly_1p41_sub NOT polycut) == 2) |
| |
| xuhrpoly_1p41_sub = xuhrpoly_1p41 NOT MosNwell |
| q1xuhrpoly_1p41_sub = xuhrpoly_1p41_sub AND polycut |
| q2xuhrpoly_1p41_sub = xuhrpoly_1p41_sub NOT (xuhrpoly_1p41_sub ENCLOSE (xuhrpoly_1p41_sub NOT polycut) == 2) |
| "r_819_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_1p41_sub |
| } |
| q6xhrpoly_1p41_sub = xhrpoly_1p41_sub INSIDE EDGE poly |
| q7xhrpoly_1p41_sub = q6xhrpoly_1p41_sub NOT OUTSIDE EDGE q1xhrpoly_1p41_sub |
| q5xhrpoly_1p41_sub = q7xhrpoly_1p41_sub NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_1p41_sub |
| q8xhrpoly_1p41_sub = EXPAND EDGE q5xhrpoly_1p41_sub INSIDE BY 0.005 |
| q3xhrpoly_1p41_sub = (INTERACT xhrpoly_1p41_sub q8xhrpoly_1p41_sub) NOT TOUCH q8xhrpoly_1p41_sub |
| q4xhrpoly_1p41_sub = q2xhrpoly_1p41_sub OR q3xhrpoly_1p41_sub |
| q9xhrpoly_1p41_sub = q1xhrpoly_1p41_sub NOT q4xhrpoly_1p41_sub |
| |
| q6xuhrpoly_1p41_sub = xuhrpoly_1p41_sub INSIDE EDGE poly |
| q7xuhrpoly_1p41_sub = q6xuhrpoly_1p41_sub NOT OUTSIDE EDGE q1xuhrpoly_1p41_sub |
| q5xuhrpoly_1p41_sub = q7xuhrpoly_1p41_sub NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_1p41_sub |
| q8xuhrpoly_1p41_sub = EXPAND EDGE q5xuhrpoly_1p41_sub INSIDE BY 0.005 |
| q3xuhrpoly_1p41_sub = (INTERACT xuhrpoly_1p41_sub q8xuhrpoly_1p41_sub) NOT TOUCH q8xuhrpoly_1p41_sub |
| q4xuhrpoly_1p41_sub = q2xuhrpoly_1p41_sub OR q3xuhrpoly_1p41_sub |
| q9xuhrpoly_1p41_sub = q1xuhrpoly_1p41_sub NOT q4xuhrpoly_1p41_sub |
| "r_820_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_1p41_sub |
| } |
| |
| DEVICE xhrpoly_1p41 xhrpoly_1p41_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_1p41_sub 1.41 "xhrpoly_1p41" |
| |
| DEVICE xuhrpoly_1p41 xuhrpoly_1p41_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_1p41_sub 1.41 "xuhrpoly_1p41" |
| //DEVICE R(xhrpoly_1p41) xhrpoly_1p41_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_1p41_sub ) * L_scale2 |
| // l = a / 1.41 |
| // w = 1.41 |
| // ] |
| |
| LVS DEVICE TYPE RESISTOR xhrpoly_1p41 |
| CMACRO TRACE_PARAM xhrpoly_1p41 m w l |
| |
| LVS DEVICE TYPE RESISTOR xuhrpoly_1p41 |
| CMACRO TRACE_PARAM xuhrpoly_1p41 m w l |
| |
| DMACRO XRDN rec_layer width x_model { |
| [ |
| PROPERTY w , l , m , model , mult |
| m = 1 |
| mult = 1 |
| model = x_model |
| a = area( rec_layer ) * L_square |
| l = a / width |
| w = width |
| ] |
| } |
| DMACRO XRDN2 rec_layer x_model { |
| [ |
| PROPERTY w , l , m , model , mult, segments |
| m = 1 |
| mult = 1 |
| model = x_model |
| dev_perim = perimeter( rec_layer ) * 0.5 * L_scale |
| width = perimeter_inside(rec_layer , poly ) * 0.5 * L_scale |
| a = area( rec_layer ) * L_square |
| segments = 1 + bends( rec_layer ) / 2 |
| //l = a / width |
| l = dev_perim - (width * (1 + (segments * 0.5))) |
| w = width |
| ] |
| } |
| DMACRO XRDN3 rec_layer x_model { |
| [ |
| PROPERTY w , l , m , model , mult |
| m = 1 |
| mult = 1 |
| model = x_model |
| width = perimeter_inside(rec_layer , ) * 0.5 * L_scale |
| a = area( rec_layer ) * L_square |
| l = a / width |
| w = width |
| ] |
| } |
| |
| DMACRO TRACE_PARAM element M P1 P2 { |
| TRACE PROPERTY element [ |
| PROPERTY M , P1 , P2 |
| tolerance = 1 |
| |
| lay_m = layout_numeric_value(m) |
| sch_m = source_numeric_value(m) |
| |
| lay_P1 = layout_numeric_value(P1) |
| sch_P1 = source_numeric_value(P1) |
| diff_P1 = 100 * ABS( lay_P1 - sch_P1 ) / sch_P1 |
| |
| lay_P2 = layout_numeric_value(P2) |
| sch_P2 = source_numeric_value(P2) |
| diff_P2 = 100 * ABS( lay_P2 - sch_P2 ) / sch_P2 |
| |
| if( lay_m != sch_m ) { |
| diff_m = ABS(lay_m - sch_m) |
| report_numeric_value( m, diff_m ) |
| } |
| if( diff_P1 > tolerance ) { |
| report_numeric_discrepancy( P1, diff_P1 ) |
| } |
| if( diff_P2 > tolerance ) { |
| report_numeric_discrepancy( P2, diff_P2 ) |
| } |
| |
| ] |
| } |
| |
| DMACRO TRACE_PARAM_bent element M P1 P2 segments { |
| TRACE PROPERTY element [ |
| PROPERTY M , P1 , P2, segments |
| |
| lay_b = layout_numeric_value(segments) |
| sch_b = source_numeric_value(segments) |
| if( lay_b > 1 ) { |
| tolerance = 5 |
| } else { |
| tolerance = 1 |
| } |
| diff_b = 100 * ABS( lay_b - sch_b ) / sch_b |
| |
| lay_m = layout_numeric_value(m) |
| sch_m = source_numeric_value(m) |
| |
| lay_P1 = layout_numeric_value(P1) |
| sch_P1 = source_numeric_value(P1) |
| diff_P1 = 100 * ABS( lay_P1 - sch_P1 ) / sch_P1 |
| |
| lay_P2 = layout_numeric_value(P2) |
| sch_P2 = source_numeric_value(P2) |
| diff_P2 = 100 * ABS( lay_P2 - sch_P2 ) / sch_P2 |
| |
| if( lay_m != sch_m ) { |
| diff_m = ABS(lay_m - sch_m) |
| report_numeric_value( m, diff_m ) |
| } |
| if( diff_P1 > tolerance ) { |
| report_numeric_discrepancy( P1, diff_P1 ) |
| } |
| if( diff_P2 > tolerance ) { |
| report_numeric_discrepancy( P2, diff_P2 ) |
| } |
| if( diff_b > tolerance ) { |
| report_numeric_discrepancy( segments, diff_b ) |
| } |
| |
| ] |
| } |
| |
| |
| xhrpoly_2p85_sub = xhrpoly_2p85 NOT MosNwell |
| q1xhrpoly_2p85_sub = xhrpoly_2p85_sub AND polycut |
| q2xhrpoly_2p85_sub = xhrpoly_2p85_sub NOT (xhrpoly_2p85_sub ENCLOSE (xhrpoly_2p85_sub NOT polycut) == 2) |
| |
| xuhrpoly_2p85_sub = xuhrpoly_2p85 NOT MosNwell |
| q1xuhrpoly_2p85_sub = xuhrpoly_2p85_sub AND polycut |
| q2xuhrpoly_2p85_sub = xuhrpoly_2p85_sub NOT (xuhrpoly_2p85_sub ENCLOSE (xuhrpoly_2p85_sub NOT polycut) == 2) |
| "r_821_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_2p85_sub |
| } |
| q6xhrpoly_2p85_sub = xhrpoly_2p85_sub INSIDE EDGE poly |
| q7xhrpoly_2p85_sub = q6xhrpoly_2p85_sub NOT OUTSIDE EDGE q1xhrpoly_2p85_sub |
| q5xhrpoly_2p85_sub = q7xhrpoly_2p85_sub NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_2p85_sub |
| q8xhrpoly_2p85_sub = EXPAND EDGE q5xhrpoly_2p85_sub INSIDE BY 0.005 |
| q3xhrpoly_2p85_sub = (INTERACT xhrpoly_2p85_sub q8xhrpoly_2p85_sub) NOT TOUCH q8xhrpoly_2p85_sub |
| q4xhrpoly_2p85_sub = q2xhrpoly_2p85_sub OR q3xhrpoly_2p85_sub |
| q9xhrpoly_2p85_sub = q1xhrpoly_2p85_sub NOT q4xhrpoly_2p85_sub |
| |
| q6xuhrpoly_2p85_sub = xuhrpoly_2p85_sub INSIDE EDGE poly |
| q7xuhrpoly_2p85_sub = q6xuhrpoly_2p85_sub NOT OUTSIDE EDGE q1xuhrpoly_2p85_sub |
| q5xuhrpoly_2p85_sub = q7xuhrpoly_2p85_sub NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_2p85_sub |
| q8xuhrpoly_2p85_sub = EXPAND EDGE q5xuhrpoly_2p85_sub INSIDE BY 0.005 |
| q3xuhrpoly_2p85_sub = (INTERACT xuhrpoly_2p85_sub q8xuhrpoly_2p85_sub) NOT TOUCH q8xuhrpoly_2p85_sub |
| q4xuhrpoly_2p85_sub = q2xuhrpoly_2p85_sub OR q3xuhrpoly_2p85_sub |
| q9xuhrpoly_2p85_sub = q1xuhrpoly_2p85_sub NOT q4xuhrpoly_2p85_sub |
| "r_822_resistorError" { |
| @ resistorError: badd polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_2p85_sub |
| } |
| |
| DEVICE xhrpoly_2p85 xhrpoly_2p85_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_2p85_sub 2.85 "xhrpoly_2p85" |
| |
| DEVICE xuhrpoly_2p85 xuhrpoly_2p85_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_2p85_sub 2.85 "xuhrpoly_2p85" |
| //DEVICE R(xhrpoly_2p85) xhrpoly_2p85_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_2p85_sub ) * L_scale2 |
| // l = a / 2.85 |
| // w = 2.85 |
| // ] |
| |
| LVS DEVICE TYPE RESISTOR xhrpoly_2p85 |
| CMACRO TRACE_PARAM xhrpoly_2p85 m w l |
| |
| LVS DEVICE TYPE RESISTOR xuhrpoly_2p85 |
| CMACRO TRACE_PARAM xuhrpoly_2p85 m w l |
| |
| xhrpoly_5p73_sub = xhrpoly_5p73 NOT MosNwell |
| q1xhrpoly_5p73_sub = xhrpoly_5p73_sub AND polycut |
| q2xhrpoly_5p73_sub = xhrpoly_5p73_sub NOT (xhrpoly_5p73_sub ENCLOSE (xhrpoly_5p73_sub NOT polycut) == 2) |
| |
| xuhrpoly_5p73_sub = xuhrpoly_5p73 NOT MosNwell |
| q1xuhrpoly_5p73_sub = xuhrpoly_5p73_sub AND polycut |
| q2xuhrpoly_5p73_sub = xuhrpoly_5p73_sub NOT (xuhrpoly_5p73_sub ENCLOSE (xuhrpoly_5p73_sub NOT polycut) == 2) |
| "r_823_resistorError" { |
| @ resistorError: polycut does not divide poly in two |
| COPY q2xhrpoly_5p73_sub |
| } |
| q6xhrpoly_5p73_sub = xhrpoly_5p73_sub INSIDE EDGE poly |
| q7xhrpoly_5p73_sub = q6xhrpoly_5p73_sub NOT OUTSIDE EDGE q1xhrpoly_5p73_sub |
| q5xhrpoly_5p73_sub = q7xhrpoly_5p73_sub NOT COINCIDENT OUTSIDE EDGE q1xhrpoly_5p73_sub |
| q8xhrpoly_5p73_sub = EXPAND EDGE q5xhrpoly_5p73_sub INSIDE BY 0.005 |
| q3xhrpoly_5p73_sub = (INTERACT xhrpoly_5p73_sub q8xhrpoly_5p73_sub) NOT TOUCH q8xhrpoly_5p73_sub |
| q4xhrpoly_5p73_sub = q2xhrpoly_5p73_sub OR q3xhrpoly_5p73_sub |
| q9xhrpoly_5p73_sub = q1xhrpoly_5p73_sub NOT q4xhrpoly_5p73_sub |
| |
| q6xuhrpoly_5p73_sub = xuhrpoly_5p73_sub INSIDE EDGE poly |
| q7xuhrpoly_5p73_sub = q6xuhrpoly_5p73_sub NOT OUTSIDE EDGE q1xuhrpoly_5p73_sub |
| q5xuhrpoly_5p73_sub = q7xuhrpoly_5p73_sub NOT COINCIDENT OUTSIDE EDGE q1xuhrpoly_5p73_sub |
| q8xuhrpoly_5p73_sub = EXPAND EDGE q5xuhrpoly_5p73_sub INSIDE BY 0.005 |
| q3xuhrpoly_5p73_sub = (INTERACT xuhrpoly_5p73_sub q8xuhrpoly_5p73_sub) NOT TOUCH q8xuhrpoly_5p73_sub |
| q4xuhrpoly_5p73_sub = q2xuhrpoly_5p73_sub OR q3xuhrpoly_5p73_sub |
| q9xuhrpoly_5p73_sub = q1xuhrpoly_5p73_sub NOT q4xuhrpoly_5p73_sub |
| "r_824_resistorError" { |
| @ resistorError: bad polycut use/orientation, must not touch the terminal |
| COPY q3xhrpoly_5p73_sub |
| } |
| |
| DEVICE xhrpoly_5p73 xhrpoly_5p73_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xhrpoly_5p73_sub 5.73 "xhrpoly_5p73" |
| |
| DEVICE xhrpoly xhrpoly_base_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN2 xhrpoly_base_sub "xhrpoly" |
| |
| DEVICE xuhrpoly_5p73 xuhrpoly_5p73_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN xuhrpoly_5p73_sub 5.73 "xuhrpoly_5p73" |
| //DEVICE xuhrpoly_5p73 xuhrpoly_5p73_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| //CMACRO XRDN2 xuhrpoly_5p73_sub "xuhrpoly_5p73" |
| |
| DEVICE xuhrpoly xuhrpoly_base_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET |
| CMACRO XRDN2 xuhrpoly_base_sub "xuhrpoly" |
| //DEVICE R(xhrp1ly_5p73) xhrpoly_5p73_sub POLY_cond_nrc(POS) POLY_cond_nrc(NEG) Substrate(SUB) <poly> ("POS" "NEG") BY NET [ |
| // PROPERTY w , l , m |
| // m = 1 |
| // a = area( xhrpoly_5p73_sub ) * L_scale2 |
| // l = a / 5.73 |
| // w = 5.73 |
| // ] |
| |
| LVS DEVICE TYPE RESISTOR xhrpoly_5p73 |
| CMACRO TRACE_PARAM xhrpoly_5p73 m w l |
| |
| LVS DEVICE TYPE RESISTOR xuhrpoly_5p73 |
| CMACRO TRACE_PARAM xuhrpoly_5p73 m w l |
| |
| //LVS DEVICE TYPE RESISTOR xhrpoly |
| //CMACRO TRACE_PARAM xhrpoly m w l |
| LVS DEVICE TYPE RESISTOR xhrpoly |
| CMACRO TRACE_PARAM_bent xhrpoly m w l segments |
| LVS DEVICE TYPE RESISTOR xuhrpoly |
| CMACRO TRACE_PARAM_bent xuhrpoly m w l segments |
| |
| xhrpoly_x_1_device_a = (SIZE (xhrpoly_0p35 OR xuhrpoly_0p35) BY 0.5) OR ((SIZE (xhrpoly_0p69 OR xuhrpoly_0p69) BY 0.5) OR (SIZE (xhrpoly_1p41 OR (xuhrpoly_1p41 OR xuhrpoly_base)) BY 0.5)) |
| xhrpoly_x_1_device = (SIZE (xuhrpoly_base OR xhrpoly_base) BY 0.5) OR xhrpoly_x_1_device_a |
| //xhrpoly_x_2_device = COPY xhrpoly_x_1_device |
| xhrpoly_x_2_device = (SIZE (xhrpoly_2p85 OR xuhrpoly_2p85) BY 1.18) OR (SIZE (xhrpoly_5p73 OR xuhrpoly_5p73) BY 1.18) |
| pwellresistor = pwres AND dnwell |
| pwresBiasTerm = INTERACT (SIZE pwres BY 0.005) ((SIZE pwres BY 0.005) AND (nwell WITH EDGE (nwell COINCIDENT OUTSIDE EDGE pwres))) |
| mrpw = pwellresistor AND pwres |
| q1mrpw = mrpw AND pwcut |
| q2mrpw = mrpw NOT (mrpw ENCLOSE (mrpw NOT pwcut) == 2) |
| "r_825_resistorError" { |
| @ resistorError: pwcut does not divide pwellresistor in two |
| COPY q2mrpw |
| } |
| q6mrpw = mrpw INSIDE EDGE pwellresistor |
| q7mrpw = q6mrpw NOT OUTSIDE EDGE q1mrpw |
| q5mrpw = q7mrpw NOT COINCIDENT OUTSIDE EDGE q1mrpw |
| q8mrpw = EXPAND EDGE q5mrpw INSIDE BY 0.005 |
| q3mrpw = (INTERACT mrpw q8mrpw) NOT TOUCH q8mrpw |
| q4mrpw = q2mrpw OR q3mrpw |
| q9mrpw = q1mrpw NOT q4mrpw |
| "r_826_resistorError" { |
| @ resistorError: badd pwcut use/orientation, must not touch the terminal |
| COPY q3mrpw |
| } |
| |
| //DEVICE R(xpwres) mrpw SubstrateIso(POS) SubstrateIso(NEG) pwresBiasTerm_cond(SUB) <pwellresistor> ("POS" "NEG") BY NET [ |
| DEVICE xpwres mrpw SubstrateIso(POS) SubstrateIso(NEG) pwresBiasTerm_cond(SUB) <pwellresistor> ("POS" "NEG") BY NET [ |
| PROPERTY w , l , m |
| m = 1 |
| a = area( mrpw ) * L_scale |
| l = a / 2.65 *L_scale |
| w = 2.65 |
| ] |
| |
| TRACE PROPERTY xpwres w w 1 |
| TRACE PROPERTY xpwres l l 1 |
| TRACE PROPERTY xpwres m m 0 |
| |
| // ;ss |
| |
| "r_827_Illegal mrdn device mrdn_lv must not overlap ncm" { |
| @ Illegal mrdn device: mrdn_lv must not overlap ncm |
| mrdn_lv AND ncm |
| } |
| "r_828_Illegal mrdn device mrdn_lv must not overlap nwell" { |
| @ Illegal mrdn device: mrdn_lv must not overlap nwell |
| mrdn_lv AND nwell |
| } |
| "r_829_Illegal mrdn device mrdn_lv must not overlap tap" { |
| @ Illegal mrdn device: mrdn_lv must not overlap tap |
| mrdn_lv AND tap |
| } |
| "r_830_Illegal mrdn device mrdn_lv must not overlap poly" { |
| @ Illegal mrdn device: mrdn_lv must not overlap poly |
| mrdn_lv AND poly |
| } |
| "r_831_Illegal mrdn device mrdn_lv must not overlap polyres" { |
| @ Illegal mrdn device: mrdn_lv must not overlap polyres |
| mrdn_lv AND polyres |
| } |
| "r_832_Illegal mrdn device mrdn_lv must not overlap polycut" { |
| @ Illegal mrdn device: mrdn_lv must not overlap polycut |
| mrdn_lv AND polycut |
| } |
| "r_833_Illegal mrdn device mrdn_lv must not overlap li1cut" { |
| @ Illegal mrdn device: mrdn_lv must not overlap li1cut |
| mrdn_lv AND li1cut |
| } |
| "r_834_Illegal mrdn device mrdn_lv must not overlap fuse" { |
| @ Illegal mrdn device: mrdn_lv must not overlap fuse |
| mrdn_lv AND fuse |
| } |
| "r_835_Illegal mrdn device mrdn_lv must not overlap psdm" { |
| @ Illegal mrdn device: mrdn_lv must not overlap psdm |
| mrdn_lv AND psdm |
| } |
| "r_836_Illegal mrdn device mrdn_lv must not overlap capacitor" { |
| @ Illegal mrdn device: mrdn_lv must not overlap capacitor |
| mrdn_lv AND capacitor |
| } |
| "r_837_Illegal mrdn device mrdn_lv must not overlap LVID" { |
| @ Illegal mrdn device: mrdn_lv must not overlap LVID |
| mrdn_lv AND LVID |
| } |
| "r_838_Illegal mrdn device mrdn_lv must not overlap ENID" { |
| @ Illegal mrdn device: mrdn_lv must not overlap ENID |
| mrdn_lv AND ENID |
| } |
| "r_839_Illegal mrdn device mrdn_lv must not overlap hvtp" { |
| @ Illegal mrdn device: mrdn_lv must not overlap hvtp |
| mrdn_lv AND hvtp |
| } |
| "r_840_Illegal mrdn device mrdn_lv must not overlap lvtn" { |
| @ Illegal mrdn device: mrdn_lv must not overlap lvtn |
| mrdn_lv AND lvtn |
| } |
| "r_841_Illegal mrdn device mrdn_lv must not overlap hvi" { |
| @ Illegal mrdn device: mrdn_lv must not overlap hvi |
| mrdn_lv AND hvi |
| } |
| "r_842_Illegal mrdn device mrdn_lv must not overlap pnp" { |
| @ Illegal mrdn device: mrdn_lv must not overlap pnp |
| mrdn_lv AND pnp |
| } |
| "r_843_Illegal mrdn device mrdn_lv must not overlap DiodeID" { |
| @ Illegal mrdn device: mrdn_lv must not overlap DiodeID |
| mrdn_lv AND DiodeID |
| } |
| "r_844_Illegal mrdn device mrdn_lv must not overlap COREID" { |
| @ Illegal mrdn device: mrdn_lv must not overlap COREID |
| mrdn_lv AND COREID |
| } |
| "r_845_Illegal mrdp device mrdp_lv must not overlap tap" { |
| @ Illegal mrdp device: mrdp_lv must not overlap tap |
| mrdp_lv AND tap |
| } |
| "r_846_Illegal mrdp device mrdp_lv must not overlap poly" { |
| @ Illegal mrdp device: mrdp_lv must not overlap poly |
| mrdp_lv AND poly |
| } |
| "r_847_Illegal mrdp device mrdp_lv must not overlap polyres" { |
| @ Illegal mrdp device: mrdp_lv must not overlap polyres |
| mrdp_lv AND polyres |
| } |
| "r_848_Illegal mrdp device mrdp_lv must not overlap polycut" { |
| @ Illegal mrdp device: mrdp_lv must not overlap polycut |
| mrdp_lv AND polycut |
| } |
| "r_849_Illegal mrdp device mrdp_lv must not overlap li1cut" { |
| @ Illegal mrdp device: mrdp_lv must not overlap li1cut |
| mrdp_lv AND li1cut |
| } |
| "r_850_Illegal mrdp device mrdp_lv must not overlap fuse" { |
| @ Illegal mrdp device: mrdp_lv must not overlap fuse |
| mrdp_lv AND fuse |
| } |
| "r_851_Illegal mrdp device mrdp_lv must not overlap nsdm" { |
| @ Illegal mrdp device: mrdp_lv must not overlap nsdm |
| mrdp_lv AND nsdm |
| } |
| "r_852_Illegal mrdp device mrdp_lv must not overlap capacitor" { |
| @ Illegal mrdp device: mrdp_lv must not overlap capacitor |
| mrdp_lv AND capacitor |
| } |
| "r_853_Illegal mrdp device mrdp_lv must not overlap LVID" { |
| @ Illegal mrdp device: mrdp_lv must not overlap LVID |
| mrdp_lv AND LVID |
| } |
| "r_854_Illegal mrdp device mrdp_lv must not overlap ENID" { |
| @ Illegal mrdp device: mrdp_lv must not overlap ENID |
| mrdp_lv AND ENID |
| } |
| "r_855_Illegal mrdp device mrdp_lv must not overlap hvtp" { |
| @ Illegal mrdp device: mrdp_lv must not overlap hvtp |
| mrdp_lv AND hvtp |
| } |
| "r_856_Illegal mrdp device mrdp_lv must not overlap lvtn" { |
| @ Illegal mrdp device: mrdp_lv must not overlap lvtn |
| mrdp_lv AND lvtn |
| } |
| "r_857_Illegal mrdp device mrdp_lv must not overlap hvi" { |
| @ Illegal mrdp device: mrdp_lv must not overlap hvi |
| mrdp_lv AND hvi |
| } |
| "r_858_Illegal mrdp device mrdp_lv must not overlap pnp" { |
| @ Illegal mrdp device: mrdp_lv must not overlap pnp |
| mrdp_lv AND pnp |
| } |
| "r_859_Illegal mrdp device mrdp_lv must not overlap DiodeID" { |
| @ Illegal mrdp device: mrdp_lv must not overlap DiodeID |
| mrdp_lv AND DiodeID |
| } |
| "r_860_Illegal mrdp device mrdp_lv must not overlap COREID" { |
| @ Illegal mrdp device: mrdp_lv must not overlap COREID |
| mrdp_lv AND COREID |
| } |
| "r_861_Illegal mrdp device mrdp_lv must not overlap PHdiodeID" { |
| @ Illegal mrdp device: mrdp_lv must not overlap PHdiodeID |
| mrdp_lv AND PHdiodeID |
| } |
| "r_862_Illegal HV mrdn device mrdn_hv must not overlap ncm" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap ncm |
| mrdn_hv AND ncm |
| } |
| "r_863_Illegal HV mrdn device mrdn_hv must not overlap nwell" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap nwell |
| mrdn_hv AND nwell |
| } |
| "r_864_Illegal HV mrdn device mrdn_hv must not overlap tap" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap tap |
| mrdn_hv AND tap |
| } |
| "r_865_Illegal HV mrdn device mrdn_hv must not overlap poly" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap poly |
| mrdn_hv AND poly |
| } |
| "r_866_Illegal HV mrdn device mrdn_hv must not overlap polyres" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap polyres |
| mrdn_hv AND polyres |
| } |
| "r_867_Illegal HV mrdn device mrdn_hv must not overlap polycut" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap polycut |
| mrdn_hv AND polycut |
| } |
| "r_868_Illegal HV mrdn device mrdn_hv must not overlap li1cut" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap li1cut |
| mrdn_hv AND li1cut |
| } |
| "r_869_Illegal HV mrdn device mrdn_hv must not overlap fuse" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap fuse |
| mrdn_hv AND fuse |
| } |
| "r_870_Illegal HV mrdn device mrdn_hv must not overlap psdm" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap psdm |
| mrdn_hv AND psdm |
| } |
| "r_871_Illegal HV mrdn device mrdn_hv must not overlap capacitor" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap capacitor |
| mrdn_hv AND capacitor |
| } |
| "r_872_Illegal HV mrdn device mrdn_hv must not overlap LVID" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap LVID |
| mrdn_hv AND LVID |
| } |
| "r_873_Illegal HV mrdn device mrdn_hv must not overlap ENID" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap ENID |
| mrdn_hv AND ENID |
| } |
| "r_874_Illegal HV mrdn device mrdn_hv must not overlap hvtp" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap hvtp |
| mrdn_hv AND hvtp |
| } |
| "r_875_Illegal HV mrdn device mrdn_hv must not overlap lvtn" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap lvtn |
| mrdn_hv AND lvtn |
| } |
| "r_876_Illegal HV mrdn device mrdn_hv must not overlap pnp" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap pnp |
| mrdn_hv AND pnp |
| } |
| "r_877_Illegal HV mrdn device mrdn_hv must not overlap DiodeID" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap DiodeID |
| mrdn_hv AND DiodeID |
| } |
| "r_878_Illegal HV mrdn device mrdn_hv must not overlap COREID" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap COREID |
| mrdn_hv AND COREID |
| } |
| "r_879_Illegal HV mrdn device mrdn_hv must not overlap PHdiodeID" { |
| @ Illegal HV mrdn device: mrdn_hv must not overlap PHdiodeID |
| mrdn_hv AND PHdiodeID |
| } |
| "r_880_Illegal HV mrdp device mrdp_hv must not overlap ncm" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap ncm |
| mrdp_hv AND ncm |
| } |
| "r_881_Illegal HV mrdp device mrdp_hv must not overlap tap" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap tap |
| mrdp_hv AND tap |
| } |
| "r_882_Illegal HV mrdp device mrdp_hv must not overlap poly" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap poly |
| mrdp_hv AND poly |
| } |
| "r_883_Illegal HV mrdp device mrdp_hv must not overlap polyres" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap polyres |
| mrdp_hv AND polyres |
| } |
| "r_884_Illegal HV mrdp device mrdp_hv must not overlap polycut" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap polycut |
| mrdp_hv AND polycut |
| } |
| "r_885_Illegal HV mrdp device mrdp_hv must not overlap li1cut" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap li1cut |
| mrdp_hv AND li1cut |
| } |
| "r_886_Illegal HV mrdp device mrdp_hv must not overlap fuse" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap fuse |
| mrdp_hv AND fuse |
| } |
| "r_887_Illegal HV mrdp device mrdp_hv must not overlap nsdm" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap nsdm |
| mrdp_hv AND nsdm |
| } |
| "r_888_Illegal HV mrdp device mrdp_hv must not overlap capacitor" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap capacitor |
| mrdp_hv AND capacitor |
| } |
| "r_889_Illegal HV mrdp device mrdp_hv must not overlap LVID" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap LVID |
| mrdp_hv AND LVID |
| } |
| "r_890_Illegal HV mrdp device mrdp_hv must not overlap ENID" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap ENID |
| mrdp_hv AND ENID |
| } |
| "r_891_Illegal HV mrdp device mrdp_hv must not overlap hvtp" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap hvtp |
| mrdp_hv AND hvtp |
| } |
| "r_892_Illegal HV mrdp device mrdp_hv must not overlap lvtn" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap lvtn |
| mrdp_hv AND lvtn |
| } |
| "r_893_Illegal HV mrdp device mrdp_hv must not overlap pnp" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap pnp |
| mrdp_hv AND pnp |
| } |
| "r_894_Illegal HV mrdp device mrdp_hv must not overlap DiodeID" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap DiodeID |
| mrdp_hv AND DiodeID |
| } |
| "r_895_Illegal HV mrdp device mrdp_hv must not overlap COREID" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap COREID |
| mrdp_hv AND COREID |
| } |
| "r_896_Illegal HV mrdp device mrdp_hv must not overlap PHdiodeID" { |
| @ Illegal HV mrdp device: mrdp_hv must not overlap PHdiodeID |
| mrdp_hv AND PHdiodeID |
| } |
| "r_897_Illegal mrp1 device mrp1 must not overlap ncm" { |
| @ Illegal mrp1 device: mrp1 must not overlap ncm |
| mrp1 AND ncm |
| } |
| "r_898_Illegal mrp1 device mrp1 must not overlap tap" { |
| @ Illegal mrp1 device: mrp1 must not overlap tap |
| mrp1 AND tap |
| } |
| "r_899_Illegal mrp1 device mrp1 must not overlap diff" { |
| @ Illegal mrp1 device: mrp1 must not overlap diff |
| mrp1 AND diff |
| } |
| "r_900_Illegal mrp1 device mrp1 must not overlap diffres" { |
| @ Illegal mrp1 device: mrp1 must not overlap diffres |
| mrp1 AND diffres |
| } |
| "r_901_Illegal mrp1 device mrp1 must not overlap diffcut" { |
| @ Illegal mrp1 device: mrp1 must not overlap diffcut |
| mrp1 AND diffcut |
| } |
| "r_902_Illegal mrp1 device mrp1 must not overlap li1cut" { |
| @ Illegal mrp1 device: mrp1 must not overlap li1cut |
| mrp1 AND li1cut |
| } |
| "r_903_Illegal mrp1 device mrp1 must not overlap fuse" { |
| @ Illegal mrp1 device: mrp1 must not overlap fuse |
| mrp1 AND fuse |
| } |
| "r_904_Illegal mrp1 device mrp1 must not overlap capacitor" { |
| @ Illegal mrp1 device: mrp1 must not overlap capacitor |
| mrp1 AND capacitor |
| } |
| "r_905_Illegal mrp1 device mrp1 must not overlap LVID" { |
| @ Illegal mrp1 device: mrp1 must not overlap LVID |
| mrp1 AND LVID |
| } |
| "r_906_Illegal mrp1 device mrp1 must not overlap ENID" { |
| @ Illegal mrp1 device: mrp1 must not overlap ENID |
| mrp1 AND ENID |
| } |
| "r_907_Illegal mrp1 device mrp1 must not overlap hvtp" { |
| @ Illegal mrp1 device: mrp1 must not overlap hvtp |
| mrp1 AND hvtp |
| } |
| "r_908_Illegal mrp1 device mrp1 must not overlap lvtn" { |
| @ Illegal mrp1 device: mrp1 must not overlap lvtn |
| mrp1 AND lvtn |
| } |
| "r_909_Illegal mrp1 device mrp1 must not overlap pnp" { |
| @ Illegal mrp1 device: mrp1 must not overlap pnp |
| mrp1 AND pnp |
| } |
| "r_910_Illegal mrp1 device mrp1 must not overlap DiodeID" { |
| @ Illegal mrp1 device: mrp1 must not overlap DiodeID |
| mrp1 AND DiodeID |
| } |
| "r_911_Illegal mrp1 device mrp1 must not overlap COREID" { |
| @ Illegal mrp1 device: mrp1 must not overlap COREID |
| mrp1 AND COREID |
| } |
| "r_912_Illegal ml1 device mrl1 must not overlap LVID" { |
| @ Illegal ml1 device: mrl1 must not overlap LVID |
| mrl1 AND LVID |
| } |
| "r_913_Illegal ml1 device mrl1 must not overlap licon1" { |
| @ Illegal ml1 device: mrl1 must not overlap licon1 |
| mrl1 AND licon1 |
| } |
| "r_914_Illegal ml1 device mrl1 must not overlap capacitor" { |
| @ Illegal ml1 device: mrl1 must not overlap capacitor |
| mrl1 AND capacitor |
| } |
| "r_915_Illegal ml1 device mrl1 must not overlap ENID" { |
| @ Illegal ml1 device: mrl1 must not overlap ENID |
| mrl1 AND ENID |
| } |
| "r_916_Illegal ml1 device mrl1 must not overlap COREID" { |
| @ Illegal ml1 device: mrl1 must not overlap COREID |
| mrl1 AND COREID |
| } |
| "r_917_Illegal ml1 device mrl1 must not overlap PHdiodeID" { |
| @ Illegal ml1 device: mrl1 must not overlap PHdiodeID |
| mrl1 AND PHdiodeID |
| } |
| "r_918_Illegal pwell resistor device pwellresistor must not overlap nwell" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap nwell |
| pwellresistor AND nwell |
| } |
| "r_919_Illegal pwell resistor device pwellresistor must not overlap poly" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap poly |
| pwellresistor AND poly |
| } |
| "r_920_Illegal pwell resistor device pwellresistor must not overlap polyres" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap polyres |
| pwellresistor AND polyres |
| } |
| "r_921_Illegal pwell resistor device pwellresistor must not overlap polycut" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap polycut |
| pwellresistor AND polycut |
| } |
| "r_922_Illegal pwell resistor device pwellresistor must not overlap li1cut" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap li1cut |
| pwellresistor AND li1cut |
| } |
| "r_923_Illegal pwell resistor device pwellresistor must not overlap fuse" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap fuse |
| pwellresistor AND fuse |
| } |
| "r_924_Illegal pwell resistor device pwellresistor must not overlap capacitor" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap capacitor |
| pwellresistor AND capacitor |
| } |
| "r_925_Illegal pwell resistor device pwellresistor must not overlap LVID" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap LVID |
| pwellresistor AND LVID |
| } |
| "r_926_Illegal pwell resistor device pwellresistor must not overlap ENID" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap ENID |
| pwellresistor AND ENID |
| } |
| "r_927_Illegal pwell resistor device pwellresistor must not overlap COREID" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap COREID |
| pwellresistor AND COREID |
| } |
| "r_928_Illegal pwell resistor device pwellresistor must not overlap PHdiodeID" { |
| @ Illegal pwell resistor device: pwellresistor must not overlap PHdiodeID |
| pwellresistor AND PHdiodeID |
| } |
| "r_929_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap tap" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap tap |
| xhrpoly_0p35 AND tap |
| } |
| "r_930_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap diff" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap diff |
| xhrpoly_0p35 AND diff |
| } |
| "r_931_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap diffres" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap diffres |
| xhrpoly_0p35 AND diffres |
| } |
| "r_932_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap diffcut" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap diffcut |
| xhrpoly_0p35 AND diffcut |
| } |
| "r_933_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap li1cut" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap li1cut |
| xhrpoly_0p35 AND li1cut |
| } |
| "r_934_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap fuse" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap fuse |
| xhrpoly_0p35 AND fuse |
| } |
| "r_935_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap nsdm" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap nsdm |
| xhrpoly_0p35 AND nsdm |
| } |
| "r_936_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap capacitor" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap capacitor |
| xhrpoly_0p35 AND capacitor |
| } |
| "r_937_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap LVID" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap LVID |
| xhrpoly_0p35 AND LVID |
| } |
| "r_938_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap ENID" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap ENID |
| xhrpoly_0p35 AND ENID |
| } |
| "r_939_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap hvtp" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap hvtp |
| xhrpoly_0p35 AND hvtp |
| } |
| "r_940_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap lvtn" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap lvtn |
| xhrpoly_0p35 AND lvtn |
| } |
| "r_941_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap pnp" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap pnp |
| xhrpoly_0p35 AND pnp |
| } |
| "r_942_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap DiodeID" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap DiodeID |
| xhrpoly_0p35 AND DiodeID |
| } |
| "r_943_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap COREID" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap COREID |
| xhrpoly_0p35 AND COREID |
| } |
| "r_944_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap PHdiodeID" { |
| @ Illegal xhrpoly_0p35 device: xhrpoly_0p35 must not overlap PHdiodeID |
| xhrpoly_0p35 AND PHdiodeID |
| } |
| "r_945_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap tap" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap tap |
| xhrpoly_0p69 AND tap |
| } |
| "r_946_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap diff" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap diff |
| xhrpoly_0p69 AND diff |
| } |
| "r_947_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap diffres" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap diffres |
| xhrpoly_0p69 AND diffres |
| } |
| "r_948_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap diffcut" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap diffcut |
| xhrpoly_0p69 AND diffcut |
| } |
| "r_949_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap li1cut" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap li1cut |
| xhrpoly_0p69 AND li1cut |
| } |
| "r_950_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap fuse" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap fuse |
| xhrpoly_0p69 AND fuse |
| } |
| "r_951_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap nsdm" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap nsdm |
| xhrpoly_0p69 AND nsdm |
| } |
| "r_952_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap capacitor" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap capacitor |
| xhrpoly_0p69 AND capacitor |
| } |
| "r_953_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap LVID" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap LVID |
| xhrpoly_0p69 AND LVID |
| } |
| "r_954_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap ENID" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap ENID |
| xhrpoly_0p69 AND ENID |
| } |
| "r_955_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap hvtp" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap hvtp |
| xhrpoly_0p69 AND hvtp |
| } |
| "r_956_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap lvtn" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap lvtn |
| xhrpoly_0p69 AND lvtn |
| } |
| "r_957_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap pnp" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap pnp |
| xhrpoly_0p69 AND pnp |
| } |
| "r_958_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap DiodeID" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap DiodeID |
| xhrpoly_0p69 AND DiodeID |
| } |
| "r_959_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap COREID" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap COREID |
| xhrpoly_0p69 AND COREID |
| } |
| "r_960_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap PHdiodeID" { |
| @ Illegal xhrpoly_0p69 device: xhrpoly_0p69 must not overlap PHdiodeID |
| xhrpoly_0p69 AND PHdiodeID |
| } |
| "r_961_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap tap" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap tap |
| xhrpoly_1p41 AND tap |
| } |
| "r_962_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap diff" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap diff |
| xhrpoly_1p41 AND diff |
| } |
| "r_963_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap diffres" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap diffres |
| xhrpoly_1p41 AND diffres |
| } |
| "r_964_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap diffcut" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap diffcut |
| xhrpoly_1p41 AND diffcut |
| } |
| "r_965_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap li1cut" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap li1cut |
| xhrpoly_1p41 AND li1cut |
| } |
| "r_966_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap fuse" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap fuse |
| xhrpoly_1p41 AND fuse |
| } |
| "r_967_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap nsdm" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap nsdm |
| xhrpoly_1p41 AND nsdm |
| } |
| "r_968_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap capacitor" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap capacitor |
| xhrpoly_1p41 AND capacitor |
| } |
| "r_969_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap LVID" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap LVID |
| xhrpoly_1p41 AND LVID |
| } |
| "r_970_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap ENID" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap ENID |
| xhrpoly_1p41 AND ENID |
| } |
| "r_971_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap hvtp" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap hvtp |
| xhrpoly_1p41 AND hvtp |
| } |
| "r_972_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap lvtn" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap lvtn |
| xhrpoly_1p41 AND lvtn |
| } |
| "r_973_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap pnp" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap pnp |
| xhrpoly_1p41 AND pnp |
| } |
| "r_974_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap DiodeID" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap DiodeID |
| xhrpoly_1p41 AND DiodeID |
| } |
| "r_975_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap COREID" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap COREID |
| xhrpoly_1p41 AND COREID |
| } |
| "r_976_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap PHdiodeID" { |
| @ Illegal xhrpoly_1p41 device: xhrpoly_1p41 must not overlap PHdiodeID |
| xhrpoly_1p41 AND PHdiodeID |
| } |
| "r_977_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap tap" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap tap |
| xhrpoly_2p85 AND tap |
| } |
| "r_978_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap diff" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap diff |
| xhrpoly_2p85 AND diff |
| } |
| "r_979_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap diffres" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap diffres |
| xhrpoly_2p85 AND diffres |
| } |
| "r_980_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap diffcut" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap diffcut |
| xhrpoly_2p85 AND diffcut |
| } |
| "r_981_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap li1cut" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap li1cut |
| xhrpoly_2p85 AND li1cut |
| } |
| "r_982_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap fuse" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap fuse |
| xhrpoly_2p85 AND fuse |
| } |
| "r_983_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap nsdm" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap nsdm |
| xhrpoly_2p85 AND nsdm |
| } |
| "r_984_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap capacitor" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap capacitor |
| xhrpoly_2p85 AND capacitor |
| } |
| "r_985_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap LVID" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap LVID |
| xhrpoly_2p85 AND LVID |
| } |
| "r_986_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap ENID" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap ENID |
| xhrpoly_2p85 AND ENID |
| } |
| "r_987_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap hvtp" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap hvtp |
| xhrpoly_2p85 AND hvtp |
| } |
| "r_988_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap lvtn" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap lvtn |
| xhrpoly_2p85 AND lvtn |
| } |
| "r_989_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap pnp" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap pnp |
| xhrpoly_2p85 AND pnp |
| } |
| "r_990_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap DiodeID" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap DiodeID |
| xhrpoly_2p85 AND DiodeID |
| } |
| "r_991_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap COREID" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap COREID |
| xhrpoly_2p85 AND COREID |
| } |
| "r_992_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap PHdiodeID" { |
| @ Illegal xhrpoly_2p85 device: xhrpoly_2p85 must not overlap PHdiodeID |
| xhrpoly_2p85 AND PHdiodeID |
| } |
| "r_993_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap tap" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap tap |
| xhrpoly_5p73 AND tap |
| } |
| "r_994_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap diff" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap diff |
| xhrpoly_5p73 AND diff |
| } |
| "r_995_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap diffres" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap diffres |
| xhrpoly_5p73 AND diffres |
| } |
| "r_996_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap diffcut" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap diffcut |
| xhrpoly_5p73 AND diffcut |
| } |
| "r_997_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap li1cut" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap li1cut |
| xhrpoly_5p73 AND li1cut |
| } |
| "r_998_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap fuse" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap fuse |
| xhrpoly_5p73 AND fuse |
| } |
| "r_999_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap nsdm" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap nsdm |
| xhrpoly_5p73 AND nsdm |
| } |
| "r_1000_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap capacitor" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap capacitor |
| xhrpoly_5p73 AND capacitor |
| } |
| "r_1001_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap LVID" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap LVID |
| xhrpoly_5p73 AND LVID |
| } |
| "r_1002_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap ENID" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap ENID |
| xhrpoly_5p73 AND ENID |
| } |
| "r_1003_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap hvtp" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap hvtp |
| xhrpoly_5p73 AND hvtp |
| } |
| "r_1004_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap lvtn" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap lvtn |
| xhrpoly_5p73 AND lvtn |
| } |
| "r_1005_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap pnp" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap pnp |
| xhrpoly_5p73 AND pnp |
| } |
| "r_1006_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap DiodeID" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap DiodeID |
| xhrpoly_5p73 AND DiodeID |
| } |
| "r_1007_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap COREID" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap COREID |
| xhrpoly_5p73 AND COREID |
| } |
| "r_1008_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap PHdiodeID" { |
| @ Illegal xhrpoly_5p73 device: xhrpoly_5p73 must not overlap PHdiodeID |
| xhrpoly_5p73 AND PHdiodeID |
| } |
| |
| LVS REDUCE R PARALLEL YES [ |
| TOLERANCE w 1.0 |
| l 1.0 |
| |
| EFFECTIVE m , w , l |
| m = SUM( m ) |
| w = SUM( (w * m) ) / m |
| l = SUM( (l * m) ) / m |
| ] |
| |
| LVS REDUCE R SERIES POS NEG NO |
| |
| pyshort = poly AND py_short |
| DEVICE R(short) pyshort POLY_cond(POS) POLY_cond(NEG) <poly> ("POS" "NEG") BY NET [ |
| PROPERTY R , m |
| R = 0.01 |
| m = 1 |
| ] |
| |
| TRACE PROPERTY R(short) m m 0 |
| |
| lishort = li1 AND li_short |
| DEVICE R(short) lishort LI1_cond(POS) LI1_cond(NEG) <li1> ("POS" "NEG") BY NET [ |
| PROPERTY R , m |
| R = 0.01 |
| m = 1 |
| ] |
| |
| m1short = met1 AND m1_short |
| DEVICE R(short) m1short MET1_cond(POS) MET1_cond(NEG) <met1> ("POS" "NEG") BY NET [ |
| PROPERTY R , m |
| R = 0.01 |
| m = 1 |
| ] |
| |
| m2short = met2 AND m2_short |
| DEVICE R(short) m2short MET2_cond(POS) MET2_cond(NEG) <met2> ("POS" "NEG") BY NET [ |
| PROPERTY R , m |
| R = 0.01 |
| m = 1 |
| ] |
| |
| m3short = met3 AND m3_short |
| DEVICE R(short) m3short MET3_cond(POS) MET3_cond(NEG) <met3> ("POS" "NEG") BY NET [ |
| PROPERTY R , m |
| R = 0.01 |
| m = 1 |
| ] |
| |
| m4short = met4 AND m4_short |
| DEVICE R(short) m4short MET4_cond(POS) MET4_cond(NEG) <met4> ("POS" "NEG") BY NET [ |
| PROPERTY R , m |
| R = 0.01 |
| m = 1 |
| ] |
| |
| m5short = met5 AND m5_short |
| DEVICE R(short) m5short MET5_cond(POS) MET5_cond(NEG) <met5> ("POS" "NEG") BY NET [ |
| PROPERTY R , m |
| R = 0.01 |
| m = 1 |
| ] |
| |
| rdshort = rdl AND rd_short |
| DEVICE R(short) rdshort RDL_cond(POS) RDL_cond(NEG) <rdl> ("POS" "NEG") BY NET [ |
| PROPERTY R , m |
| R = 0.01 |
| m = 1 |
| ] |
| |
| LVS REDUCE R(short) PARALLEL YES [EFFECTIVE m |
| m = SUM( m ) |
| ] |
| |
| LVS REDUCE R(short) SERIES POS NEG NO |
| |
| m4fuse = met4 AND fuse |
| |
| DEVICE R(fuse) m4fuse MET4_cond(POS) MET4_cond(NEG) <met4> ("POS" "NEG") BY SHAPE [ |
| PROPERTY w , l , m |
| dev_perim = perimeter( m4fuse ) * 0.5 * L_scale |
| w = perimeter_inside( m4fuse , met4 ) * 0.5 * L_scale |
| nbend = bends( m4fuse ) |
| l = dev_perim - (w * (1 + (nbend * 0.5))) |
| m = 1 |
| ] |
| |
| TRACE PROPERTY R(fuse) w w 1 |
| TRACE PROPERTY R(fuse) l l 1 |
| TRACE PROPERTY R(fuse) m m 0 |
| |
| LVS REDUCE R(fuse) PARALLEL NO |
| |
| LVS REDUCE R(fuse) SERIES POS NEG NO |
| |
| // ;ss match lvsRules |
| |
| "r_1009_Illegal fuse device m4fuse must not overlap nwell" { |
| @ Illegal fuse device: m4fuse must not overlap nwell |
| m4fuse AND nwell |
| } |
| "r_1010_Illegal fuse device m4fuse must not overlap tap" { |
| @ Illegal fuse device: m4fuse must not overlap tap |
| m4fuse AND tap |
| } |
| "r_1011_Illegal fuse device m4fuse must not overlap diff" { |
| @ Illegal fuse device: m4fuse must not overlap diff |
| m4fuse AND diff |
| } |
| "r_1012_Illegal fuse device m4fuse must not overlap diffres" { |
| @ Illegal fuse device: m4fuse must not overlap diffres |
| m4fuse AND diffres |
| } |
| "r_1013_Illegal fuse device m4fuse must not overlap diffcut" { |
| @ Illegal fuse device: m4fuse must not overlap diffcut |
| m4fuse AND diffcut |
| } |
| "r_1014_Illegal fuse device m4fuse must not overlap poly" { |
| @ Illegal fuse device: m4fuse must not overlap poly |
| m4fuse AND poly |
| } |
| "r_1015_Illegal fuse device m4fuse must not overlap polyres" { |
| @ Illegal fuse device: m4fuse must not overlap polyres |
| m4fuse AND polyres |
| } |
| "r_1016_Illegal fuse device m4fuse must not overlap polycut" { |
| @ Illegal fuse device: m4fuse must not overlap polycut |
| m4fuse AND polycut |
| } |
| "r_1017_Illegal fuse device m4fuse must not overlap licon1" { |
| @ Illegal fuse device: m4fuse must not overlap licon1 |
| m4fuse AND licon1 |
| } |
| "r_1018_Illegal fuse device m4fuse must not overlap li1" { |
| @ Illegal fuse device: m4fuse must not overlap li1 |
| m4fuse AND li1 |
| } |
| "r_1019_Illegal fuse device m4fuse must not overlap li1res" { |
| @ Illegal fuse device: m4fuse must not overlap li1res |
| m4fuse AND li1res |
| } |
| "r_1020_Illegal fuse device m4fuse must not overlap li1cut" { |
| @ Illegal fuse device: m4fuse must not overlap li1cut |
| m4fuse AND li1cut |
| } |
| "r_1021_Illegal fuse device m4fuse must not overlap capacitor" { |
| @ Illegal fuse device: m4fuse must not overlap capacitor |
| m4fuse AND capacitor |
| } |
| "r_1022_Illegal fuse device m4fuse must not overlap LVID" { |
| @ Illegal fuse device: m4fuse must not overlap LVID |
| m4fuse AND LVID |
| } |
| "r_1023_Illegal fuse device m4fuse must not overlap ENID" { |
| @ Illegal fuse device: m4fuse must not overlap ENID |
| m4fuse AND ENID |
| } |
| "r_1024_Illegal fuse device m4fuse must not overlap hvtp" { |
| @ Illegal fuse device: m4fuse must not overlap hvtp |
| m4fuse AND hvtp |
| } |
| "r_1025_Illegal fuse device m4fuse must not overlap lvtn" { |
| @ Illegal fuse device: m4fuse must not overlap lvtn |
| m4fuse AND lvtn |
| } |
| "r_1026_Illegal fuse device m4fuse must not overlap hvi" { |
| @ Illegal fuse device: m4fuse must not overlap hvi |
| m4fuse AND hvi |
| } |
| "r_1027_Illegal fuse device m4fuse must not overlap pnp" { |
| @ Illegal fuse device: m4fuse must not overlap pnp |
| m4fuse AND pnp |
| } |
| "r_1028_Illegal fuse device m4fuse must not overlap DiodeID" { |
| @ Illegal fuse device: m4fuse must not overlap DiodeID |
| m4fuse AND DiodeID |
| } |
| "r_1029_Illegal fuse device m4fuse must not overlap ESDID" { |
| @ Illegal fuse device: m4fuse must not overlap ESDID |
| m4fuse AND ESDID |
| } |
| "r_1030_Illegal fuse device m4fuse must not overlap PHdiodeID" { |
| @ Illegal fuse device: m4fuse must not overlap PHdiodeID |
| m4fuse AND PHdiodeID |
| } |
| |
| q0metop1 = metop1 NOT met3 |
| q0metop2 = metop2 NOT met3 |
| q0metop3 = metop3 NOT met3 |
| q0metop4 = metop4 NOT met3 |
| q0metop5 = metop5 NOT met3 |
| q0metop6 = metop6 NOT met3 |
| q0metop7 = metop7 NOT met3 |
| q0metop8 = metop8 NOT met3 |
| |
| DEVICE R(metop) q0metop1 MET3_cond(POS) MET3_cond(NEG) ("POS" "NEG") BY NET [ |
| PROPERTY w , l , metopNumber |
| metopNumber = 1 |
| A = area( q0metop1 ) * L_scale2 |
| w = perimeter_coincide( q0metop1 , MET3_cond ) * 0.5 * L_scale |
| l = A / w |
| ] |
| |
| |
| DEVICE R(metop) q0metop2 MET3_cond(POS) MET3_cond(NEG) ("POS" "NEG") BY NET [ |
| PROPERTY w , l , metopNumber |
| metopNumber = 2 |
| A = area( q0metop2 ) * L_scale2 |
| w = perimeter_coincide( q0metop2 , MET3_cond ) * 0.5 * L_scale |
| l = A / w |
| ] |
| |
| |
| DEVICE R(metop) q0metop3 MET3_cond(POS) MET3_cond(NEG) ("POS" "NEG") BY NET [ |
| PROPERTY w , l , metopNumber |
| metopNumber = 3 |
| A = area( q0metop3 ) * L_scale2 |
| w = perimeter_coincide( q0metop3 , MET3_cond ) * 0.5 * L_scale |
| l = A / w |
| ] |
| |
| |
| DEVICE R(metop) q0metop4 MET3_cond(POS) MET3_cond(NEG) ("POS" "NEG") BY NET [ |
| PROPERTY w , l , metopNumber |
| metopNumber = 4 |
| A = area( q0metop4 ) * L_scale2 |
| w = perimeter_coincide( q0metop4 , MET3_cond ) * 0.5 * L_scale |
| l = A / w |
| ] |
| |
| |
| DEVICE R(metop) q0metop5 MET3_cond(POS) MET3_cond(NEG) ("POS" "NEG") BY NET [ |
| PROPERTY w , l , metopNumber |
| metopNumber = 5 |
| A = area( q0metop5 ) * L_scale2 |
| w = perimeter_coincide( q0metop5 , MET3_cond ) * 0.5 * L_scale |
| l = A / w |
| ] |
| |
| |
| DEVICE R(metop) q0metop6 MET3_cond(POS) MET3_cond(NEG) ("POS" "NEG") BY NET [ |
| PROPERTY w , l , metopNumber |
| metopNumber = 6 |
| A = area( q0metop6 ) * L_scale2 |
| w = perimeter_coincide( q0metop6 , MET3_cond ) * 0.5 * L_scale |
| l = A / w |
| ] |
| |
| |
| DEVICE R(metop) q0metop7 MET3_cond(POS) MET3_cond(NEG) ("POS" "NEG") BY NET [ |
| PROPERTY w , l , metopNumber |
| metopNumber = 7 |
| A = area( q0metop7 ) * L_scale2 |
| w = perimeter_coincide( q0metop7 , MET3_cond ) * 0.5 * L_scale |
| l = A / w |
| ] |
| |
| |
| DEVICE R(metop) q0metop8 MET3_cond(POS) MET3_cond(NEG) ("POS" "NEG") BY NET [ |
| PROPERTY w , l , metopNumber |
| metopNumber = 8 |
| A = area( q0metop8 ) * L_scale2 |
| w = perimeter_coincide( q0metop8 , MET3_cond ) * 0.5 * L_scale |
| l = A / w |
| ] |
| |
| |
| TRACE PROPERTY R(metop) metopNumber metopNumber 0 |
| |
| LVS REDUCE R(metop) PARALLEL YES [ |
| TOLERANCE metopNumber 0 |
| |
| EFFECTIVE metopNumber |
| metopNumber = max( metopNumber ) |
| ] |
| |
| LVS REDUCE R(metop) SERIES POS NEG NO |
| |
| liprobe = EXPAND TEXT "?" li1probe BY 0.005 |
| LI1_PROBE_cond = SIZE liprobe BY 0.005 |
| CONNECT LI1_PROBE_cond |
| TEXT LAYER li1probe ATTACH li1probe LI1_PROBE_cond |
| DEVICE Probe(probe_li1probe) liprobe LI1_PROBE_cond(probe) LI1_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER li1probe [ |
| PROPERTY probeType |
| probeType = 0 |
| ] |
| |
| |
| pyprobe = EXPAND TEXT "?" polyprobe BY 0.005 |
| POLY_PROBE_cond = SIZE pyprobe BY 0.005 |
| CONNECT POLY_PROBE_cond |
| TEXT LAYER polyprobe ATTACH polyprobe POLY_PROBE_cond |
| DEVICE Probe(probe_polyprobe) pyprobe POLY_PROBE_cond(probe) POLY_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER polyprobe [ |
| PROPERTY probeType |
| probeType = 0 |
| ] |
| |
| |
| m1probe = EXPAND TEXT "?" met1probe BY 0.005 |
| MET1_PROBE_cond = SIZE m1probe BY 0.005 |
| CONNECT MET1_PROBE_cond |
| TEXT LAYER met1probe ATTACH met1probe MET1_PROBE_cond |
| DEVICE Probe(probe_met1probe) m1probe MET1_PROBE_cond(probe) MET1_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met1probe [ |
| PROPERTY probeType |
| probeType = 0 |
| ] |
| |
| |
| m2probe = EXPAND TEXT "?" met2probe BY 0.005 |
| MET2_PROBE_cond = SIZE m2probe BY 0.005 |
| CONNECT MET2_PROBE_cond |
| TEXT LAYER met2probe ATTACH met2probe MET2_PROBE_cond |
| DEVICE Probe(probe_met2probe) m2probe MET2_PROBE_cond(probe) MET2_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met2probe [ |
| PROPERTY probeType |
| probeType = 0 |
| ] |
| |
| |
| m3probe = EXPAND TEXT "?" met3probe BY 0.005 |
| MET3_PROBE_cond = SIZE m3probe BY 0.005 |
| CONNECT MET3_PROBE_cond |
| TEXT LAYER met3probe ATTACH met3probe MET3_PROBE_cond |
| DEVICE Probe(probe_met3probe) m3probe MET3_PROBE_cond(probe) MET3_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met3probe [ |
| PROPERTY probeType |
| probeType = 0 |
| ] |
| |
| |
| m4probe = EXPAND TEXT "?" met4probe BY 0.005 |
| MET4_PROBE_cond = SIZE m4probe BY 0.005 |
| CONNECT MET4_PROBE_cond |
| TEXT LAYER met4probe ATTACH met4probe MET4_PROBE_cond |
| DEVICE Probe(probe_met4probe) m4probe MET4_PROBE_cond(probe) MET4_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met4probe [ |
| PROPERTY probeType |
| probeType = 0 |
| ] |
| |
| |
| m5probe = EXPAND TEXT "?" met5probe BY 0.005 |
| MET5_PROBE_cond = SIZE m5probe BY 0.005 |
| CONNECT MET5_PROBE_cond |
| TEXT LAYER met5probe ATTACH met5probe MET5_PROBE_cond |
| DEVICE Probe(probe_met5probe) m5probe MET5_PROBE_cond(probe) MET5_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met5probe [ |
| PROPERTY probeType |
| probeType = 0 |
| ] |
| |
| |
| q4SubstrateTmp1 = COPY pwellresistor |
| q5SubstrateTmp1 = COPY SubstrateTmp1 |
| Substrate = q5SubstrateTmp1 NOT q4SubstrateTmp1 |
| CONNECT pwell_pin Substrate |
| TEXT LAYER pwellpt ATTACH pwellpt pwell_pin ATTACH pwellpt Substrate |
| TEXT LAYER pwelltt ATTACH pwelltt Substrate |
| q4SubstrateIsoTmp = COPY pwellresistor |
| q5SubstrateIsoTmp = COPY SubstrateIsoTmp |
| SubstrateIso = q5SubstrateIsoTmp NOT (q9mrpw OR q4SubstrateIsoTmp) |
| CONNECT pwelliso_pin SubstrateIso |
| TEXT LAYER pwellisopt ATTACH pwellisopt pwelliso_pin ATTACH pwellisopt SubstrateIso |
| TEXT LAYER pwellisott ATTACH pwellisott SubstrateIso |
| q4dnwell = COPY 4005 |
| q5dnwell = COPY dnwell |
| DNWELL_cond = q5dnwell NOT q4dnwell |
| q4MosNwell_tmp = COPY 4006 |
| q5MosNwell_tmp = COPY MosNwell_tmp |
| MosNwell = q5MosNwell_tmp NOT q4MosNwell_tmp |
| CONNECT nwell_pin MosNwell |
| TEXT LAYER nwellpt ATTACH nwellpt nwell_pin ATTACH nwellpt MosNwell |
| TEXT LAYER nwelltt ATTACH nwelltt MosNwell |
| q4PnpNwell_tmp = COPY 4007 |
| q5PnpNwell_tmp = COPY PnpNwell_tmp |
| PnpNwell = q5PnpNwell_tmp NOT q4PnpNwell_tmp |
| CONNECT nwell_pin PnpNwell |
| TEXT LAYER nwellpt ATTACH nwellpt nwell_pin ATTACH nwellpt PnpNwell |
| TEXT LAYER nwelltt ATTACH nwelltt PnpNwell |
| q4NpnNwell_tmp = COPY 4008 |
| q5NpnNwell_tmp = COPY NpnNwell_tmp |
| NpnNwell = q5NpnNwell_tmp NOT q4NpnNwell_tmp |
| CONNECT nwell_pin NpnNwell |
| TEXT LAYER nwellpt ATTACH nwellpt nwell_pin ATTACH nwellpt NpnNwell |
| TEXT LAYER nwelltt ATTACH nwelltt NpnNwell |
| q4pwresBiasTerm = COPY 4009 |
| q5pwresBiasTerm = COPY pwresBiasTerm |
| pwresBiasTerm_cond = q5pwresBiasTerm NOT q4pwresBiasTerm |
| q4PMOSDIFF = TAPgate OR MOSDIFFandPOLY |
| q5PMOSDIFF = COPY PMOSDIFF |
| PDIFF_cond = q5PMOSDIFF NOT ((q9mrdp_lv OR q9mrdp_hv) OR q4PMOSDIFF) |
| CONNECT diff_pin PDIFF_cond |
| TEXT LAYER diffpt ATTACH diffpt diff_pin ATTACH diffpt PDIFF_cond |
| TEXT LAYER difftt ATTACH difftt PDIFF_cond |
| q4NMOSDIFF = TAPgate OR MOSDIFFandPOLY |
| q5NMOSDIFF = COPY NMOSDIFF |
| NDIFF_cond = q5NMOSDIFF NOT ((q9mrdn_lv OR q9mrdn_hv) OR q4NMOSDIFF) |
| CONNECT diff_pin NDIFF_cond |
| TEXT LAYER diffpt ATTACH diffpt diff_pin ATTACH diffpt NDIFF_cond |
| TEXT LAYER difftt ATTACH difftt NDIFF_cond |
| q4PNPDIFF = COPY 4010 |
| q5PNPDIFF = COPY PNPDIFF |
| PNPDIFF_cond = q5PNPDIFF NOT q4PNPDIFF |
| CONNECT diff_pin PNPDIFF_cond |
| TEXT LAYER diffpt ATTACH diffpt diff_pin ATTACH diffpt PNPDIFF_cond |
| TEXT LAYER difftt ATTACH difftt PNPDIFF_cond |
| q4NPNDIFF = COPY 4011 |
| q5NPNDIFF = COPY NPNDIFF |
| NPNDIFF_cond = q5NPNDIFF NOT q4NPNDIFF |
| CONNECT diff_pin NPNDIFF_cond |
| TEXT LAYER diffpt ATTACH diffpt diff_pin ATTACH diffpt NPNDIFF_cond |
| TEXT LAYER difftt ATTACH difftt NPNDIFF_cond |
| q4PTAP_pnp = COPY TAPgate |
| q5PTAP_pnp = COPY PTAP_pnp |
| PTAP_pnp_cond = q5PTAP_pnp NOT q4PTAP_pnp |
| q4PTAP_npn = COPY TAPgate |
| q5PTAP_npn = COPY PTAP_npn |
| PTAP_npn_cond = q5PTAP_npn NOT q4PTAP_npn |
| q4PTAP_defet20 = COPY TAPgate |
| q5PTAP_defet20 = COPY PTAP_defet20 |
| PTAP_defet20_cond = q5PTAP_defet20 NOT q4PTAP_defet20 |
| q4PTAP_notbjt = COPY TAPgate |
| q5PTAP_notbjt = COPY PTAP_notbjt |
| PTAP_notbjt_cond = q5PTAP_notbjt NOT q4PTAP_notbjt |
| q4PTAP_NotDnwell = COPY TAPgate |
| q5PTAP_NotDnwell = COPY PTAP_NotDnwell |
| PTAP_NotDnwell_cond = q5PTAP_NotDnwell NOT q4PTAP_NotDnwell |
| q4NTAP_pnp = COPY TAPgate |
| q5NTAP_pnp = COPY NTAP_pnp |
| NTAP_pnp_cond = q5NTAP_pnp NOT q4NTAP_pnp |
| q4NTAP_npn = COPY TAPgate |
| q5NTAP_npn = COPY NTAP_npn |
| NTAP_npn_cond = q5NTAP_npn NOT q4NTAP_npn |
| q4NTAP_notbjt = COPY TAPgate |
| q5NTAP_notbjt = COPY NTAP_notbjt |
| NTAP_notbjt_cond = q5NTAP_notbjt NOT q4NTAP_notbjt |
| q4BulkTermCap = COPY 4012 |
| q5BulkTermCap = COPY BulkTermCap |
| BulkTermCap_cond = q5BulkTermCap NOT q4BulkTermCap |
| q4BulkTermCapMos = COPY 4013 |
| q5BulkTermCapMos = COPY BulkTermCapMos |
| BulkTermCapMos_cond = q5BulkTermCapMos NOT q4BulkTermCapMos |
| q4BulkTermCapVpp = COPY 4014 |
| q5BulkTermCapVpp = COPY BulkTermCapVpp |
| BulkTermCap_condVpp = q5BulkTermCapVpp NOT q4BulkTermCapVpp |
| q4BulkTermCapVpp_M5 = COPY 4015 |
| q5BulkTermCapVpp_M5 = COPY BulkTermCapVpp_M5 |
| BulkTermCap_condVpp_M5 = q5BulkTermCapVpp_M5 NOT q4BulkTermCapVpp_M5 |
| q4BulkTermCapVpp_M4 = COPY 4016 |
| q5BulkTermCapVpp_M4 = COPY BulkTermCapVpp_M4 |
| BulkTermCap_condVpp_M4 = q5BulkTermCapVpp_M4 NOT q4BulkTermCapVpp_M4 |
| q4poly = COPY polycut |
| q5poly = poly OR POLY_waff |
| q0poly = varactor OR |
| (xhrpoly_x_1_device OR |
| (xhrpoly_x_2_device OR |
| (capdrawRCSz OR |
| (rcxDioESDblk OR |
| (xcmvpp_2RCX OR |
| (capdrawRCSz_M5 OR |
| (capdrawRCSz_M4 OR inductor))))))) |
| //POLY_cond_nrc = q2poly NOT ((((((((((((q9mrp1 OR pyshort) OR q4poly) OR q9xhrpoly_0p35_nwell) OR q9xhrpoly_0p69_nwell) OR q9xhrpoly_1p41_nwell) OR q9xhrpoly_2p85_nwell) OR q9xhrpoly_5p73_nwell) OR q9xhrpoly_0p35_sub) OR q9xhrpoly_0p69_sub) OR q9xhrpoly_1p41_sub) OR q9xhrpoly_2p85_sub) OR q9xhrpoly_5p73_sub) |
| //POLY_cond_nrc = q2poly NOT ((((((((((((q9mrp1 OR pyshort) OR q4poly) OR (q9xhrpoly_0p35_nwell OR q9xuhrpoly_0p35_nwell)) OR (q9xhrpoly_0p69_nwell OR q9xuhrpoly_0p69_nwell)) OR q9xhrpoly_1p41_nwell) OR (q9xhrpoly_2p85_nwell OR q9xuhrpoly_2p85_nwell)) OR (q9xhrpoly_5p73_nwell OR q9xuhrpoly_5p73_nwell)) OR (q9xhrpoly_0p35_sub OR q9xuhrpoly_0p35_sub)) OR (q9xhrpoly_0p69_sub OR q9xuhrpoly_0p69_sub)) OR (q9xhrpoly_1p41_sub OR q9xuhrpoly_1p41_sub)) OR (q9xhrpoly_2p85_sub OR q9xuhrpoly_2p85_sub)) OR (q9xhrpoly_5p73_sub OR q9xuhrpoly_5p73_sub)) |
| POLY_cond_nrc = q2poly NOT ((((((((((((((q9mrp1 OR pyshort) OR q4poly) OR (q9xhrpoly_0p35_nwell OR q9xuhrpoly_0p35_nwell)) OR (q9xhrpoly_0p69_nwell OR q9xuhrpoly_0p69_nwell)) OR q9xhrpoly_1p41_nwell) OR (q9xhrpoly_2p85_nwell OR q9xuhrpoly_2p85_nwell)) OR (q9xhrpoly_5p73_nwell OR q9xuhrpoly_5p73_nwell)) OR (q9xhrpoly_0p35_sub OR q9xuhrpoly_0p35_sub)) OR (q9xhrpoly_0p69_sub OR q9xuhrpoly_0p69_sub)) OR (q9xhrpoly_1p41_sub OR q9xuhrpoly_1p41_sub)) OR (q9xhrpoly_2p85_sub OR q9xuhrpoly_2p85_sub)) OR (q9xhrpoly_5p73_sub OR q9xuhrpoly_5p73_sub)) OR (q9xhrpoly_base_nwell OR q9xuhrpoly_base_nwell)) OR (q9xhrpoly_base_sub OR q9xuhrpoly_base_sub)) |
| //POLY_cond_nrc = q2poly NOT ((((q9mrp1 OR pyshort) OR (q9xuhrpoly_base_sub OR q9xuhrpoly_base_nwell)) OR (q9xhrpoly_base_sub OR q9xhrpoly_base_nwell)) OR q4poly) |
| q2poly = q5poly AND q0poly |
| CONNECT POLY_cond POLY_cond_nrc |
| CONNECT poly_pin POLY_cond_nrc |
| //POLY_cond = q5poly NOT (((((((((((((q9mrp1 OR pyshort) OR q4poly) OR q9xhrpoly_0p35_nwell) OR q9xhrpoly_0p69_nwell) OR q9xhrpoly_1p41_nwell) OR q9xhrpoly_2p85_nwell) OR q9xhrpoly_5p73_nwell) OR q9xhrpoly_0p35_sub) OR q9xhrpoly_0p69_sub) OR q9xhrpoly_1p41_sub) OR q9xhrpoly_2p85_sub) OR q9xhrpoly_5p73_sub) OR q0poly) |
| //POLY_cond = q5poly NOT ((((q9mrp1 OR pyshort) OR (q9xuhrpoly_base_sub OR q9xuhrpoly_base_nwell)) OR (q9xhrpoly_base_sub OR q9xhrpoly_base_nwell)) OR (q4poly OR q0poly)) |
| POLY_cond = q5poly NOT (((((((((((((((q9mrp1 OR pyshort) OR q4poly) OR (q9xhrpoly_0p35_nwell OR q9xuhrpoly_0p35_nwell)) OR (q9xhrpoly_0p69_nwell OR q9xuhrpoly_0p69_nwell)) OR (q9xhrpoly_1p41_nwell OR q9xuhrpoly_1p41_nwell)) OR (q9xhrpoly_2p85_nwell OR q9xuhrpoly_2p85_nwell)) OR (q9xhrpoly_5p73_nwell OR q9xuhrpoly_5p73_nwell)) OR (q9xhrpoly_0p35_sub OR q9xuhrpoly_0p35_sub)) OR (q9xhrpoly_0p69_sub OR q9xuhrpoly_0p69_sub)) OR (q9xhrpoly_1p41_sub OR q9xuhrpoly_1p41_sub)) OR (q9xhrpoly_2p85_sub OR q9xuhrpoly_2p85_sub)) OR (q9xhrpoly_5p73_sub OR q9xuhrpoly_5p73_sub)) OR (q9xhrpoly_base_nwell OR q9xuhrpoly_base_nwell)) OR (q9xhrpoly_base_sub OR q9xuhrpoly_base_sub)) OR q0poly) |
| //POLY_cond = q5poly NOT (((((q9mrp1 OR pyshort) OR q4poly) OR (q9xhrpoly_base_nwell OR q9xuhrpoly_base_nwell)) OR (q9xhrpoly_base_sub OR q9xuhrpoly_base_sub)) OR q0poly) |
| CONNECT poly_pin POLY_cond |
| TEXT LAYER polypt ATTACH polypt poly_pin ATTACH polypt POLY_cond ATTACH polypt POLY_cond_nrc |
| TEXT LAYER polytt ATTACH polytt POLY_cond ATTACH polytt POLY_cond_nrc |
| RESISTANCE SHEET POLY_cond [ 48.2 0 ] |
| PARASITIC VARIATION POLY_cond SHEET // deltaW = 0.056000, max error = 0.020000 |
| SPACE > 0 DRAWN_WIDTH >= 0.000000 < 0.155000 VALUE 76.914894 // sheet @ w==0.15 |
| SPACE > 0 DRAWN_WIDTH >= 0.155000 < 0.165000 VALUE 74.153846 // sheet @ w==0.16 |
| SPACE > 0 DRAWN_WIDTH >= 0.165000 < 0.175000 VALUE 71.877193 // sheet @ w==0.17 |
| SPACE > 0 DRAWN_WIDTH >= 0.175000 < 0.185000 VALUE 69.967742 // sheet @ w==0.18 |
| SPACE > 0 DRAWN_WIDTH >= 0.185000 < 0.195000 VALUE 68.343284 // sheet @ w==0.19 |
| SPACE > 0 DRAWN_WIDTH >= 0.195000 < 0.215000 VALUE 66.315436 // sheet @ w==0.205 |
| SPACE > 0 DRAWN_WIDTH >= 0.215000 < 0.235000 VALUE 64.171598 // sheet @ w==0.225 |
| SPACE > 0 DRAWN_WIDTH >= 0.235000 < 0.265000 VALUE 62.113402 // sheet @ w==0.25 |
| SPACE > 0 DRAWN_WIDTH >= 0.265000 < 0.310000 VALUE 59.986900 // sheet @ w==0.285 |
| SPACE > 0 DRAWN_WIDTH >= 0.310000 < 0.375000 VALUE 57.704225 // sheet @ w==0.34 |
| SPACE > 0 DRAWN_WIDTH >= 0.375000 < 0.480000 VALUE 55.615385 // sheet @ w==0.42 |
| SPACE > 0 DRAWN_WIDTH >= 0.480000 < 0.690000 VALUE 53.502947 // sheet @ w==0.565 |
| SPACE > 0 DRAWN_WIDTH >= 0.690000 < 1.275000 VALUE 51.417163 // sheet @ w==0.895 |
| SPACE > 0 DRAWN_WIDTH >= 1.275000 < 2.800000 VALUE 49.408236 // sheet @ w==2.29 |
| q8poly = EXPAND TEXT "?" polytt BY 0.005 PRIMARY ONLY |
| q10poly = COPY poly_pin |
| q6poly = q8poly NOT (SIZE q10poly BY 0.005) |
| q7poly = SIZE q6poly BY 0.005 |
| CONNECT q7poly |
| DEVICE Probe(probe_polytt) q6poly q7poly(probe) POLY_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER polytt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| q4li1 = COPY mrl1 |
| q5li1 = COPY li1 |
| q0li1 = varactor OR |
| (xhrpoly_x_1_device OR |
| (xhrpoly_x_2_device OR |
| (PTAP_pwellres OR |
| (capdrawSz OR |
| (rcxDioESDblk OR |
| (xcmvpp_2RCX OR |
| (capdrawSz_M5 OR |
| (capdrawSz_M4 OR inductor)))))))) |
| LI1_cond_nrc = q2li1 NOT ((q9mrl1 OR lishort) OR q4li1) |
| q2li1 = q5li1 AND q0li1 |
| CONNECT LI1_cond LI1_cond_nrc |
| CONNECT li1_pin LI1_cond_nrc |
| LI1_cond = q5li1 NOT (((q9mrl1 OR lishort) OR q4li1) OR q0li1) |
| CONNECT li1_pin LI1_cond |
| TEXT LAYER li1pt ATTACH li1pt li1_pin ATTACH li1pt LI1_cond ATTACH li1pt LI1_cond_nrc |
| TEXT LAYER li1tt ATTACH li1tt LI1_cond ATTACH li1tt LI1_cond_nrc |
| RESISTANCE SHEET LI1_cond [ 12.2 0 ] |
| PARASITIC VARIATION LI1_cond SHEET // deltaW = -0.017000, max error = 0.020000 |
| SPACE > 0 DRAWN_WIDTH >= 0.000000 < 0.215000 VALUE 11.090909 // sheet @ w==0.17 |
| SPACE > 0 DRAWN_WIDTH >= 0.215000 < 0.450000 VALUE 11.524430 // sheet @ w==0.29 |
| SPACE > 0 DRAWN_WIDTH >= 0.450000 < 0.850000 VALUE 11.960784 // sheet @ w==0.85 |
| q8li1 = EXPAND TEXT "?" li1tt BY 0.005 PRIMARY ONLY |
| q10li1 = COPY li1_pin |
| q6li1 = q8li1 NOT (SIZE q10li1 BY 0.005) |
| q7li1 = SIZE q6li1 BY 0.005 |
| CONNECT q7li1 |
| DEVICE Probe(probe_li1tt) q6li1 q7li1(probe) LI1_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER li1tt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| q4met1 = COPY 4017 |
| q5met1 = met1 OR MET1_waff |
| q0met1 = varactor OR |
| (capdrawSz OR |
| (rcxDioESDblk OR |
| (xcmvpp_2RCX OR |
| (capdrawSz_M5 OR |
| (capdrawSz_M4 OR inductor))))) |
| MET1_cond_nrc = q2met1 NOT (m1short OR q4met1) |
| q2met1 = q5met1 AND q0met1 |
| CONNECT MET1_cond MET1_cond_nrc |
| CONNECT met1_pin MET1_cond_nrc |
| MET1_cond = q5met1 NOT ((m1short OR q4met1) OR q0met1) |
| CONNECT met1_pin MET1_cond |
| TEXT LAYER met1pt ATTACH met1pt met1_pin ATTACH met1pt MET1_cond ATTACH met1pt MET1_cond_nrc |
| TEXT LAYER met1tt ATTACH met1tt MET1_cond ATTACH met1tt MET1_cond_nrc |
| RESISTANCE SHEET MET1_cond [ 0.125 0 ] |
| PARASITIC VARIATION MET1_cond SHEET // deltaW = 0.039000, max error = 0.020000 |
| SPACE > 0 DRAWN_WIDTH >= 0.000000 < 0.145000 VALUE 0.173267 // sheet @ w==0.14 |
| SPACE > 0 DRAWN_WIDTH >= 0.145000 < 0.155000 VALUE 0.168919 // sheet @ w==0.15 |
| SPACE > 0 DRAWN_WIDTH >= 0.155000 < 0.175000 VALUE 0.163690 // sheet @ w==0.165 |
| SPACE > 0 DRAWN_WIDTH >= 0.175000 < 0.195000 VALUE 0.158390 // sheet @ w==0.185 |
| SPACE > 0 DRAWN_WIDTH >= 0.195000 < 0.230000 VALUE 0.153509 // sheet @ w==0.21 |
| SPACE > 0 DRAWN_WIDTH >= 0.230000 < 0.285000 VALUE 0.147569 // sheet @ w==0.255 |
| SPACE > 0 DRAWN_WIDTH >= 0.285000 < 0.380000 VALUE 0.142045 // sheet @ w==0.325 |
| SPACE > 0 DRAWN_WIDTH >= 0.380000 < 0.585000 VALUE 0.136580 // sheet @ w==0.46 |
| SPACE > 0 DRAWN_WIDTH >= 0.585000 < 1.350000 VALUE 0.131282 // sheet @ w==0.815 |
| SPACE > 0 DRAWN_WIDTH >= 1.350000 < 1.950000 VALUE 0.127551 // sheet @ w==1.95 |
| q8met1 = EXPAND TEXT "?" met1tt BY 0.005 PRIMARY ONLY |
| q10met1 = COPY met1_pin |
| q6met1 = q8met1 NOT (SIZE q10met1 BY 0.005) |
| q7met1 = SIZE q6met1 BY 0.005 |
| CONNECT q7met1 |
| DEVICE Probe(probe_met1tt) q6met1 q7met1(probe) MET1_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met1tt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| q4met2 = COPY 4018 |
| q5met2 = met2 OR MET2_waff |
| q0met2 = varactor OR |
| (capdrawSz OR |
| (rcxDioESDblk OR |
| (xcmvpp_2RCX OR |
| (capdrawSz_M5 OR |
| (capdrawSz_M4 OR inductor))))) |
| MET2_cond_nrc = q2met2 NOT (m2short OR q4met2) |
| q2met2 = q5met2 AND q0met2 |
| CONNECT MET2_cond MET2_cond_nrc |
| CONNECT met2_pin MET2_cond_nrc |
| MET2_cond = q5met2 NOT ((m2short OR q4met2) OR q0met2) |
| CONNECT met2_pin MET2_cond |
| TEXT LAYER met2pt ATTACH met2pt met2_pin ATTACH met2pt MET2_cond ATTACH met2pt MET2_cond_nrc |
| TEXT LAYER met2tt ATTACH met2tt MET2_cond ATTACH met2tt MET2_cond_nrc |
| RESISTANCE SHEET MET2_cond [ 0.125 0 ] |
| PARASITIC VARIATION MET2_cond SHEET // deltaW = 0.039000, max error = 0.020000 |
| SPACE > 0 DRAWN_WIDTH >= 0.000000 < 0.145000 VALUE 0.173267 // sheet @ w==0.14 |
| SPACE > 0 DRAWN_WIDTH >= 0.145000 < 0.155000 VALUE 0.168919 // sheet @ w==0.15 |
| SPACE > 0 DRAWN_WIDTH >= 0.155000 < 0.175000 VALUE 0.163690 // sheet @ w==0.165 |
| SPACE > 0 DRAWN_WIDTH >= 0.175000 < 0.195000 VALUE 0.158390 // sheet @ w==0.185 |
| SPACE > 0 DRAWN_WIDTH >= 0.195000 < 0.230000 VALUE 0.153509 // sheet @ w==0.21 |
| SPACE > 0 DRAWN_WIDTH >= 0.230000 < 0.285000 VALUE 0.147569 // sheet @ w==0.255 |
| SPACE > 0 DRAWN_WIDTH >= 0.285000 < 0.380000 VALUE 0.142045 // sheet @ w==0.325 |
| SPACE > 0 DRAWN_WIDTH >= 0.380000 < 0.585000 VALUE 0.136580 // sheet @ w==0.46 |
| SPACE > 0 DRAWN_WIDTH >= 0.585000 < 1.350000 VALUE 0.131282 // sheet @ w==0.815 |
| SPACE > 0 DRAWN_WIDTH >= 1.350000 < 1.950000 VALUE 0.127551 // sheet @ w==1.95 |
| q8met2 = EXPAND TEXT "?" met2tt BY 0.005 PRIMARY ONLY |
| q10met2 = COPY met2_pin |
| q6met2 = q8met2 NOT (SIZE q10met2 BY 0.005) |
| q7met2 = SIZE q6met2 BY 0.005 |
| CONNECT q7met2 |
| DEVICE Probe(probe_met2tt) q6met2 q7met2(probe) MET2_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met2tt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| q4met3 = COPY 4019 |
| q5met3 = met3 OR MET3_waff |
| q0met3_a = capdrawSz_tmp2 OR |
| (capdrawSz_M5 OR |
| (capdrawSz_M4 OR inductor)) |
| q0met3 = q0met3_a OR capm |
| //q0met3 = capdrawSz_tmp2 OR ((capdrawSz_M5 OR capm) (capdrawSz_M4 OR inductor)) |
| MET3_cond_nrc = q2met3 NOT (m3short OR q4met3) |
| q2met3 = q5met3 AND q0met3 |
| CONNECT MET3_cond MET3_cond_nrc |
| CONNECT met3_pin MET3_cond_nrc |
| MET3_cond = q5met3 NOT ((m3short OR q4met3) OR q0met3) |
| CONNECT met3_pin MET3_cond |
| TEXT LAYER met3pt ATTACH met3pt met3_pin ATTACH met3pt MET3_cond ATTACH met3pt MET3_cond_nrc |
| TEXT LAYER met3tt ATTACH met3tt MET3_cond ATTACH met3tt MET3_cond_nrc |
| RESISTANCE SHEET MET3_cond [ 0.047 0 ] |
| PARASITIC VARIATION MET3_cond SHEET // deltaW = 0.025000, max error = 0.020000 |
| SPACE > 0 DRAWN_WIDTH >= 0.000000 < 0.380000 VALUE 0.051273 // sheet @ w==0.3 |
| SPACE > 0 DRAWN_WIDTH >= 0.380000 < 0.900000 VALUE 0.049304 // sheet @ w==0.535 |
| SPACE > 0 DRAWN_WIDTH >= 0.900000 < 1.250000 VALUE 0.047959 // sheet @ w==1.25 |
| q8met3 = EXPAND TEXT "?" met3tt BY 0.005 PRIMARY ONLY |
| q10met3 = COPY met3_pin |
| q6met3 = q8met3 NOT (SIZE q10met3 BY 0.005) |
| q7met3 = SIZE q6met3 BY 0.005 |
| CONNECT q7met3 |
| DEVICE Probe(probe_met3tt) q6met3 q7met3(probe) MET3_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met3tt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| q4met4 = COPY 4020 |
| q5met4 = COPY met4 |
| q0met4_a = capdrawSz_M5 OR |
| (capdrawSz_M4 OR inductor) |
| q0met4 = q0met4_a OR cap2m |
| MET4_cond_nrc = q2met4 NOT ((m4short OR m4fuse) OR q4met4) |
| q2met4 = q5met4 AND q0met4 |
| CONNECT MET4_cond MET4_cond_nrc |
| CONNECT met4_pin MET4_cond_nrc |
| MET4_cond = q5met4 NOT (((m4short OR m4fuse) OR q4met4) OR q0met4) |
| CONNECT met4_pin MET4_cond |
| TEXT LAYER met4pt ATTACH met4pt met4_pin ATTACH met4pt MET4_cond ATTACH met4pt MET4_cond_nrc |
| TEXT LAYER met4tt ATTACH met4tt MET4_cond ATTACH met4tt MET4_cond_nrc |
| RESISTANCE SHEET MET4_cond [ 0.047 0 ] |
| PARASITIC VARIATION MET4_cond SHEET // deltaW = 0.025000, max error = 0.020000 |
| SPACE > 0 DRAWN_WIDTH >= 0.000000 < 0.380000 VALUE 0.051273 // sheet @ w==0.3 |
| SPACE > 0 DRAWN_WIDTH >= 0.380000 < 0.900000 VALUE 0.049304 // sheet @ w==0.535 |
| SPACE > 0 DRAWN_WIDTH >= 0.900000 < 1.250000 VALUE 0.047959 // sheet @ w==1.25 |
| q8met4 = EXPAND TEXT "?" met4tt BY 0.005 PRIMARY ONLY |
| q10met4 = COPY met4_pin |
| q6met4 = q8met4 NOT (SIZE q10met4 BY 0.005) |
| q7met4 = SIZE q6met4 BY 0.005 |
| CONNECT q7met4 |
| DEVICE Probe(probe_met4tt) q6met4 q7met4(probe) MET4_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met4tt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| q4met5 = COPY 4021 |
| q5met5 = COPY met5 |
| q0met5 = capdrawSz_M5_noshrink OR |
| (capdrawSz_M4 OR inductor) |
| MET5_cond_nrc = q2met5 NOT (m5short OR q4met5) |
| q2met5 = q5met5 AND q0met5 |
| CONNECT MET5_cond MET5_cond_nrc |
| CONNECT met5_pin MET5_cond_nrc |
| MET5_cond = q5met5 NOT ((m5short OR q4met5) OR q0met5) |
| CONNECT met5_pin MET5_cond |
| TEXT LAYER met5pt ATTACH met5pt met5_pin ATTACH met5pt MET5_cond ATTACH met5pt MET5_cond_nrc |
| TEXT LAYER met5tt ATTACH met5tt MET5_cond ATTACH met5tt MET5_cond_nrc |
| RESISTANCE SHEET MET5_cond [ 0.0285 0 ] |
| PARASITIC VARIATION MET5_cond SHEET // deltaW = 0.090000, max error = 0.020000 |
| SPACE > 0 DRAWN_WIDTH >= 0.000000 < 2.405000 VALUE 0.030199 // sheet @ w==1.6 |
| SPACE > 0 DRAWN_WIDTH >= 2.405000 < 4.500000 VALUE 0.029082 // sheet @ w==4.5 |
| q8met5 = EXPAND TEXT "?" met5tt BY 0.005 PRIMARY ONLY |
| q10met5 = COPY met5_pin |
| q6met5 = q8met5 NOT (SIZE q10met5 BY 0.005) |
| q7met5 = SIZE q6met5 BY 0.005 |
| CONNECT q7met5 |
| DEVICE Probe(probe_met5tt) q6met5 q7met5(probe) MET5_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER met5tt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| q4pad = COPY 4022 |
| q5pad = COPY pad |
| PAD_cond = q5pad NOT q4pad |
| CONNECT pad_pin PAD_cond |
| TEXT LAYER padpt ATTACH padpt pad_pin ATTACH padpt PAD_cond |
| TEXT LAYER padtt ATTACH padtt PAD_cond |
| RESISTANCE SHEET PAD_cond [ 0.0 0 ] |
| q8pad = EXPAND TEXT "?" padtt BY 0.005 PRIMARY ONLY |
| q10pad = COPY pad_pin |
| q6pad = q8pad NOT (SIZE q10pad BY 0.005) |
| q7pad = SIZE q6pad BY 0.005 |
| CONNECT q7pad |
| DEVICE Probe(probe_padtt) q6pad q7pad(probe) PAD_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER padtt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| q4rdl = COPY 4023 |
| q5rdl = COPY rdl |
| q0rdl = COPY inductor |
| RDL_cond_nrc = q2rdl NOT (rdshort OR q4rdl) |
| q2rdl = q5rdl AND q0rdl |
| CONNECT RDL_cond RDL_cond_nrc |
| CONNECT rdl_pin RDL_cond_nrc |
| RDL_cond = q5rdl NOT ((rdshort OR q4rdl) OR q0rdl) |
| CONNECT rdl_pin RDL_cond |
| TEXT LAYER rdlpt ATTACH rdlpt rdl_pin ATTACH rdlpt RDL_cond ATTACH rdlpt RDL_cond_nrc |
| TEXT LAYER rdltt ATTACH rdltt RDL_cond ATTACH rdltt RDL_cond_nrc |
| RESISTANCE SHEET RDL_cond [ 0.005 0 ] |
| q8rdl = EXPAND TEXT "?" rdltt BY 0.005 PRIMARY ONLY |
| q10rdl = COPY rdl_pin |
| q6rdl = q8rdl NOT (SIZE q10rdl BY 0.005) |
| q7rdl = SIZE q6rdl BY 0.005 |
| CONNECT q7rdl |
| DEVICE Probe(probe_rdltt) q6rdl q7rdl(probe) RDL_cond(conductor) BY NET NETLIST ELEMENT "p" TEXT MODEL LAYER rdltt [ |
| PROPERTY probeType |
| probeType = 1 |
| ] |
| |
| |
| contactLicon1 = licon1 INSIDE MOSDIFFnotPOLY |
| sizeupLicon1 = SIZE contactLicon1 BY 0.11 INSIDE OF MOSDIFFnotPOLY STEP 0.19 |
| gateEdgeBlock = poly COINCIDENT OUTSIDE EDGE sizeupLicon1 |
| q0gateEdgeBlock = EXPAND EDGE gateEdgeBlock BY 0.001 |
| q0POLY_gshield_low = q9mrp1 OR |
| (pyshort OR |
| (q9xhrpoly_0p35_nwell OR |
| (q9xhrpoly_0p69_nwell OR |
| (q9xhrpoly_1p41_nwell OR |
| (q9xhrpoly_2p85_nwell OR |
| (q9xhrpoly_5p73_nwell OR |
| (q9xhrpoly_0p35_sub OR |
| (q9xhrpoly_0p69_sub OR |
| (q9xhrpoly_1p41_sub OR |
| (q9xhrpoly_2p85_sub OR |
| (q9xhrpoly_5p73_sub OR |
| (q9xuhrpoly_base_nwell OR |
| (q9xuhrpoly_base_sub OR |
| (q9xhrpoly_base_sub OR q9xhrpoly_base_nwell)))))))))))))) |
| q1POLY_gshield_low = SIZE q0POLY_gshield_low BY 0.001 |
| POLY_gshield_low = q1POLY_gshield_low OR q0gateEdgeBlock |
| CONNECT POLY_gshield_low |
| CAPACITANCE NEARBODY POLY_cond INSIDE OF POLY_gshield_low [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| POLY_gshield_upp = COPY POLY_gshield_low |
| q0Li1capacitorEdgeBlock = EXPAND EDGE Li1capacitorEdgeBlock BY 0.001 |
| q0LI1_gshield_low = q9mrl1 OR lishort |
| q1LI1_gshield_low = SIZE q0LI1_gshield_low BY 0.001 |
| LI1_gshield_low = q1LI1_gshield_low OR q0Li1capacitorEdgeBlock |
| CONNECT LI1_gshield_low |
| CAPACITANCE NEARBODY LI1_cond INSIDE OF LI1_gshield_low [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| LI1_gshield_upp = COPY LI1_gshield_low |
| Li1capacitorEdgeBlock = li1 INSIDE EDGE all_capdrawSz |
| Met1capacitorEdgeBlock = met1 INSIDE EDGE all_capdrawSz |
| Met2capacitorEdgeBlock = met2 INSIDE EDGE all_capdrawSz |
| Met3capacitorEdgeBlock = met3 INSIDE EDGE all_capdrawSz |
| Met4capacitorEdgeBlock = met4 INSIDE EDGE all_capdrawSz |
| Met5capacitorEdgeBlock = met5 INSIDE EDGE (all_capdrawSz NOT (SIZE cap140fF_7 BY 0.005)) |
| RdlcapacitorEdgeBlock = rdl INSIDE EDGE all_capdrawSz |
| q0Met1capacitorEdgeBlock = EXPAND EDGE Met1capacitorEdgeBlock BY 0.001 |
| q0MET1_gshield_low = COPY m1short |
| q1MET1_gshield_low = SIZE q0MET1_gshield_low BY 0.001 |
| MET1_gshield_low = q1MET1_gshield_low OR q0Met1capacitorEdgeBlock |
| CONNECT MET1_gshield_low |
| CAPACITANCE NEARBODY MET1_cond INSIDE OF MET1_gshield_low [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| MET1_gshield_upp = COPY MET1_gshield_low |
| q0Met2capacitorEdgeBlock = EXPAND EDGE Met2capacitorEdgeBlock BY 0.001 |
| q0MET2_gshield_low = COPY m2short |
| q1MET2_gshield_low = SIZE q0MET2_gshield_low BY 0.001 |
| MET2_gshield_low = q1MET2_gshield_low OR q0Met2capacitorEdgeBlock |
| CONNECT MET2_gshield_low |
| CAPACITANCE NEARBODY MET2_cond INSIDE OF MET2_gshield_low [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| MET2_gshield_upp = COPY MET2_gshield_low |
| q0Met3capacitorEdgeBlock = EXPAND EDGE Met3capacitorEdgeBlock BY 0.001 |
| q0MET3_gshield_low = COPY m3short |
| q1MET3_gshield_low = SIZE q0MET3_gshield_low BY 0.001 |
| MET3_gshield_low = q1MET3_gshield_low OR q0Met3capacitorEdgeBlock |
| CONNECT MET3_gshield_low |
| CAPACITANCE NEARBODY MET3_cond INSIDE OF MET3_gshield_low [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| MET3_gshield_upp = COPY MET3_gshield_low |
| q0Met4capacitorEdgeBlock = EXPAND EDGE Met4capacitorEdgeBlock BY 0.001 |
| q0MET4_gshield_low = m4short OR m4fuse |
| q1MET4_gshield_low = SIZE q0MET4_gshield_low BY 0.001 |
| MET4_gshield_low = q1MET4_gshield_low OR q0Met4capacitorEdgeBlock |
| CONNECT MET4_gshield_low |
| CAPACITANCE NEARBODY MET4_cond INSIDE OF MET4_gshield_low [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| MET4_gshield_upp = COPY MET4_gshield_low |
| q0Met5capacitorEdgeBlock = EXPAND EDGE Met5capacitorEdgeBlock BY 0.001 |
| q0MET5_gshield_low = COPY m5short |
| q1MET5_gshield_low = SIZE q0MET5_gshield_low BY 0.001 |
| MET5_gshield_low = q1MET5_gshield_low OR q0Met5capacitorEdgeBlock |
| CONNECT MET5_gshield_low |
| CAPACITANCE NEARBODY MET5_cond INSIDE OF MET5_gshield_low [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| MET5_gshield_upp = COPY MET5_gshield_low |
| q0RdlcapacitorEdgeBlock = EXPAND EDGE RdlcapacitorEdgeBlock BY 0.001 |
| q0RDL_gshield_low = COPY rdshort |
| q1RDL_gshield_low = SIZE q0RDL_gshield_low BY 0.001 |
| RDL_gshield_low = q1RDL_gshield_low OR q0RdlcapacitorEdgeBlock |
| CONNECT RDL_gshield_low |
| CAPACITANCE NEARBODY RDL_cond INSIDE OF RDL_gshield_low [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| RDL_gshield_upp = COPY RDL_gshield_low |
| q1GATE_shield = SIZE ((SIZE allGate BY 0.056 INSIDE OF diff) AND LI1_cond) BY 0.001 |
| CAPACITANCE NEARBODY LI1_cond INSIDE OF GATE_shield [ |
| PROPERTY C |
| max_distance = 0.055 |
| C = 0 |
| ] |
| |
| CAPACITANCE NEARBODY LI1_cond POLY_cond INSIDE OF GATE_shield [ |
| PROPERTY C |
| max_distance = 0.055 |
| C = 0 |
| ] |
| |
| GATE_shield = allGate OR q1GATE_shield |
| CONNECT GATE_shield |
| CAPACITANCE CROSSOVER PLATE POLY_cond GATE_shield [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| CAPACITANCE INTRINSIC FRINGE POLY_cond INSIDE OF GATE_shield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAP3_Well_cont = BulkTermCap_cond AND nwell |
| CAP3_NoWell_cont = BulkTermCap_cond NOT nwell |
| CAP3_WellMos_cont = (poly AND BulkTermCapMos_cond) AND nwell |
| CAP3_NoWellMos_cont = (poly AND BulkTermCapMos_cond) NOT nwell |
| CAP3_Well_contVpp = ((BulkTermCap_condVpp_M4 OR BulkTermCap_condVpp_M5) OR BulkTermCap_condVpp) AND nwell |
| CAP3_NoWell_contVpp = ((BulkTermCap_condVpp_M4 OR BulkTermCap_condVpp_M5) OR BulkTermCap_condVpp) NOT nwell |
| PTAP_pnp_cont = COPY PTAP_pnp_cond |
| PTAP_npn_cont = COPY PTAP_npn_cond |
| PTAP_defet20_cont = COPY nfetExtDr20isolocalBody |
| PTAP_notbjt_cont = COPY PTAP_notbjt_cond |
| PTAP_NotDnwell_cont = COPY PTAP_NotDnwell_cond |
| NTAP_pnp_cont = NTAP_pnp_cond AND nwell |
| NTAP_npn_cont = NTAP_npn_cond AND nwell |
| NTAP_notbjt_cont = NTAP_notbjt_cond AND nwell |
| DNWELL_cont = DNWELL_cond AND nwell |
| licon1_PDIFF = PDIFF_cond AND licon1 |
| licon1_NDIFF = NDIFF_cond AND licon1 |
| licon1_PNPDIFF = PNPDIFF_cond AND licon1 |
| licon1_NPNDIFF = NPNDIFF_cond AND licon1 |
| licon1_NTAP_pnp = NTAP_pnp_cond AND licon1 |
| licon1_NTAP_npn = NTAP_npn_cond AND licon1 |
| licon1_NTAP_notbjt = NTAP_notbjt_cond AND licon1 |
| licon1_PTAP_pnp = PTAP_pnp_cond AND licon1 |
| licon1_PTAP_npn = PTAP_npn_cond AND licon1 |
| licon1_PTAP_defet20 = PTAP_defet20_cond AND licon1 |
| licon1_PTAP_notbjt = PTAP_notbjt_cond AND licon1 |
| licon1_PTAP_notDnwell = PTAP_NotDnwell_cond AND licon1 |
| licon1_POLY = (POLY_cond OR POLY_cond_nrc) AND (licon1 AND npc) |
| rdl_MET5 = MET5_cond AND rdlcon |
| NFOM_cond = NDIFF_cond OR |
| (NTAP_pnp_cond OR |
| (NTAP_npn_cond OR |
| (NTAP_notbjt_cond OR |
| (NPNDIFF_cond OR FOM_waff)))) |
| PFOM_cond = PDIFF_cond OR |
| (PTAP_pnp_cond OR |
| (PTAP_defet20_cond OR |
| (PTAP_npn_cond OR |
| (PTAP_notbjt_cond OR |
| (PNPDIFF_cond OR PTAP_NotDnwell_cond))))) |
| |
| PDIFF_cond_vhv = AND PDIFF_COND (AND uhvi EXTDRAIN20) |
| NDIFF_cond_vhv = AND NDIFF_COND (AND uhvi EXTDRAIN20) |
| CONNECT PDIFF_cond_vhv LI1_cond BY licon1 |
| CONNECT NDIFF_cond_vhv LI1_cond BY licon1 |
| #IFDEF PEX |
| PEX IGNORE RESISTANCE VIA PDIFF_cond_vhv LI1_cond |
| PEX IGNORE RESISTANCE VIA NDIFF_cond_vhv LI1_cond |
| #ENDIF //PEX |
| |
| CONNECT MET2_cond_nrc vppTermpoly |
| CONNECT MET2_cond_nrc vppTermNopoly |
| CONNECT MET2_cond_nrc vppTermli1 |
| CONNECT MET2_cond_nrc vppTermNoli1 |
| CONNECT MET2_cond_nrc vppTermBB |
| CONNECT MET2_cond_nrc vppTermBBMos |
| CONNECT MET3_cond_nrc vppTermli1_M5_noM4 |
| CONNECT MET3_cond_nrc vppTermM1_M5_noM4 |
| CONNECT MET3_cond topMetVpp |
| CONNECT MET3_cond_nrc vppTermpoly_M4 |
| CONNECT MET3_cond_nrc vppTermNopoly_M4 |
| CONNECT MET3_cond_nrc vppTermli1_M4 |
| CONNECT MET3_cond_nrc vppTermli1_M4 |
| CONNECT MET3_cond_nrc vppTermM1_M4 |
| CONNECT MET4_cond_nrc topMetVpp_M4 |
| CONNECT MET4_cond_nrc vppTermpoly_M5 |
| CONNECT MET4_cond_nrc vppTermNopoly_M5 |
| CONNECT MET4_cond_nrc vppTermli1_M5 |
| CONNECT MET4_cond_nrc vppTermM1_M5 |
| CONNECT MET4_cond_nrc vppTerm_classN |
| CONNECT MET5_cond_nrc topMetVpp_M5 |
| CONNECT MET5_cond topMetVpp_M5_shrunk |
| CONNECT MET5_cond rdl_MET5 |
| CONNECT RDL_cond rdlcon |
| CONNECT RDL_cond_nrc ind4T1_rdl |
| CONNECT RDL_cond_nrc ind4T2_rdl |
| CONNECT RDL_cond_nrc ind4Center_rdl |
| CONNECT MET5_cond_nrc ind4Center_met5 |
| CONNECT MET5_cond_nrc ind4T1_met5 |
| CONNECT MET5_cond_nrc ind4T2_met5 |
| CONNECT MET3_cond_nrc ind4Center_met3 |
| CONNECT MET1_cond_nrc ind4Shield |
| CONNECT MET5_cond_nrc balunT1 |
| CONNECT MET5_cond_nrc balunT2 |
| CONNECT RDL_cond_nrc balunT3 |
| CONNECT RDL_cond_nrc balunT4 |
| CONNECT MET5_cond_nrc balunCenter |
| CONNECT MET1_cond_nrc balunShield |
| CONNECT BulkTermCap_cond Substrate BY CAP3_NoWell_cont |
| CONNECT BulkTermCap_cond MosNwell BY CAP3_Well_cont |
| CONNECT BulkTermCap_cond PnpNwell BY CAP3_Well_cont |
| CONNECT BulkTermCap_cond NpnNwell BY CAP3_Well_cont |
| CONNECT BulkTermCapMos_cond POLY_cond_nrc BY CAP3_NoWellMos_cont |
| CONNECT BulkTermCapMos_cond POLY_cond_nrc BY CAP3_WellMos_cont |
| CONNECT BulkTermCap_condVpp Substrate BY CAP3_NoWell_contVpp |
| CONNECT BulkTermCap_condVpp MosNwell BY CAP3_Well_contVpp |
| CONNECT BulkTermCap_condVpp PnpNwell BY CAP3_Well_contVpp |
| CONNECT BulkTermCap_condVpp NpnNwell BY CAP3_Well_contVpp |
| CONNECT BulkTermCap_condVpp_M5 Substrate BY CAP3_NoWell_contVpp |
| CONNECT BulkTermCap_condVpp_M5 MosNwell BY CAP3_Well_contVpp |
| CONNECT BulkTermCap_condVpp_M5 PnpNwell BY CAP3_Well_contVpp |
| CONNECT BulkTermCap_condVpp_M5 NpnNwell BY CAP3_Well_contVpp |
| CONNECT BulkTermCap_condVpp_M4 Substrate BY CAP3_NoWell_contVpp |
| CONNECT BulkTermCap_condVpp_M4 MosNwell BY CAP3_Well_contVpp |
| CONNECT BulkTermCap_condVpp_M4 PnpNwell BY CAP3_Well_contVpp |
| CONNECT BulkTermCap_condVpp_M4 NpnNwell BY CAP3_Well_contVpp |
| CONNECT Substrate SubstrateIso |
| CONNECT PTAP_pnp_cond Substrate BY PTAP_pnp_cont |
| CONNECT PTAP_npn_cond Substrate BY PTAP_npn_cont |
| CONNECT PTAP_defet20_cond nfetExtDr20isolocalBody BY PTAP_defet20_cont |
| CONNECT PTAP_notbjt_cond Substrate BY PTAP_notbjt_cont |
| CONNECT PTAP_NotDnwell_cond Substrate BY PTAP_NotDnwell_cont |
| CONNECT NTAP_pnp_cond PnpNwell BY NTAP_pnp_cont |
| CONNECT NTAP_npn_cond NpnNwell BY NTAP_npn_cont |
| CONNECT NTAP_notbjt_cond MosNwell BY NTAP_notbjt_cont |
| CONNECT MosNwell DNWELL_cond BY DNWELL_cont |
| CONNECT MosNwell pwresBiasTerm_cond |
| CONNECT NFOM_cond NDIFF_cond |
| CONNECT NFOM_cond NTAP_pnp_cond |
| CONNECT NFOM_cond NTAP_notbjt_cond |
| CONNECT PFOM_cond PDIFF_cond |
| CONNECT PFOM_cond PTAP_pnp_cond |
| CONNECT PFOM_cond PTAP_notbjt_cond |
| CONNECT PFOM_cond PTAP_NotDnwell_cond |
| CONNECT LI1_cond_nrc NDIFF_cond BY licon1_NDIFF |
| CONNECT LI1_cond NDIFF_cond BY licon1_NDIFF |
| RESISTANCE CONNECTION LI1_cond NDIFF_cond [ 5.2598 0 ] |
| CONNECT LI1_cond_nrc PDIFF_cond BY licon1_PDIFF |
| CONNECT LI1_cond PDIFF_cond BY licon1_PDIFF |
| RESISTANCE CONNECTION LI1_cond PDIFF_cond [ 17.34 0 ] |
| CONNECT LI1_cond NTAP_pnp_cond BY licon1_NTAP_pnp |
| CONNECT LI1_cond NTAP_npn_cond BY licon1_NTAP_npn |
| CONNECT LI1_cond PTAP_pnp_cond BY licon1_PTAP_pnp |
| CONNECT LI1_cond PTAP_npn_cond BY licon1_PTAP_npn |
| CONNECT LI1_cond PTAP_defet20_cond BY licon1_PTAP_defet20 |
| CONNECT LI1_cond PTAP_NotDnwell_cond BY licon1_PTAP_notDnwell |
| CONNECT LI1_cond_nrc NTAP_notbjt_cond BY licon1_NTAP_notbjt |
| CONNECT LI1_cond NTAP_notbjt_cond BY licon1_NTAP_notbjt |
| RESISTANCE CONNECTION LI1_cond NTAP_notbjt_cond [ 5.2598 0 ] |
| CONNECT LI1_cond_nrc PTAP_notbjt_cond BY licon1_PTAP_notbjt |
| CONNECT LI1_cond PTAP_notbjt_cond BY licon1_PTAP_notbjt |
| RESISTANCE CONNECTION LI1_cond PTAP_notbjt_cond [ 17.34 0 ] |
| CONNECT LI1_cond PNPDIFF_cond BY licon1_PNPDIFF |
| CONNECT LI1_cond NPNDIFF_cond BY licon1_NPNDIFF |
| CONNECT LI1_cond_nrc POLY_cond_nrc BY licon1_POLY |
| CONNECT LI1_cond_nrc POLY_cond BY licon1_POLY |
| CONNECT LI1_cond POLY_cond_nrc BY licon1_POLY |
| CONNECT LI1_cond POLY_cond BY licon1_POLY |
| RESISTANCE CONNECTION LI1_cond POLY_cond [ 4.198592 0 ] |
| CONNECT MET1_cond_nrc LI1_cond_nrc BY mcon |
| CONNECT MET1_cond_nrc LI1_cond BY mcon |
| CONNECT MET1_cond LI1_cond_nrc BY mcon |
| CONNECT MET1_cond LI1_cond BY mcon |
| RESISTANCE CONNECTION MET1_cond LI1_cond [ 0.26877 0 ] |
| CONNECT MET2_cond_nrc MET1_cond_nrc BY via |
| CONNECT MET2_cond_nrc MET1_cond BY via |
| CONNECT MET2_cond MET1_cond_nrc BY via |
| CONNECT MET2_cond MET1_cond BY via |
| RESISTANCE CONNECTION MET2_cond MET1_cond [ 0.10125 0 ] |
| CONNECT MET3_cond_nrc MET2_cond_nrc BY via2 |
| CONNECT MET3_cond_nrc MET2_cond BY via2 |
| CONNECT MET3_cond MET2_cond_nrc BY via2 |
| CONNECT MET3_cond MET2_cond BY via2 |
| RESISTANCE CONNECTION MET3_cond MET2_cond [ 0.1364 0 ] |
| CONNECT MET4_cond_nrc MET3_cond_nrc BY via3_notcapm |
| CONNECT MET4_cond_nrc MET3_cond BY via3_notcapm |
| CONNECT MET4_cond MET3_cond_nrc BY via3_notcapm |
| CONNECT MET4_cond MET3_cond BY via3_notcapm |
| //CONNECT MET4_cond_nrc MET3_cond_nrc BY via3 |
| //CONNECT MET4_cond_nrc MET3_cond BY via3 |
| //CONNECT MET4_cond MET3_cond_nrc BY via3 |
| //CONNECT MET4_cond MET3_cond BY via3 |
| RESISTANCE CONNECTION MET4_cond MET3_cond [ 0.1364 0 ] |
| CONNECT MET4_cond_nrc capm_cond BY capmvia3 |
| CONNECT MET4_cond capm_cond BY capmvia3 |
| CONNECT MET5_cond MET4_cond_nrc BY via4_notcap2m |
| CONNECT MET5_cond MET4_cond BY via4_notcap2m |
| MET5_cond_nrc_temp = MET5_cond_nrc NOT inductor |
| MET4_cond_nrc_temp = MET4_cond_nrc NOT inductor |
| CONNECT MET5_cond_nrc_temp MET5_cond_nrc |
| CONNECT MET4_cond_nrc_temp MET4_cond_nrc |
| CONNECT MET5_cond_nrc_temp MET4_cond_nrc_temp BY via4_notcap2m |
| CONNECT MET5_cond_nrc_temp MET4_cond BY via4_notcap2m |
| CONNECT MET5_cond MET4_cond_nrc_temp BY via4_notcap2m |
| CONNECT MET5_cond MET4_cond BY via4_notcap2m |
| CONNECT MET5_cond_nrc cap2m_cond BY via4_notcap2m |
| |
| // ;ss this is wrong |
| // CONNECT MET5_cond cap2m_cond BY capmvia3 |
| CONNECT MET5_cond cap2m_cond BY cap2mvia4 |
| |
| RESISTANCE CONNECTION MET5_cond MET4_cond [ 0.2432 0 ] |
| CONNECT RDL_cond MET5_rdl BY rdl_MET5 |
| RESISTANCE CONNECTION RDL_cond MET5_rdl [ 0.116 0 ] |
| CONNECT RDL_cond MET5_cond BY rdlcon |
| RESISTANCE CONNECTION RDL_cond MET5_cond [ 0.116 0 ] |
| CONNECT PAD_cond MET5_cond |
| |
| // ;ss I think this is obsolete |
| |
| LI1shield = COPY 4024 |
| LI1_plate = LI1shield OR all_capdrawSz |
| LI1_cshield = COPY LI1_plate |
| CONNECT LI1_cshield |
| CAPACITANCE CROSSOVER PLATE LI1_cond LI1_cshield [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| CAPACITANCE INTRINSIC FRINGE LI1_cond INSIDE OF LI1_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| MET1shield = COPY 4025 |
| MET1_plate = MET1shield OR all_capdrawSz |
| MET1_cshield = COPY MET1_plate |
| CONNECT MET1_cshield |
| CAPACITANCE CROSSOVER PLATE MET1_cond MET1_cshield [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| CAPACITANCE INTRINSIC FRINGE MET1_cond INSIDE OF MET1_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| MET2shield = COPY 4026 |
| MET2_plate = MET2shield OR all_capdrawSz |
| MET2_cshield = COPY MET2_plate |
| CONNECT MET2_cshield |
| CAPACITANCE CROSSOVER PLATE MET2_cond MET2_cshield [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| CAPACITANCE INTRINSIC FRINGE MET2_cond INSIDE OF MET2_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| MET3shield = COPY 4027 |
| MET3_plate = MET3shield OR all_capdrawSz |
| MET3_cshield = COPY MET3_plate |
| CONNECT MET3_cshield |
| CAPACITANCE CROSSOVER PLATE MET3_cond MET3_cshield [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| CAPACITANCE INTRINSIC FRINGE MET3_cond INSIDE OF MET3_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| MET4shield = COPY 4028 |
| MET4_plate = MET4shield OR all_capdrawSz |
| MET4_cshield = COPY MET4_plate |
| CONNECT MET4_cshield |
| CAPACITANCE CROSSOVER PLATE MET4_cond MET4_cshield [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| CAPACITANCE INTRINSIC FRINGE MET4_cond INSIDE OF MET4_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| MET5_shield = COPY 4029 |
| MET5_plate = (all_capdrawSz NOT (SIZE cap140fF_7 BY 0.165)) OR (SIZE cap140fF_7 BY -0.235) |
| MET5_cshield = COPY MET5_plate |
| CONNECT MET5_cshield |
| CAPACITANCE CROSSOVER PLATE MET5_cond MET5_cshield [ |
| PROPERTY C |
| max_width = 0.01 |
| max_distance = 0.01 |
| C = 0 |
| ] |
| |
| CAPACITANCE INTRINSIC FRINGE MET5_cond INSIDE OF MET5_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE LI1_cond POLY_cond INSIDE OF LI1_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET5_cond POLY_cond INSIDE OF MET5_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET5_cond LI1_cond INSIDE OF MET5_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET5_cond MET1_cond INSIDE OF MET5_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET5_cond MET2_cond INSIDE OF MET5_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET5_cond MET3_cond INSIDE OF MET5_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET5_cond MET4_cond INSIDE OF MET5_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET4_cond POLY_cond INSIDE OF MET4_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET4_cond LI1_cond INSIDE OF MET4_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET4_cond MET1_cond INSIDE OF MET4_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET4_cond MET2_cond INSIDE OF MET4_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET4_cond MET3_cond INSIDE OF MET4_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET3_cond POLY_cond INSIDE OF MET3_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET3_cond LI1_cond INSIDE OF MET3_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET3_cond MET1_cond INSIDE OF MET3_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET3_cond MET2_cond INSIDE OF MET3_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET2_cond POLY_cond INSIDE OF MET2_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET2_cond LI1_cond INSIDE OF MET2_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET2_cond MET1_cond INSIDE OF MET2_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET1_cond POLY_cond INSIDE OF MET1_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE CROSSOVER FRINGE MET1_cond LI1_cond INSIDE OF MET1_cshield [ |
| PROPERTY C |
| C = 0 |
| ] |
| |
| CAPACITANCE ORDER Substrate SubstrateIso MosNwell PnpNwell NpnNwell NFOM_cond PFOM_cond GATE_shield POLY_gshield_low POLY_cond POLY_gshield_upp LI1_cshield LI1_gshield_low LI1_cond LI1_gshield_upp MET1_cshield MET1_gshield_low MET1_cond MET1_gshield_upp MET2_cshield MET2_gshield_low MET2_cond MET2_gshield_upp MET3_cshield MET3_gshield_low MET3_cond MET3_gshield_upp MET4_cshield MET4_gshield_low MET4_cond MET4_gshield_upp MET5_cshield MET5_gshield_low MET5_cond MET5_gshield_upp RDL_gshield_low RDL_cond RDL_gshield_upp |
| |
| // ;ss dnwell diodes added to match lvsRules |
| |
| PTAPnotSeal = PTAP NOT SEALID |
| PTAPnotSealDonut = DONUT PTAPnotSeal |
| PTAPvictim = (WITH TEXT PTAP "victim" textdraw) OR (WITH TEXT PTAP "vic" textdraw) |
| PTAPaggressor = (WITH TEXT PTAP "aggressor" textdraw) OR (WITH TEXT PTAP "agr" textdraw) |
| PTAPringVictim = PTAPvictim AND PTAPnotSealDonut |
| PTAPringAggressor = PTAPaggressor AND PTAPnotSealDonut |
| allVicAgrPTAPrings = PTAPringVictim OR PTAPringAggressor |
| victimRegionTmp1 = HOLES PTAPringVictim |
| aggressorRegionTmp1 = HOLES PTAPringAggressor |
| victimRegion = (INTERACT PTAPringVictim victimRegionTmp1) OR victimRegionTmp1 |
| aggressorRegion = (INTERACT PTAPringAggressor aggressorRegionTmp1) OR aggressorRegionTmp1 |
| CONNECT PTAP_NotDnwell_cond victimRegion |
| CONNECT PTAP_NotDnwell_cond aggressorRegion |
| vicDnwdiode = DNWELL_cond AND victimRegion |
| agrDnwdiode = DNWELL_cond AND aggressorRegion |
| vicNwdiode = (NOT DONUT (MosNwell AND victimRegion)) NOT INSIDE dnwell |
| agrNwdiode = (NOT DONUT (MosNwell AND aggressorRegion)) NOT INSIDE dnwell |
| DEVICE D(dnwdiode_psub_victim) vicDnwdiode victimRegion(POS) DNWELL_cond(NEG) BY NET NETLIST MODEL dnwdiode_psub [ |
| PROPERTY a , p , m , ahftempperim |
| p = perimeter( vicDnwdiode ) |
| a = area( vicDnwdiode ) |
| m = 1 |
| ahftempperim = perimeter( vicDnwdiode ) |
| ] |
| |
| TRACE PROPERTY D(dnwdiode_psub_victim) a a 10 |
| TRACE PROPERTY D(dnwdiode_psub_victim) p p 10 |
| TRACE PROPERTY D(dnwdiode_psub_victim) m m 0 |
| |
| DEVICE D(nwdiode_victim) vicNwdiode victimRegion(POS) MosNwell(NEG) BY NET NETLIST MODEL nwdiode [ |
| PROPERTY a , p , m , ahftempperim |
| p = perimeter( vicNwdiode ) |
| a = area( vicNwdiode ) |
| m = 1 |
| ahftempperim = perimeter( vicNwdiode ) |
| ] |
| |
| TRACE PROPERTY D(nwdiode_victim) a a 10 |
| TRACE PROPERTY D(nwdiode_victim) p p 10 |
| TRACE PROPERTY D(nwdiode_victim) m m 0 |
| |
| DEVICE D(dnwdiode_psub_aggressor) agrDnwdiode aggressorRegion(POS) DNWELL_cond(NEG) BY NET NETLIST MODEL dnwdiode_psub [ |
| PROPERTY a , p , m , ahftempperim |
| p = perimeter( agrDnwdiode ) |
| a = area( agrDnwdiode ) |
| m = 1 |
| ahftempperim = perimeter( agrDnwdiode ) |
| ] |
| |
| TRACE PROPERTY D(dnwdiode_psub_aggressor) a a 10 |
| TRACE PROPERTY D(dnwdiode_psub_aggressor) p p 10 |
| TRACE PROPERTY D(dnwdiode_psub_aggressor) m m 0 |
| |
| DEVICE D(nwdiode_aggressor) agrNwdiode aggressorRegion(POS) MosNwell(NEG) BY NET NETLIST MODEL nwdiode [ |
| PROPERTY a , p , m , ahftempperim |
| p = perimeter( agrNwdiode ) |
| a = area( agrNwdiode ) |
| m = 1 |
| ahftempperim = perimeter( agrNwdiode ) |
| ] |
| |
| TRACE PROPERTY D(nwdiode_aggressor) a a 10 |
| TRACE PROPERTY D(nwdiode_aggressor) p p 10 |
| TRACE PROPERTY D(nwdiode_aggressor) m m 0 |
| |
| /// End of Calibre Rules |
| |
| PORT LAYER POLYGON rdl_pin pad_pin met5_pin met4_pin |
| met3_pin met2_pin met1_pin li1_pin poly_pin diff_pin |
| nwell_pin pwelliso_pin pwell_pin |
| |
| // ;ss use same GROUP commands as lvsRules |
| |
| GROUP drcErrors "r_1030_Illegal fuse device m4fuse must not overlap PHdiodeID" "r_1029_Illegal fuse device m4fuse must not overlap ESDID" "r_1028_Illegal fuse device m4fuse must not overlap DiodeID" "r_1027_Illegal fuse device m4fuse must not overlap pnp" |
| "r_1026_Illegal fuse device m4fuse must not overlap hvi" "r_1025_Illegal fuse device m4fuse must not overlap lvtn" "r_1024_Illegal fuse device m4fuse must not overlap hvtp" "r_1023_Illegal fuse device m4fuse must not overlap ENID" "r_1022_Illegal fuse device m4fuse must not overlap LVID" |
| "r_1021_Illegal fuse device m4fuse must not overlap capacitor" "r_1020_Illegal fuse device m4fuse must not overlap li1cut" "r_1019_Illegal fuse device m4fuse must not overlap li1res" "r_1018_Illegal fuse device m4fuse must not overlap li1" "r_1017_Illegal fuse device m4fuse must not overlap licon1" |
| "r_1016_Illegal fuse device m4fuse must not overlap polycut" "r_1015_Illegal fuse device m4fuse must not overlap polyres" "r_1014_Illegal fuse device m4fuse must not overlap poly" "r_1013_Illegal fuse device m4fuse must not overlap diffcut" "r_1012_Illegal fuse device m4fuse must not overlap diffres" |
| "r_1011_Illegal fuse device m4fuse must not overlap diff" "r_1010_Illegal fuse device m4fuse must not overlap tap" "r_1009_Illegal fuse device m4fuse must not overlap nwell" "r_1008_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap PHdiodeID" "r_1007_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap COREID" |
| "r_1006_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap DiodeID" "r_1005_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap pnp" "r_1004_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap lvtn" "r_1003_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap hvtp" "r_1002_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap ENID" |
| "r_1001_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap LVID" "r_1000_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap capacitor" "r_999_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap nsdm" "r_998_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap fuse" "r_997_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap li1cut" |
| "r_996_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap diffcut" "r_995_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap diffres" "r_994_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap diff" "r_993_Illegal xhrpoly_5p73 device xhrpoly_5p73 must not overlap tap" "r_992_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap PHdiodeID" |
| "r_991_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap COREID" "r_990_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap DiodeID" "r_989_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap pnp" "r_988_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap lvtn" "r_987_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap hvtp" |
| "r_986_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap ENID" "r_985_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap LVID" "r_984_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap capacitor" "r_983_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap nsdm" "r_982_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap fuse" |
| "r_981_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap li1cut" "r_980_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap diffcut" "r_979_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap diffres" "r_978_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap diff" "r_977_Illegal xhrpoly_2p85 device xhrpoly_2p85 must not overlap tap" |
| "r_976_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap PHdiodeID" "r_975_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap COREID" "r_974_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap DiodeID" "r_973_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap pnp" "r_972_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap lvtn" |
| "r_971_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap hvtp" "r_970_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap ENID" "r_969_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap LVID" "r_968_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap capacitor" "r_967_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap nsdm" |
| "r_966_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap fuse" "r_965_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap li1cut" "r_964_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap diffcut" "r_963_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap diffres" "r_962_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap diff" |
| "r_961_Illegal xhrpoly_1p41 device xhrpoly_1p41 must not overlap tap" "r_960_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap PHdiodeID" "r_959_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap COREID" "r_958_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap DiodeID" "r_957_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap pnp" |
| "r_956_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap lvtn" "r_955_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap hvtp" "r_954_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap ENID" "r_953_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap LVID" "r_952_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap capacitor" |
| "r_951_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap nsdm" "r_950_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap fuse" "r_949_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap li1cut" "r_948_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap diffcut" "r_947_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap diffres" |
| "r_946_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap diff" "r_945_Illegal xhrpoly_0p69 device xhrpoly_0p69 must not overlap tap" "r_944_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap PHdiodeID" "r_943_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap COREID" "r_942_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap DiodeID" |
| "r_941_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap pnp" "r_940_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap lvtn" "r_939_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap hvtp" "r_938_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap ENID" "r_937_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap LVID" |
| "r_936_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap capacitor" "r_935_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap nsdm" "r_934_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap fuse" "r_933_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap li1cut" "r_932_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap diffcut" |
| "r_931_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap diffres" "r_930_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap diff" "r_929_Illegal xhrpoly_0p35 device xhrpoly_0p35 must not overlap tap" "r_928_Illegal pwell resistor device pwellresistor must not overlap PHdiodeID" "r_927_Illegal pwell resistor device pwellresistor must not overlap COREID" |
| "r_926_Illegal pwell resistor device pwellresistor must not overlap ENID" "r_925_Illegal pwell resistor device pwellresistor must not overlap LVID" "r_924_Illegal pwell resistor device pwellresistor must not overlap capacitor" "r_923_Illegal pwell resistor device pwellresistor must not overlap fuse" "r_922_Illegal pwell resistor device pwellresistor must not overlap li1cut" |
| "r_921_Illegal pwell resistor device pwellresistor must not overlap polycut" "r_920_Illegal pwell resistor device pwellresistor must not overlap polyres" "r_919_Illegal pwell resistor device pwellresistor must not overlap poly" "r_918_Illegal pwell resistor device pwellresistor must not overlap nwell" "r_917_Illegal ml1 device mrl1 must not overlap PHdiodeID" |
| "r_916_Illegal ml1 device mrl1 must not overlap COREID" "r_915_Illegal ml1 device mrl1 must not overlap ENID" "r_914_Illegal ml1 device mrl1 must not overlap capacitor" "r_913_Illegal ml1 device mrl1 must not overlap licon1" "r_912_Illegal ml1 device mrl1 must not overlap LVID" |
| "r_911_Illegal mrp1 device mrp1 must not overlap COREID" "r_910_Illegal mrp1 device mrp1 must not overlap DiodeID" "r_909_Illegal mrp1 device mrp1 must not overlap pnp" "r_908_Illegal mrp1 device mrp1 must not overlap lvtn" "r_907_Illegal mrp1 device mrp1 must not overlap hvtp" |
| "r_906_Illegal mrp1 device mrp1 must not overlap ENID" "r_905_Illegal mrp1 device mrp1 must not overlap LVID" "r_904_Illegal mrp1 device mrp1 must not overlap capacitor" "r_903_Illegal mrp1 device mrp1 must not overlap fuse" "r_902_Illegal mrp1 device mrp1 must not overlap li1cut" |
| "r_901_Illegal mrp1 device mrp1 must not overlap diffcut" "r_900_Illegal mrp1 device mrp1 must not overlap diffres" "r_899_Illegal mrp1 device mrp1 must not overlap diff" "r_898_Illegal mrp1 device mrp1 must not overlap tap" "r_897_Illegal mrp1 device mrp1 must not overlap ncm" |
| "r_896_Illegal HV mrdp device mrdp_hv must not overlap PHdiodeID" "r_895_Illegal HV mrdp device mrdp_hv must not overlap COREID" "r_894_Illegal HV mrdp device mrdp_hv must not overlap DiodeID" "r_893_Illegal HV mrdp device mrdp_hv must not overlap pnp" "r_892_Illegal HV mrdp device mrdp_hv must not overlap lvtn" |
| "r_891_Illegal HV mrdp device mrdp_hv must not overlap hvtp" "r_890_Illegal HV mrdp device mrdp_hv must not overlap ENID" "r_889_Illegal HV mrdp device mrdp_hv must not overlap LVID" "r_888_Illegal HV mrdp device mrdp_hv must not overlap capacitor" "r_887_Illegal HV mrdp device mrdp_hv must not overlap nsdm" |
| "r_886_Illegal HV mrdp device mrdp_hv must not overlap fuse" "r_885_Illegal HV mrdp device mrdp_hv must not overlap li1cut" "r_884_Illegal HV mrdp device mrdp_hv must not overlap polycut" "r_883_Illegal HV mrdp device mrdp_hv must not overlap polyres" "r_882_Illegal HV mrdp device mrdp_hv must not overlap poly" |
| "r_881_Illegal HV mrdp device mrdp_hv must not overlap tap" "r_880_Illegal HV mrdp device mrdp_hv must not overlap ncm" "r_879_Illegal HV mrdn device mrdn_hv must not overlap PHdiodeID" "r_878_Illegal HV mrdn device mrdn_hv must not overlap COREID" "r_877_Illegal HV mrdn device mrdn_hv must not overlap DiodeID" |
| "r_876_Illegal HV mrdn device mrdn_hv must not overlap pnp" "r_875_Illegal HV mrdn device mrdn_hv must not overlap lvtn" "r_874_Illegal HV mrdn device mrdn_hv must not overlap hvtp" "r_873_Illegal HV mrdn device mrdn_hv must not overlap ENID" "r_872_Illegal HV mrdn device mrdn_hv must not overlap LVID" |
| "r_871_Illegal HV mrdn device mrdn_hv must not overlap capacitor" "r_870_Illegal HV mrdn device mrdn_hv must not overlap psdm" "r_869_Illegal HV mrdn device mrdn_hv must not overlap fuse" "r_868_Illegal HV mrdn device mrdn_hv must not overlap li1cut" "r_867_Illegal HV mrdn device mrdn_hv must not overlap polycut" |
| "r_866_Illegal HV mrdn device mrdn_hv must not overlap polyres" "r_865_Illegal HV mrdn device mrdn_hv must not overlap poly" "r_864_Illegal HV mrdn device mrdn_hv must not overlap tap" "r_863_Illegal HV mrdn device mrdn_hv must not overlap nwell" "r_862_Illegal HV mrdn device mrdn_hv must not overlap ncm" |
| "r_861_Illegal mrdp device mrdp_lv must not overlap PHdiodeID" "r_860_Illegal mrdp device mrdp_lv must not overlap COREID" "r_859_Illegal mrdp device mrdp_lv must not overlap DiodeID" "r_858_Illegal mrdp device mrdp_lv must not overlap pnp" "r_857_Illegal mrdp device mrdp_lv must not overlap hvi" |
| "r_856_Illegal mrdp device mrdp_lv must not overlap lvtn" "r_855_Illegal mrdp device mrdp_lv must not overlap hvtp" "r_854_Illegal mrdp device mrdp_lv must not overlap ENID" "r_853_Illegal mrdp device mrdp_lv must not overlap LVID" "r_852_Illegal mrdp device mrdp_lv must not overlap capacitor" |
| "r_851_Illegal mrdp device mrdp_lv must not overlap nsdm" "r_850_Illegal mrdp device mrdp_lv must not overlap fuse" "r_849_Illegal mrdp device mrdp_lv must not overlap li1cut" "r_848_Illegal mrdp device mrdp_lv must not overlap polycut" "r_847_Illegal mrdp device mrdp_lv must not overlap polyres" |
| "r_846_Illegal mrdp device mrdp_lv must not overlap poly" "r_845_Illegal mrdp device mrdp_lv must not overlap tap" "r_844_Illegal mrdn device mrdn_lv must not overlap COREID" "r_843_Illegal mrdn device mrdn_lv must not overlap DiodeID" "r_842_Illegal mrdn device mrdn_lv must not overlap pnp" |
| "r_841_Illegal mrdn device mrdn_lv must not overlap hvi" "r_840_Illegal mrdn device mrdn_lv must not overlap lvtn" "r_839_Illegal mrdn device mrdn_lv must not overlap hvtp" "r_838_Illegal mrdn device mrdn_lv must not overlap ENID" "r_837_Illegal mrdn device mrdn_lv must not overlap LVID" |
| "r_836_Illegal mrdn device mrdn_lv must not overlap capacitor" "r_835_Illegal mrdn device mrdn_lv must not overlap psdm" "r_834_Illegal mrdn device mrdn_lv must not overlap fuse" "r_833_Illegal mrdn device mrdn_lv must not overlap li1cut" "r_832_Illegal mrdn device mrdn_lv must not overlap polycut" |
| "r_831_Illegal mrdn device mrdn_lv must not overlap polyres" "r_830_Illegal mrdn device mrdn_lv must not overlap poly" "r_829_Illegal mrdn device mrdn_lv must not overlap tap" "r_828_Illegal mrdn device mrdn_lv must not overlap nwell" "r_827_Illegal mrdn device mrdn_lv must not overlap ncm" |
| "r_826_resistorError" "r_825_resistorError" "r_824_resistorError" "r_823_resistorError" "r_822_resistorError" |
| "r_821_resistorError" "r_820_resistorError" "r_819_resistorError" "r_818_resistorError" "r_817_resistorError" |
| "r_816_resistorError" "r_815_resistorError" "r_814_resistorError" "r_813_resistorError" "r_812_resistorError" |
| "r_811_resistorError" "r_810_resistorError" "r_809_resistorError" "r_808_resistorError" "r_807_resistorError" |
| "r_806_resistorError" "r_805_resistorError" "r_804_resistorError" "r_803_resistorError" "r_802_resistorError" |
| "r_801_resistorError" "r_800_resistorError" "r_799_resistorError" "r_798_resistorError" "r_797_resistorError" |
| "r_796_resistorError" "r_795_resistorError" "r_794_resistorError" "r_793_resistorError" |
| "r_792_Illegal rdl cu inductor device rdl_inductor must not overlap ind4Center_met3" |
| "r_791_Illegal met5 cu inductor device met5_inductor must not overlap ind4Center_met5" "r_790_Illegal met5 cu device balun must not overlap COREID" "r_789_Illegal met5 cu device balun must not overlap PHdiodeID" "r_788_Illegal met5 cu device balun must not overlap DiodeID" "r_787_Illegal met5 cu device balun must not overlap npn" |
| "r_786_Illegal met5 cu device balun must not overlap pnp" "r_785_Illegal met5 cu device balun must not overlap localSub" "r_784_Illegal met5 cu device balun must not overlap ENID" "r_783_Illegal met5 cu device balun must not overlap LVID" "r_782_Illegal met5 cu device balun must not overlap capacitor" |
| "r_781_Illegal inductor device xind4 must not overlap COREID" "r_780_Illegal inductor device xind4 must not overlap PHdiodeID" "r_779_Illegal inductor device xind4 must not overlap DiodeID" "r_778_Illegal inductor device xind4 must not overlap npn" "r_777_Illegal inductor device xind4 must not overlap pnp" |
| "r_776_Illegal inductor device xind4 must not overlap localSub" "r_775_Illegal inductor device xind4 must not overlap ENID" "r_774_Illegal inductor device xind4 must not overlap LVID" "r_773_Illegal inductor device xind4 must not overlap capacitor" "r_772_Illegal vppcaps capdraw must not overlap PHdiodeID" |
| "r_771_Illegal vppcaps capdraw must not overlap COREID" "r_770_Illegal vppcaps capdraw must not overlap ENID" "r_769_Illegal vppcaps capdraw must not overlap LVID" "r_768_Illegal vppcaps capdraw must not overlap fuse" "r_767_Illegal pdiode_lvt device pdiode_par_lvtn must not overlap PHdiodeID" |
| "r_766_Illegal pdiode_lvt device pdiode_par_lvtn must not overlap hvtp" "r_765_Illegal dnwdiode_pw device pw_dnw_par must not overlap PHdiodeID" "r_764_Illegal dnwdiode_pw device pw_dnw_par must not overlap nwell" "r_763_Illegal nwdiode device nwdio_par must not overlap PHdiodeID" "r_762_Illegal nwdiode device nwdio_par must not overlap dnwell" |
| "r_761_Illegal pdiode_hvt device pdiode_par_highvt must not overlap PHdiodeID" "r_760_Illegal pdiode_hvt device pdiode_par_highvt must not overlap hvi" "r_759_Illegal photoDiode device photoDiode must not overlap ESDID" "r_758_Illegal photoDiode device photoDiode must not overlap COREID" "r_757_Illegal photoDiode device photoDiode must not overlap pnp" |
| "r_756_Illegal photoDiode device photoDiode must not overlap LVID" "r_755_Illegal photoDiode device photoDiode must not overlap capacitor" "r_754_Illegal photoDiode device photoDiode must not overlap fuse" "r_753_Illegal photoDiode device photoDiode must not overlap li1cut" "r_752_Illegal photoDiode device photoDiode must not overlap li1res" |
| "r_751_Illegal photoDiode device photoDiode must not overlap psdm" "r_750_Illegal photoDiode device photoDiode must not overlap npc" "r_749_Illegal photoDiode device photoDiode must not overlap polyModel" "r_748_Illegal photoDiode device photoDiode must not overlap polycut" "r_747_Illegal photoDiode device photoDiode must not overlap polyres" |
| "r_746_Illegal photoDiode device photoDiode must not overlap poly" "r_745_Illegal photoDiode device photoDiode must not overlap hvi" "r_744_Illegal photoDiode device photoDiode must not overlap tunm" "r_743_Illegal photoDiode device photoDiode must not overlap lvtn" "r_742_Illegal photoDiode device photoDiode must not overlap hvtp" |
| "r_741_Illegal photoDiode device photoDiode must not overlap diffcut" "r_740_Illegal photoDiode device photoDiode must not overlap diffres" "r_739_Illegal photoDiode device photoDiode must not overlap diff" "r_738_Illegal photoDiode device photoDiode must not overlap ncm" "r_737_Illegal pDiode_hvi device pDiode_hvi must not overlap PHdiodeID" |
| "r_736_Illegal pDiode_hvi device pDiode_hvi must not overlap COREID" "r_735_Illegal pDiode_hvi device pDiode_hvi must not overlap pnp" "r_734_Illegal pDiode_hvi device pDiode_hvi must not overlap lvtn" "r_733_Illegal pDiode_hvi device pDiode_hvi must not overlap hvtp" "r_732_Illegal pDiode_hvi device pDiode_hvi must not overlap LVID" |
| "r_731_Illegal pDiode_hvi device pDiode_hvi must not overlap capacitor" "r_730_Illegal pDiode_hvi device pDiode_hvi must not overlap nsdm" "r_729_Illegal pDiode_hvi device pDiode_hvi must not overlap li1cut" "r_728_Illegal pDiode_hvi device pDiode_hvi must not overlap li1res" "r_727_Illegal pDiode_hvi device pDiode_hvi must not overlap fuse" |
| "r_726_Illegal pDiode_hvi device pDiode_hvi must not overlap polycut" "r_725_Illegal pDiode_hvi device pDiode_hvi must not overlap polyres" "r_724_Illegal pDiode_hvi device pDiode_hvi must not overlap poly" "r_723_Illegal pDiode_hvi device pDiode_hvi must not overlap diffcut" "r_722_Illegal pDiode_hvi device pDiode_hvi must not overlap diffres" |
| "r_721_Illegal pDiode_hvi device pDiode_hvi must not overlap tap" "r_720_Illegal pDiode_hvi device pDiode_hvi must not overlap ncm" "r_719_Illegal pDiode device pDiode must not overlap PHdiodeID" "r_718_Illegal pDiode device pDiode must not overlap pnp" "r_717_Illegal pDiode device pDiode must not overlap hvi" |
| "r_716_Illegal pDiode device pDiode must not overlap lvtn" "r_715_Illegal pDiode device pDiode must not overlap hvtp" "r_714_Illegal pDiode device pDiode must not overlap LVID" "r_713_Illegal pDiode device pDiode must not overlap capacitor" "r_712_Illegal pDiode device pDiode must not overlap nsdm" |
| "r_711_Illegal pDiode device pDiode must not overlap li1cut" "r_710_Illegal pDiode device pDiode must not overlap li1res" "r_709_Illegal pDiode device pDiode must not overlap fuse" "r_708_Illegal pDiode device pDiode must not overlap polycut" "r_707_Illegal pDiode device pDiode must not overlap polyres" |
| "r_706_Illegal pDiode device pDiode must not overlap poly" "r_705_Illegal pDiode device pDiode must not overlap diffcut" "r_704_Illegal pDiode device pDiode must not overlap diffres" "r_703_Illegal pDiode device pDiode must not overlap tap" "r_702_Illegal nDiode_hvi device nDiode_hvi must not overlap PHdiodeID" |
| "r_701_Illegal nDiode_hvi device nDiode_hvi must not overlap COREID" "r_700_Illegal nDiode_hvi device nDiode_hvi must not overlap pnp" "r_699_Illegal nDiode_hvi device nDiode_hvi must not overlap lvtn" "r_698_Illegal nDiode_hvi device nDiode_hvi must not overlap hvtp" "r_697_Illegal nDiode_hvi device nDiode_hvi must not overlap LVID" |
| "r_696_Illegal nDiode_hvi device nDiode_hvi must not overlap capacitor" "r_695_Illegal nDiode_hvi device nDiode_hvi must not overlap psdm" "r_694_Illegal nDiode_hvi device nDiode_hvi must not overlap li1cut" "r_693_Illegal nDiode_hvi device nDiode_hvi must not overlap li1res" "r_692_Illegal nDiode_hvi device nDiode_hvi must not overlap fuse" |
| "r_691_Illegal nDiode_hvi device nDiode_hvi must not overlap polycut" "r_690_Illegal nDiode_hvi device nDiode_hvi must not overlap polyres" "r_689_Illegal nDiode_hvi device nDiode_hvi must not overlap poly" "r_688_Illegal nDiode_hvi device nDiode_hvi must not overlap diffcut" "r_687_Illegal nDiode_hvi device nDiode_hvi must not overlap diffres" |
| "r_686_Illegal nDiode_hvi device nDiode_hvi must not overlap tap" "r_685_Illegal nDiode_hvi device nDiode_hvi must not overlap nwell" "r_684_Illegal nDiode_hvi device nDiode_hvi must not overlap ncm" "r_683_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap PHdiodeID" "r_682_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap pnp" |
| "r_681_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap hvi" "r_680_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap lvtn" "r_679_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap hvtp" "r_678_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap LVID" "r_677_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap capacitor" |
| "r_676_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap psdm" "r_675_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap li1cut" "r_674_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap li1res" "r_673_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap fuse" "r_672_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap polycut" |
| "r_671_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap polyres" "r_670_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap poly" "r_669_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap diffcut" "r_668_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap diffres" "r_667_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap tap" |
| "r_666_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap nwell" "r_665_Illegal diode_pw2nd_05v5 device diode_pw2nd_05v5 must not overlap ncm" "r_664_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap pwres" "r_663_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap pnp" "r_662_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap PHdiodeID" |
| "r_661_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap ESDID" "r_660_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap COREID" "r_659_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap DiodeID" "r_658_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap lvtn" "r_657_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap ENID" |
| "r_656_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap LVID" "r_655_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap capacitor" "r_654_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap fuse" "r_653_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap li1cut" "r_652_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap li1res" |
| "r_651_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap polycut" "r_650_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap polyres" "r_649_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap diffcut" "r_648_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap diffres" "r_647_Illegal npnpar device npn_and_s8rf_npn_1x1_2p0_HV must not overlap ncm" |
| "r_646_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap pwres" "r_645_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap pnp" "r_644_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap PHdiodeID" "r_643_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap ESDID" "r_642_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap COREID" |
| "r_641_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap DiodeID" "r_640_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap hvi" "r_639_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap lvtn" "r_638_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap ENID" "r_637_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap LVID" |
| "r_636_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap capacitor" "r_635_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap fuse" "r_634_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap li1cut" "r_633_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap li1res" "r_632_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap polycut" |
| "r_631_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap polyres" "r_630_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap poly" "r_629_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap diffcut" "r_628_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap diffres" "r_627_Illegal npnpar device npn_not_s8rf_npn_1x1_2p0_HV must not overlap ncm" |
| "r_626_Illegal pnppar device pnp must not overlap PHdiodeID" "r_625_Illegal pnppar device pnp must not overlap ESDID" "r_624_Illegal pnppar device pnp must not overlap COREID" "r_623_Illegal pnppar device pnp must not overlap DiodeID" "r_622_Illegal pnppar device pnp must not overlap hvi" |
| "r_621_Illegal pnppar device pnp must not overlap lvtn" "r_620_Illegal pnppar device pnp must not overlap ENID" "r_619_Illegal pnppar device pnp must not overlap LVID" "r_618_Illegal pnppar device pnp must not overlap capacitor" "r_617_Illegal pnppar device pnp must not overlap fuse" |
| "r_616_Illegal pnppar device pnp must not overlap li1cut" "r_615_Illegal pnppar device pnp must not overlap li1res" "r_614_Illegal pnppar device pnp must not overlap polycut" "r_613_Illegal pnppar device pnp must not overlap polyres" "r_612_Illegal pnppar device pnp must not overlap poly" |
| "r_611_Illegal pnppar device pnp must not overlap diffcut" "r_610_Illegal pnppar device pnp must not overlap diffres" "r_609_Illegal pnppar device pnp must not overlap dnwell" "r_608_Illegal pnppar device pnp must not overlap ncm" "r_607_bad npn" |
| "r_606_bad pnp" "r_605_bad npn" "r_604_Illegal pvhv device pfetExtDr must not overlap PHdiodeID" "r_603_Illegal pvhv device pfetExtDr must not overlap ESDID" "r_602_Illegal pvhv device pfetExtDr must not overlap COREID" |
| "r_601_Illegal pvhv device pfetExtDr must not overlap DiodeID" "r_600_Illegal pvhv device pfetExtDr must not overlap pnp" "r_599_Illegal pvhv device pfetExtDr must not overlap lvtn" "r_598_Illegal pvhv device pfetExtDr must not overlap hvtp" "r_597_Illegal pvhv device pfetExtDr must not overlap LVID" |
| "r_596_Illegal pvhv device pfetExtDr must not overlap capacitor" "r_595_Illegal pvhv device pfetExtDr must not overlap nsdm" "r_594_Illegal pvhv device pfetExtDr must not overlap fuse" "r_593_Illegal pvhv device pfetExtDr must not overlap li1cut" "r_592_Illegal pvhv device pfetExtDr must not overlap li1res" |
| "r_591_Illegal pvhv device pfetExtDr must not overlap polycut" "r_590_Illegal pvhv device pfetExtDr must not overlap polyres" "r_589_Illegal pvhv device pfetExtDr must not overlap npc" "r_588_Illegal pvhv device pfetExtDr must not overlap diffcut" "r_587_Illegal pvhv device pfetExtDr must not overlap diffres" |
| "r_586_Illegal pvhv device pfetExtDr must not overlap tunm" "r_585_Illegal pvhv device pfetExtDr must not overlap ncm" "r_584_Illegal nvhv device nfetExtDr must not overlap PHdiodeID" "r_583_Illegal nvhv device nfetExtDr must not overlap ESDID" "r_582_Illegal nvhv device nfetExtDr must not overlap COREID" |
| "r_581_Illegal nvhv device nfetExtDr must not overlap DiodeID" "r_580_Illegal nvhv device nfetExtDr must not overlap pnp" "r_579_Illegal nvhv device nfetExtDr must not overlap lvtn" "r_578_Illegal nvhv device nfetExtDr must not overlap hvtp" "r_577_Illegal nvhv device nfetExtDr must not overlap LVID" |
| "r_576_Illegal nvhv device nfetExtDr must not overlap capacitor" "r_575_Illegal nvhv device nfetExtDr must not overlap psdm" "r_574_Illegal nvhv device nfetExtDr must not overlap fuse" "r_573_Illegal nvhv device nfetExtDr must not overlap li1cut" "r_572_Illegal nvhv device nfetExtDr must not overlap li1res" |
| "r_571_Illegal nvhv device nfetExtDr must not overlap polycut" "r_570_Illegal nvhv device nfetExtDr must not overlap polyres" "r_569_Illegal nvhv device nfetExtDr must not overlap npc" "r_568_Illegal nvhv device nfetExtDr must not overlap diffcut" "r_567_Illegal nvhv device nfetExtDr must not overlap diffres" |
| "r_566_Illegal nvhv device nfetExtDr must not overlap tunm" "r_565_Illegal nvhv device nfetExtDr must not overlap dnwell" "r_564_Illegal nvhv device nfetExtDr must not overlap ncm" "r_563_Illegal nvhv device nfetExtDrCheck must not overlap dnwell" "r_562_condiode.err" |
| "r_561_Illegal condiode device" "r_560_Illegal" "r_559_Illegal plowvt device plowvt5x4 must not overlap ldntm" "r_558_Illegal plowvt device plowvt5x4 must not overlap PHdiodeID" "r_557_Illegal plowvt device plowvt5x4 must not overlap ESDID" |
| "r_556_Illegal plowvt device plowvt5x4 must not overlap COREID" "r_555_Illegal plowvt device plowvt5x4 must not overlap DiodeID" "r_554_Illegal plowvt device plowvt5x4 must not overlap pnp" "r_553_Illegal plowvt device plowvt5x4 must not overlap hvi" "r_552_Illegal plowvt device plowvt5x4 must not overlap hvtp" |
| "r_551_Illegal plowvt device plowvt5x4 must not overlap ENID" "r_550_Illegal plowvt device plowvt5x4 must not overlap LVID" "r_549_Illegal plowvt device plowvt5x4 must not overlap nsdm" "r_548_Illegal plowvt device plowvt5x4 must not overlap fuse" "r_547_Illegal plowvt device plowvt5x4 must not overlap li1cut" |
| "r_546_Illegal plowvt device plowvt5x4 must not overlap li1res" "r_545_Illegal plowvt device plowvt5x4 must not overlap polycut" "r_544_Illegal plowvt device plowvt5x4 must not overlap polyres" "r_543_Illegal plowvt device plowvt5x4 must not overlap npc" "r_542_Illegal plowvt device plowvt5x4 must not overlap diffcut" |
| "r_541_Illegal plowvt device plowvt5x4 must not overlap diffres" "r_540_Illegal plowvt device plowvt5x4 must not overlap tunm" "r_539_Illegal plowvt device plowvt5x4 must not overlap tap" "r_538_Illegal plowvt device plowvtNoCap must not overlap ldntm" "r_537_Illegal plowvt device plowvtNoCap must not overlap PHdiodeID" |
| "r_536_Illegal plowvt device plowvtNoCap must not overlap ESDID" "r_535_Illegal plowvt device plowvtNoCap must not overlap COREID" "r_534_Illegal plowvt device plowvtNoCap must not overlap DiodeID" "r_533_Illegal plowvt device plowvtNoCap must not overlap pnp" "r_532_Illegal plowvt device plowvtNoCap must not overlap hvi" |
| "r_531_Illegal plowvt device plowvtNoCap must not overlap hvtp" "r_530_Illegal plowvt device plowvtNoCap must not overlap ENID" "r_529_Illegal plowvt device plowvtNoCap must not overlap LVID" "r_528_Illegal plowvt device plowvtNoCap must not overlap capacitor" "r_527_Illegal plowvt device plowvtNoCap must not overlap nsdm" |
| "r_526_Illegal plowvt device plowvtNoCap must not overlap fuse" "r_525_Illegal plowvt device plowvtNoCap must not overlap li1cut" "r_524_Illegal plowvt device plowvtNoCap must not overlap li1res" "r_523_Illegal plowvt device plowvtNoCap must not overlap polycut" "r_522_Illegal plowvt device plowvtNoCap must not overlap polyres" |
| "r_521_Illegal plowvt device plowvtNoCap must not overlap npc" "r_520_Illegal plowvt device plowvtNoCap must not overlap diffcut" "r_519_Illegal plowvt device plowvtNoCap must not overlap diffres" "r_518_Illegal plowvt device plowvtNoCap must not overlap tunm" "r_517_Illegal plowvt device plowvtNoCap must not overlap tap" |
| "r_516_phighvt in core must overlap ncm" "r_515_Illegal ppu device phighvt_CORE must not overlap ldntm" "r_514_Illegal ppu device phighvt_CORE must not overlap PHdiodeID" "r_513_Illegal ppu device phighvt_CORE must not overlap ESDID" "r_512_Illegal ppu device phighvt_CORE must not overlap DiodeID" |
| "r_511_Illegal ppu device phighvt_CORE must not overlap pnp" "r_510_Illegal ppu device phighvt_CORE must not overlap hvi" "r_509_Illegal ppu device phighvt_CORE must not overlap ENID" "r_508_Illegal ppu device phighvt_CORE must not overlap LVID" "r_507_Illegal ppu device phighvt_CORE must not overlap capacitor" |
| "r_506_Illegal ppu device phighvt_CORE must not overlap nsdm" "r_505_Illegal ppu device phighvt_CORE must not overlap fuse" "r_504_Illegal ppu device phighvt_CORE must not overlap li1cut" "r_503_Illegal ppu device phighvt_CORE must not overlap li1res" "r_502_Illegal ppu device phighvt_CORE must not overlap polycut" |
| "r_501_Illegal ppu device phighvt_CORE must not overlap polyres" "r_500_Illegal ppu device phighvt_CORE must not overlap npc" "r_499_Illegal ppu device phighvt_CORE must not overlap diffcut" "r_498_Illegal ppu device phighvt_CORE must not overlap diffres" "r_497_Illegal ppu device phighvt_CORE must not overlap tunm" |
| "r_496_Illegal ppu device phighvt_CORE must not overlap tap" "r_495_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap ldntm" "r_494_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap PHdiodeID" "r_493_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap ESDID" "r_492_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap COREID" |
| "r_491_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap DiodeID" "r_490_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap pnp" "r_489_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap hvi" "r_488_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap ENID" "r_487_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap LVID" |
| "r_486_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap nsdm" "r_485_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap fuse" "r_484_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap li1cut" "r_483_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap li1res" "r_482_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap polycut" |
| "r_481_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap polyres" "r_480_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap npc" "r_479_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap diffcut" "r_478_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap diffres" "r_477_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap tunm" |
| "r_476_Illegal PFET_01V8_HVT device phighvt5x4_PERI must not overlap tap" "r_475_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap ldntm" "r_474_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap PHdiodeID" "r_473_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap ESDID" "r_472_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap COREID" |
| "r_471_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap DiodeID" "r_470_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap pnp" "r_469_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap hvi" "r_468_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap ENID" "r_467_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap LVID" |
| "r_466_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap capacitor" "r_465_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap nsdm" "r_464_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap fuse" "r_463_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap li1cut" "r_462_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap li1res" |
| "r_461_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap polycut" "r_460_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap polyres" "r_459_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap npc" "r_458_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap diffcut" "r_457_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap diffres" |
| "r_456_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap tunm" "r_455_Illegal PFET_01V8_HVT device phighvtNoCap_PERI must not overlap tap" "r_454_Illegal phvesd device phvesd must not overlap ldntm" "r_453_Illegal phvesd device phvesd must not overlap PHdiodeID" "r_452_Illegal phvesd device phvesd must not overlap COREID" |
| "r_451_Illegal phvesd device phvesd must not overlap DiodeID" "r_450_Illegal phvesd device phvesd must not overlap pnp" "r_449_Illegal phvesd device phvesd must not overlap lvtn" "r_448_Illegal phvesd device phvesd must not overlap hvtp" "r_447_Illegal phvesd device phvesd must not overlap ENID" |
| "r_446_Illegal phvesd device phvesd must not overlap LVID" "r_445_Illegal phvesd device phvesd must not overlap capacitor" "r_444_Illegal phvesd device phvesd must not overlap nsdm" "r_443_Illegal phvesd device phvesd must not overlap fuse" "r_442_Illegal phvesd device phvesd must not overlap li1cut" |
| "r_441_Illegal phvesd device phvesd must not overlap li1res" "r_440_Illegal phvesd device phvesd must not overlap polycut" "r_439_Illegal phvesd device phvesd must not overlap polyres" "r_438_Illegal phvesd device phvesd must not overlap npc" "r_437_Illegal phvesd device phvesd must not overlap diffcut" |
| "r_436_Illegal phvesd device phvesd must not overlap diffres" "r_435_Illegal phvesd device phvesd must not overlap tunm" "r_434_Illegal phvesd device phvesd must not overlap tap" "r_433_Illegal phvesd device phvesd must not overlap ncm" "r_432_Illegal phv device phv5x4 must not overlap ldntm" |
| "r_431_Illegal phv device phv5x4 must not overlap PHdiodeID" "r_430_Illegal phv device phv5x4 must not overlap COREID" "r_429_Illegal phv device phv5x4 must not overlap DiodeID" "r_428_Illegal phv device phv5x4 must not overlap pnp" "r_427_Illegal phv device phv5x4 must not overlap ENID" |
| "r_426_Illegal phv device phv5x4 must not overlap LVID" "r_425_Illegal phv device phv5x4 must not overlap nsdm" "r_424_Illegal phv device phv5x4 must not overlap fuse" "r_423_Illegal phv device phv5x4 must not overlap li1cut" "r_422_Illegal phv device phv5x4 must not overlap li1res" |
| "r_421_Illegal phv device phv5x4 must not overlap polycut" "r_420_Illegal phv device phv5x4 must not overlap polyres" "r_419_Illegal phv device phv5x4 must not overlap npc" "r_418_Illegal phv device phv5x4 must not overlap diffcut" "r_417_Illegal phv device phv5x4 must not overlap diffres" |
| "r_416_Illegal phv device phv5x4 must not overlap tunm" "r_415_Illegal phv device phv5x4 must not overlap tap" "r_414_Illegal phv device phv5x4 must not overlap ncm" "r_413_Illegal phv device phvNoCap must not overlap ldntm" "r_412_Illegal phv device phvNoCap must not overlap PHdiodeID" |
| "r_411_Illegal phv device phvNoCap must not overlap COREID" "r_410_Illegal phv device phvNoCap must not overlap DiodeID" "r_409_Illegal phv device phvNoCap must not overlap pnp" "r_408_Illegal phv device phvNoCap must not overlap ENID" "r_407_Illegal phv device phvNoCap must not overlap LVID" |
| "r_406_Illegal phv device phvNoCap must not overlap capacitor" "r_405_Illegal phv device phvNoCap must not overlap nsdm" "r_404_Illegal phv device phvNoCap must not overlap fuse" "r_403_Illegal phv device phvNoCap must not overlap li1cut" "r_402_Illegal phv device phvNoCap must not overlap li1res" |
| "r_401_Illegal phv device phvNoCap must not overlap polycut" "r_400_Illegal phv device phvNoCap must not overlap polyres" "r_399_Illegal phv device phvNoCap must not overlap npc" "r_398_Illegal phv device phvNoCap must not overlap diffcut" "r_397_Illegal phv device phvNoCap must not overlap diffres" |
| "r_396_Illegal phv device phvNoCap must not overlap tunm" "r_395_Illegal phv device phvNoCap must not overlap tap" "r_394_Illegal phv device phvNoCap must not overlap ncm" "r_393_Illegal pshort device pshort5x4 must not overlap ldntm" "r_392_Illegal pshort device pshort5x4 must not overlap PHdiodeID" |
| "r_391_Illegal pshort device pshort5x4 must not overlap COREID" "r_390_Illegal pshort device pshort5x4 must not overlap DiodeID" "r_389_Illegal pshort device pshort5x4 must not overlap pnp" "r_388_Illegal pshort device pshort5x4 must not overlap hvi" "r_387_Illegal pshort device pshort5x4 must not overlap lvtn" |
| "r_386_Illegal pshort device pshort5x4 must not overlap ENID" "r_385_Illegal pshort device pshort5x4 must not overlap LVID" "r_384_Illegal pshort device pshort5x4 must not overlap nsdm" "r_383_Illegal pshort device pshort5x4 must not overlap fuse" "r_382_Illegal pshort device pshort5x4 must not overlap li1cut" |
| "r_381_Illegal pshort device pshort5x4 must not overlap li1res" "r_380_Illegal pshort device pshort5x4 must not overlap polycut" "r_379_Illegal pshort device pshort5x4 must not overlap polyres" "r_378_Illegal pshort device pshort5x4 must not overlap npc" "r_377_Illegal pshort device pshort5x4 must not overlap diffcut" |
| "r_376_Illegal pshort device pshort5x4 must not overlap diffres" "r_375_Illegal pshort device pshort5x4 must not overlap tunm" "r_374_Illegal pshort device pshort5x4 must not overlap tap" "r_373_Illegal pshort device pshortNoCap must not overlap ldntm" "r_372_Illegal pshort device pshortNoCap must not overlap PHdiodeID" |
| "r_371_Illegal pshort device pshortNoCap must not overlap COREID" "r_370_Illegal pshort device pshortNoCap must not overlap DiodeID" "r_369_Illegal pshort device pshortNoCap must not overlap pnp" "r_368_Illegal pshort device pshortNoCap must not overlap hvi" "r_367_Illegal pshort device pshortNoCap must not overlap lvtn" |
| "r_366_Illegal pshort device pshortNoCap must not overlap ENID" "r_365_Illegal pshort device pshortNoCap must not overlap LVID" "r_364_Illegal pshort device pshortNoCap must not overlap capacitor" "r_363_Illegal pshort device pshortNoCap must not overlap nsdm" "r_362_Illegal pshort device pshortNoCap must not overlap fuse" |
| "r_361_Illegal pshort device pshortNoCap must not overlap li1cut" "r_360_Illegal pshort device pshortNoCap must not overlap li1res" "r_359_Illegal pshort device pshortNoCap must not overlap polycut" "r_358_Illegal pshort device pshortNoCap must not overlap polyres" "r_357_Illegal pshort device pshortNoCap must not overlap npc" |
| "r_356_Illegal pshort device pshortNoCap must not overlap diffcut" "r_355_Illegal pshort device pshortNoCap must not overlap diffres" "r_354_Illegal pshort device pshortNoCap must not overlap tunm" "r_353_Illegal pshort device pshortNoCap must not overlap tap" "r_352_Illegal xcnwvc2 device xcnwvc2 must not overlap ldntm" |
| "r_351_Illegal xcnwvc2 device xcnwvc2 must not overlap PHdiodeID" "r_350_Illegal xcnwvc2 device xcnwvc2 must not overlap COREID" "r_349_Illegal xcnwvc2 device xcnwvc2 must not overlap ESDID" "r_348_Illegal xcnwvc2 device xcnwvc2 must not overlap DiodeID" "r_347_Illegal xcnwvc2 device xcnwvc2 must not overlap pnp" |
| "r_346_Illegal xcnwvc2 device xcnwvc2 must not overlap hvi" "r_345_Illegal xcnwvc2 device xcnwvc2 must not overlap ENID" "r_344_Illegal xcnwvc2 device xcnwvc2 must not overlap LVID" "r_343_Illegal xcnwvc2 device xcnwvc2 must not overlap capacitor" "r_342_Illegal xcnwvc2 device xcnwvc2 must not overlap psdm" |
| "r_341_Illegal xcnwvc2 device xcnwvc2 must not overlap fuse" "r_340_Illegal xcnwvc2 device xcnwvc2 must not overlap li1cut" "r_339_Illegal xcnwvc2 device xcnwvc2 must not overlap li1res" "r_338_Illegal xcnwvc2 device xcnwvc2 must not overlap polycut" "r_337_Illegal xcnwvc2 device xcnwvc2 must not overlap polyres" |
| "r_336_Illegal xcnwvc2 device xcnwvc2 must not overlap npc" "r_335_Illegal xcnwvc2 device xcnwvc2 must not overlap diffcut" "r_334_Illegal xcnwvc2 device xcnwvc2 must not overlap diffres" "r_333_Illegal xcnwvc2 device xcnwvc2 must not overlap diff" "r_332_Illegal xcnwvc2 device xcnwvc2 must not overlap tunm" |
| "r_331_Illegal xcnwvc device xcnwvc must not overlap ldntm" "r_330_Illegal xcnwvc device xcnwvc must not overlap PHdiodeID" "r_329_Illegal xcnwvc device xcnwvc must not overlap COREID" "r_328_Illegal xcnwvc device xcnwvc must not overlap ESDID" "r_327_Illegal xcnwvc device xcnwvc must not overlap DiodeID" |
| "r_326_Illegal xcnwvc device xcnwvc must not overlap pnp" "r_325_Illegal xcnwvc device xcnwvc must not overlap hvi" "r_324_Illegal xcnwvc device xcnwvc must not overlap hvtp" "r_323_Illegal xcnwvc device xcnwvc must not overlap ENID" "r_322_Illegal xcnwvc device xcnwvc must not overlap LVID" |
| "r_321_Illegal xcnwvc device xcnwvc must not overlap capacitor" "r_320_Illegal xcnwvc device xcnwvc must not overlap psdm" "r_319_Illegal xcnwvc device xcnwvc must not overlap fuse" "r_318_Illegal xcnwvc device xcnwvc must not overlap li1cut" "r_317_Illegal xcnwvc device xcnwvc must not overlap li1res" |
| "r_316_Illegal xcnwvc device xcnwvc must not overlap polycut" "r_315_Illegal xcnwvc device xcnwvc must not overlap polyres" "r_314_Illegal xcnwvc device xcnwvc must not overlap npc" "r_313_Illegal xcnwvc device xcnwvc must not overlap diffcut" "r_312_Illegal xcnwvc device xcnwvc must not overlap diffres" |
| "r_311_Illegal xcnwvc device xcnwvc must not overlap diff" "r_310_Illegal xcnwvc device xcnwvc must not overlap tunm" "r_309_Illegal xcnwvc device xcnwvc must not overlap ncm" "r_308_Illegal nshortesd device nshortesd must not overlap ldntm" "r_307_Illegal nshortesd device nshortesd must not overlap PHdiodeID" |
| "r_306_Illegal nshortesd device nshortesd must not overlap COREID" "r_305_Illegal nshortesd device nshortesd must not overlap DiodeID" "r_304_Illegal nshortesd device nshortesd must not overlap pnp" "r_303_Illegal nshortesd device nshortesd must not overlap hvi" "r_302_Illegal nshortesd device nshortesd must not overlap lvtn" |
| "r_301_Illegal nshortesd device nshortesd must not overlap hvtp" "r_300_Illegal nshortesd device nshortesd must not overlap ENID" "r_299_Illegal nshortesd device nshortesd must not overlap LVID" "r_298_Illegal nshortesd device nshortesd must not overlap capacitor" "r_297_Illegal nshortesd device nshortesd must not overlap psdm" |
| "r_296_Illegal nshortesd device nshortesd must not overlap fuse" "r_295_Illegal nshortesd device nshortesd must not overlap li1cut" "r_294_Illegal nshortesd device nshortesd must not overlap li1res" "r_293_Illegal nshortesd device nshortesd must not overlap polycut" "r_292_Illegal nshortesd device nshortesd must not overlap polyres" |
| "r_291_Illegal nshortesd device nshortesd must not overlap npc" "r_290_Illegal nshortesd device nshortesd must not overlap diffcut" "r_289_Illegal nshortesd device nshortesd must not overlap diffres" "r_288_Illegal nshortesd device nshortesd must not overlap tunm" "r_287_Illegal nshortesd device nshortesd must not overlap tap" |
| "r_286_Illegal nshortesd device nshortesd must not overlap nwell" "r_285_Illegal nshortesd device nshortesd must not overlap ncm" "r_284_Illegal nhvnativeesd device nhvnativeesd must not overlap ldntm" "r_283_Illegal nhvnativeesd device nhvnativeesd must not overlap PHdiodeID" "r_282_Illegal nhvnativeesd device nhvnativeesd must not overlap COREID" |
| "r_281_Illegal nhvnativeesd device nhvnativeesd must not overlap DiodeID" "r_280_Illegal nhvnativeesd device nhvnativeesd must not overlap pnp" "r_279_Illegal nhvnativeesd device nhvnativeesd must not overlap hvtp" "r_278_Illegal nhvnativeesd device nhvnativeesd must not overlap ENID" "r_277_Illegal nhvnativeesd device nhvnativeesd must not overlap LVID" |
| "r_276_Illegal nhvnativeesd device nhvnativeesd must not overlap capacitor" "r_275_Illegal nhvnativeesd device nhvnativeesd must not overlap psdm" "r_274_Illegal nhvnativeesd device nhvnativeesd must not overlap fuse" "r_273_Illegal nhvnativeesd device nhvnativeesd must not overlap li1cut" "r_272_Illegal nhvnativeesd device nhvnativeesd must not overlap li1res" |
| "r_271_Illegal nhvnativeesd device nhvnativeesd must not overlap polycut" "r_270_Illegal nhvnativeesd device nhvnativeesd must not overlap polyres" "r_269_Illegal nhvnativeesd device nhvnativeesd must not overlap npc" "r_268_Illegal nhvnativeesd device nhvnativeesd must not overlap diffcut" "r_267_Illegal nhvnativeesd device nhvnativeesd must not overlap diffres" |
| "r_266_Illegal nhvnativeesd device nhvnativeesd must not overlap tunm" "r_265_Illegal nhvnativeesd device nhvnativeesd must not overlap tap" "r_264_Illegal nhvnativeesd device nhvnativeesd must not overlap nwell" "r_263_Illegal nhvnativeesd device nhvnativeesd must not overlap ncm" "r_262_Illegal nhvesd device nhvesd must not overlap ldntm" |
| "r_261_Illegal nhvesd device nhvesd must not overlap PHdiodeID" "r_260_Illegal nhvesd device nhvesd must not overlap COREID" "r_259_Illegal nhvesd device nhvesd must not overlap DiodeID" "r_258_Illegal nhvesd device nhvesd must not overlap pnp" "r_257_Illegal nhvesd device nhvesd must not overlap lvtn" |
| "r_256_Illegal nhvesd device nhvesd must not overlap hvtp" "r_255_Illegal nhvesd device nhvesd must not overlap ENID" "r_254_Illegal nhvesd device nhvesd must not overlap LVID" "r_253_Illegal nhvesd device nhvesd must not overlap capacitor" "r_252_Illegal nhvesd device nhvesd must not overlap psdm" |
| "r_251_Illegal nhvesd device nhvesd must not overlap fuse" "r_250_Illegal nhvesd device nhvesd must not overlap li1cut" "r_249_Illegal nhvesd device nhvesd must not overlap li1res" "r_248_Illegal nhvesd device nhvesd must not overlap polycut" "r_247_Illegal nhvesd device nhvesd must not overlap polyres" |
| "r_246_Illegal nhvesd device nhvesd must not overlap npc" "r_245_Illegal nhvesd device nhvesd must not overlap diffcut" "r_244_Illegal nhvesd device nhvesd must not overlap diffres" "r_243_Illegal nhvesd device nhvesd must not overlap tunm" "r_242_Illegal nhvesd device nhvesd must not overlap tap" |
| "r_241_Illegal nhvesd device nhvesd must not overlap nwell" "r_240_Illegal nhvesd device nhvesd must not overlap ncm" "r_239_Illegal fnpass device fnpass must not overlap lvtn" "r_238_Illegal fnpass device fnpass must not overlap PHdiodeID" "r_237_Illegal fnpass device fnpass must not overlap ESDID" |
| "r_236_Illegal fnpass device fnpass must not overlap DiodeID" "r_235_Illegal fnpass device fnpass must not overlap pnp" "r_234_Illegal fnpass device fnpass must not overlap hvtp" "r_233_Illegal fnpass device fnpass must not overlap ENID" "r_232_Illegal fnpass device fnpass must not overlap LVID" |
| "r_231_Illegal fnpass device fnpass must not overlap capacitor" "r_230_Illegal fnpass device fnpass must not overlap fuse" "r_229_Illegal fnpass device fnpass must not overlap li1cut" "r_228_Illegal fnpass device fnpass must not overlap li1res" "r_227_Illegal fnpass device fnpass must not overlap polycut" |
| "r_226_Illegal fnpass device fnpass must not overlap polyres" "r_225_Illegal fnpass device fnpass must not overlap npc" "r_224_Illegal fnpass device fnpass must not overlap diffcut" "r_223_Illegal fnpass device fnpass must not overlap diffres" "r_222_Illegal fnpass device fnpass must not overlap tunm" |
| "r_221_Illegal fnpass device fnpass must not overlap tap" "r_220_Illegal fnpass device fnpass must not overlap nwell" "r_219_Illegal fnpass device fnpass must not overlap ncm" "r_218_Illegal ntvnative device ntvnative must not overlap ldntm" "r_217_Illegal ntvnative device ntvnative must not overlap PHdiodeID" |
| "r_216_Illegal ntvnative device ntvnative must not overlap ESDID" "r_215_Illegal ntvnative device ntvnative must not overlap COREID" "r_214_Illegal ntvnative device ntvnative must not overlap DiodeID" "r_213_Illegal ntvnative device ntvnative must not overlap pnp" "r_212_Illegal ntvnative device ntvnative must not overlap hvtp" |
| "r_211_Illegal ntvnative device ntvnative must not overlap ENID" "r_210_Illegal ntvnative device ntvnative must not overlap capacitor" "r_209_Illegal ntvnative device ntvnative must not overlap psdm" "r_208_Illegal ntvnative device ntvnative must not overlap fuse" "r_207_Illegal ntvnative device ntvnative must not overlap li1cut" |
| "r_206_Illegal ntvnative device ntvnative must not overlap li1res" "r_205_Illegal ntvnative device ntvnative must not overlap polycut" "r_204_Illegal ntvnative device ntvnative must not overlap polyres" "r_203_Illegal ntvnative device ntvnative must not overlap npc" "r_202_Illegal ntvnative device ntvnative must not overlap diffcut" |
| "r_201_Illegal ntvnative device ntvnative must not overlap diffres" "r_200_Illegal ntvnative device ntvnative must not overlap tunm" "r_199_Illegal ntvnative device ntvnative must not overlap tap" "r_198_Illegal ntvnative device ntvnative must not overlap nwell" "r_197_Illegal ntvnative device ntvnative must not overlap ncm" |
| "r_196_Illegal nhvnative device nhvnative10x4 must not overlap ldntm" "r_195_Illegal nhvnative device nhvnative10x4 must not overlap PHdiodeID" "r_194_Illegal nhvnative device nhvnative10x4 must not overlap ESDID" "r_193_Illegal nhvnative device nhvnative10x4 must not overlap COREID" "r_192_Illegal nhvnative device nhvnative10x4 must not overlap DiodeID" |
| "r_191_Illegal nhvnative device nhvnative10x4 must not overlap pnp" "r_190_Illegal nhvnative device nhvnative10x4 must not overlap hvtp" "r_189_Illegal nhvnative device nhvnative10x4 must not overlap ENID" "r_188_Illegal nhvnative device nhvnative10x4 must not overlap LVID" "r_187_Illegal nhvnative device nhvnative10x4 must not overlap psdm" |
| "r_186_Illegal nhvnative device nhvnative10x4 must not overlap fuse" "r_185_Illegal nhvnative device nhvnative10x4 must not overlap li1cut" "r_184_Illegal nhvnative device nhvnative10x4 must not overlap li1res" "r_183_Illegal nhvnative device nhvnative10x4 must not overlap polycut" "r_182_Illegal nhvnative device nhvnative10x4 must not overlap polyres" |
| "r_181_Illegal nhvnative device nhvnative10x4 must not overlap npc" "r_180_Illegal nhvnative device nhvnative10x4 must not overlap diffcut" "r_179_Illegal nhvnative device nhvnative10x4 must not overlap diffres" "r_178_Illegal nhvnative device nhvnative10x4 must not overlap tunm" "r_177_Illegal nhvnative device nhvnative10x4 must not overlap tap" |
| "r_176_Illegal nhvnative device nhvnative10x4 must not overlap nwell" "r_175_Illegal nhvnative device nhvnative10x4 must not overlap ncm" "r_174_Illegal nhvnative device nhvnativeNoCap must not overlap ldntm" "r_173_Illegal nhvnative device nhvnativeNoCap must not overlap PHdiodeID" "r_172_Illegal nhvnative device nhvnativeNoCap must not overlap ESDID" |
| "r_171_Illegal nhvnative device nhvnativeNoCap must not overlap COREID" "r_170_Illegal nhvnative device nhvnativeNoCap must not overlap DiodeID" "r_169_Illegal nhvnative device nhvnativeNoCap must not overlap pnp" "r_168_Illegal nhvnative device nhvnativeNoCap must not overlap hvtp" "r_167_Illegal nhvnative device nhvnativeNoCap must not overlap ENID" |
| "r_166_Illegal nhvnative device nhvnativeNoCap must not overlap LVID" "r_165_Illegal nhvnative device nhvnativeNoCap must not overlap capacitor" "r_164_Illegal nhvnative device nhvnativeNoCap must not overlap psdm" "r_163_Illegal nhvnative device nhvnativeNoCap must not overlap fuse" "r_162_Illegal nhvnative device nhvnativeNoCap must not overlap li1cut" |
| "r_161_Illegal nhvnative device nhvnativeNoCap must not overlap li1res" "r_160_Illegal nhvnative device nhvnativeNoCap must not overlap polycut" "r_159_Illegal nhvnative device nhvnativeNoCap must not overlap polyres" "r_158_Illegal nhvnative device nhvnativeNoCap must not overlap npc" "r_157_Illegal nhvnative device nhvnativeNoCap must not overlap diffcut" |
| "r_156_Illegal nhvnative device nhvnativeNoCap must not overlap diffres" "r_155_Illegal nhvnative device nhvnativeNoCap must not overlap tunm" "r_154_Illegal nhvnative device nhvnativeNoCap must not overlap tap" "r_153_Illegal nhvnative device nhvnativeNoCap must not overlap nwell" "r_152_Illegal nhvnative device nhvnativeNoCap must not overlap ncm" |
| "r_151_Illegal nhv device nhv must not overlap ldntm" "r_150_Illegal nhv device nhv must not overlap PHdiodeID" "r_149_Illegal nhv device nhv must not overlap COREID" "r_148_Illegal nhv device nhv must not overlap DiodeID" "r_147_Illegal nhv device nhv must not overlap pnp" |
| "r_146_Illegal nhv device nhv must not overlap lvtn" "r_145_Illegal nhv device nhv must not overlap hvtp" "r_144_Illegal nhv device nhv must not overlap ENID" "r_143_Illegal nhv device nhv must not overlap LVID" "r_142_Illegal nhv device nhv must not overlap capacitor" |
| "r_141_Illegal nhv device nhv must not overlap psdm" "r_140_Illegal nhv device nhv must not overlap fuse" "r_139_Illegal nhv device nhv must not overlap li1cut" "r_138_Illegal nhv device nhv must not overlap li1res" "r_137_Illegal nhv device nhv must not overlap polycut" |
| "r_136_Illegal nhv device nhv must not overlap polyres" "r_135_Illegal nhv device nhv must not overlap npc" "r_134_Illegal nhv device nhv must not overlap diffcut" "r_133_Illegal nhv device nhv must not overlap diffres" "r_132_Illegal nhv device nhv must not overlap tunm" |
| "r_131_Illegal nhv device nhv must not overlap tap" "r_130_Illegal nhv device nhv must not overlap nwell" "r_129_Illegal nhv device nhv must not overlap ncm" "r_128_Illegal sonos device sonos_e must not overlap PHdiodeID" "r_127_Illegal sonos device sonos_e must not overlap ESDID" |
| "r_126_Illegal sonos device sonos_e must not overlap DiodeID" "r_125_Illegal sonos device sonos_e must not overlap pnp" "r_124_Illegal sonos device sonos_e must not overlap hvi" "r_123_Illegal sonos device sonos_e must not overlap hvtp" "r_122_Illegal sonos device sonos_e must not overlap ENID" |
| "r_121_Illegal sonos device sonos_e must not overlap LVID" "r_120_Illegal sonos device sonos_e must not overlap capacitor" "r_119_Illegal sonos device sonos_e must not overlap psdm" "r_118_Illegal sonos device sonos_e must not overlap fuse" "r_117_Illegal sonos device sonos_e must not overlap li1cut" |
| "r_116_Illegal sonos device sonos_e must not overlap li1res" "r_115_Illegal sonos device sonos_e must not overlap polycut" "r_114_Illegal sonos device sonos_e must not overlap polyres" "r_113_Illegal sonos device sonos_e must not overlap npc" "r_112_Illegal sonos device sonos_e must not overlap diffcut" |
| "r_111_Illegal sonos device sonos_e must not overlap diffres" "r_110_Illegal sonos device sonos_e must not overlap tap" "r_109_Illegal sonos device sonos_e must not overlap nwell" "r_108_Illegal sonos device sonos_e must not overlap ncm" "r_107_Illegal nlowvt device nlowvt must not overlap ldntm" |
| "r_106_Illegal nlowvt device nlowvt must not overlap PHdiodeID" "r_105_Illegal nlowvt device nlowvt must not overlap ESDID" "r_104_Illegal nlowvt device nlowvt must not overlap COREID" "r_103_Illegal nlowvt device nlowvt must not overlap DiodeID" "r_102_Illegal nlowvt device nlowvt must not overlap pnp" |
| "r_101_Illegal nlowvt device nlowvt must not overlap hvi" "r_100_Illegal nlowvt device nlowvt must not overlap hvtp" "r_99_Illegal nlowvt device nlowvt must not overlap ENID" "r_98_Illegal nlowvt device nlowvt must not overlap LVID" "r_97_Illegal nlowvt device nlowvt must not overlap capacitor" |
| "r_96_Illegal nlowvt device nlowvt must not overlap psdm" "r_95_Illegal nlowvt device nlowvt must not overlap fuse" "r_94_Illegal nlowvt device nlowvt must not overlap li1cut" "r_93_Illegal nlowvt device nlowvt must not overlap li1res" "r_92_Illegal nlowvt device nlowvt must not overlap polycut" |
| "r_91_Illegal nlowvt device nlowvt must not overlap polyres" "r_90_Illegal nlowvt device nlowvt must not overlap npc" "r_89_Illegal nlowvt device nlowvt must not overlap diffcut" "r_88_Illegal nlowvt device nlowvt must not overlap diffres" "r_87_Illegal nlowvt device nlowvt must not overlap tunm" |
| "r_86_Illegal nlowvt device nlowvt must not overlap tap" "r_85_Illegal nlowvt device nlowvt must not overlap nwell" "r_84_Illegal nlowvt device nlowvt must not overlap ncm" "r_83_Illegal npass/npd device nshort_COREnew must not overlap ldntm" "r_82_Illegal npass/npd device nshort_COREnew must not overlap PHdiodeID" |
| "r_81_Illegal npass/npd device nshort_COREnew must not overlap ESDID" "r_80_Illegal npass/npd device nshort_COREnew must not overlap DiodeID" "r_79_Illegal npass/npd device nshort_COREnew must not overlap pnp" "r_78_Illegal npass/npd device nshort_COREnew must not overlap hvi" "r_77_Illegal npass/npd device nshort_COREnew must not overlap hvtp" |
| "r_76_Illegal npass/npd device nshort_COREnew must not overlap ENID" "r_75_Illegal npass/npd device nshort_COREnew must not overlap LVID" "r_74_Illegal npass/npd device nshort_COREnew must not overlap capacitor" "r_73_Illegal npass/npd device nshort_COREnew must not overlap psdm" "r_72_Illegal npass/npd device nshort_COREnew must not overlap fuse" |
| "r_71_Illegal npass/npd device nshort_COREnew must not overlap li1cut" "r_70_Illegal npass/npd device nshort_COREnew must not overlap li1res" "r_69_Illegal npass/npd device nshort_COREnew must not overlap polycut" "r_68_Illegal npass/npd device nshort_COREnew must not overlap polyres" "r_67_Illegal npass/npd device nshort_COREnew must not overlap npc" |
| "r_66_Illegal npass/npd device nshort_COREnew must not overlap diffcut" "r_65_Illegal npass/npd device nshort_COREnew must not overlap diffres" "r_64_Illegal npass/npd device nshort_COREnew must not overlap tunm" "r_63_Illegal npass/npd device nshort_COREnew must not overlap tap" "r_62_Illegal npass/npd device nshort_COREnew must not overlap nwell" |
| "r_61_Illegal npass/npd device nshort_COREnew must not overlap ncm" "r_60_Illegal npass/npd device nshort_COREorg must not overlap ldntm" "r_59_Illegal npass/npd device nshort_COREorg must not overlap PHdiodeID" "r_58_Illegal npass/npd device nshort_COREorg must not overlap ESDID" "r_57_Illegal npass/npd device nshort_COREorg must not overlap DiodeID" |
| "r_56_Illegal npass/npd device nshort_COREorg must not overlap pnp" "r_55_Illegal npass/npd device nshort_COREorg must not overlap hvi" "r_54_Illegal npass/npd device nshort_COREorg must not overlap lvtn" "r_53_Illegal npass/npd device nshort_COREorg must not overlap hvtp" "r_52_Illegal npass/npd device nshort_COREorg must not overlap ENID" |
| "r_51_Illegal npass/npd device nshort_COREorg must not overlap LVID" "r_50_Illegal npass/npd device nshort_COREorg must not overlap capacitor" "r_49_Illegal npass/npd device nshort_COREorg must not overlap psdm" "r_48_Illegal npass/npd device nshort_COREorg must not overlap fuse" "r_47_Illegal npass/npd device nshort_COREorg must not overlap li1cut" |
| "r_46_Illegal npass/npd device nshort_COREorg must not overlap li1res" "r_45_Illegal npass/npd device nshort_COREorg must not overlap polycut" "r_44_Illegal npass/npd device nshort_COREorg must not overlap polyres" "r_43_Illegal npass/npd device nshort_COREorg must not overlap npc" "r_42_Illegal npass/npd device nshort_COREorg must not overlap diffcut" |
| "r_41_Illegal npass/npd device nshort_COREorg must not overlap diffres" "r_40_Illegal npass/npd device nshort_COREorg must not overlap tunm" "r_39_Illegal npass/npd device nshort_COREorg must not overlap tap" "r_38_Illegal npass/npd device nshort_COREorg must not overlap nwell" "r_37_Illegal npass/npd device nshort_COREorg must not overlap ncm" |
| "r_36_Illegal nfet_01v8 device nshort_PERI must not overlap ldntm" "r_35_Illegal nfet_01v8 device nshort_PERI must not overlap PHdiodeID" "r_34_Illegal nfet_01v8 device nshort_PERI must not overlap DiodeID" "r_33_Illegal nfet_01v8 device nshort_PERI must not overlap pnp" "r_32_Illegal nfet_01v8 device nshort_PERI must not overlap hvi" |
| "r_31_Illegal nfet_01v8 device nshort_PERI must not overlap lvtn" "r_30_Illegal nfet_01v8 device nshort_PERI must not overlap hvtp" "r_29_Illegal nfet_01v8 device nshort_PERI must not overlap ENID" "r_28_Illegal nfet_01v8 device nshort_PERI must not overlap LVID" "r_27_Illegal nfet_01v8 device nshort_PERI must not overlap capacitor" |
| "r_26_Illegal nfet_01v8 device nshort_PERI must not overlap psdm" "r_25_Illegal nfet_01v8 device nshort_PERI must not overlap fuse" "r_24_Illegal nfet_01v8 device nshort_PERI must not overlap li1cut" "r_23_Illegal nfet_01v8 device nshort_PERI must not overlap li1res" "r_22_Illegal nfet_01v8 device nshort_PERI must not overlap polycut" |
| "r_21_Illegal nfet_01v8 device nshort_PERI must not overlap polyres" "r_20_Illegal nfet_01v8 device nshort_PERI must not overlap npc" "r_19_Illegal nfet_01v8 device nshort_PERI must not overlap diffcut" "r_18_Illegal nfet_01v8 device nshort_PERI must not overlap diffres" "r_17_Illegal nfet_01v8 device nshort_PERI must not overlap tunm" |
| "r_16_Illegal nfet_01v8 device nshort_PERI must not overlap tap" "r_15_Illegal nfet_01v8 device nshort_PERI must not overlap nwell" "r_14_Illegal nfet_01v8 device nshort_PERI must not overlap ncm" "r_13_Illegal nlvtpass device" "r_12_Illegal nlvtpass device" |
| "r_11_Illegal nlvtpass device" "r_10_Illegal npass/npd device" "r_9_Illegal npass/npd device" "r_8_Illegal fnpass device" "r_7_Illegal fnpass device" |
| "r_6_Illegal fnpass device" "r_5_Illegal fnpass device" "r_4_Illegal ppu device" "r_3_Illegal ppu device" "r_2_Illegal ppu device" |
| "r_1_Illegal ppu device" "r_0_Illegal ppu device" |
| |
| GROUP keepLayers "k_0_dnwelldg" |
| |
| /// To remove this when there are no rules checked, |
| /// pass ?dontCheckUnregisteredRules t to (CALdone) |
| |
| GROUP unRegisteredErrors "?" |
| |
| // end GROUPs |
| |
| /// VIA REDUCTION OPTIONS |
| PEX REDUCE VIA RESISTANCE FLEXIBLE |
| ERC SELECT CHECK drcErrors |
| /// To remove this when there are no rules checked, |
| /// pass ?dontCheckUnregisteredRules t to (CALdone) |
| ERC SELECT CHECK unRegisteredErrors |
| DRC SELECT CHECK keepLayers |
| ERC UNSELECT CHECK keepLayers |
| DRC CHECK MAP keepLayers |
| ASCII "keepLayer.db" |
| MAXIMUM RESULTS ALL |
| |
| /// --BEGIN AGDS TABLE-- |
| /// AGDSPURPOSE MET1_cshield none |
| /// AGDSPURPOSE MET1_cshield none |
| /// AGDSPURPOSE MET2_cshield none |
| /// AGDSPURPOSE MET2_cshield none |
| /// AGDSPURPOSE MET2_cshield none |
| /// AGDSPURPOSE MET3_cshield none |
| /// AGDSPURPOSE MET3_cshield none |
| /// AGDSPURPOSE MET3_cshield none |
| /// AGDSPURPOSE MET3_cshield none |
| /// AGDSPURPOSE MET4_cshield none |
| /// AGDSPURPOSE MET4_cshield none |
| /// AGDSPURPOSE MET4_cshield none |
| /// AGDSPURPOSE MET4_cshield none |
| /// AGDSPURPOSE MET4_cshield none |
| /// AGDSPURPOSE MET5_cshield none |
| /// AGDSPURPOSE MET5_cshield none |
| /// AGDSPURPOSE MET5_cshield none |
| /// AGDSPURPOSE MET5_cshield none |
| /// AGDSPURPOSE MET5_cshield none |
| /// AGDSPURPOSE MET5_cshield none |
| /// AGDSPURPOSE LI1_cshield none |
| /// AGDSPURPOSE MET5_cshield none |
| /// AGDSPURPOSE MET4_cshield none |
| /// AGDSPURPOSE MET3_cshield none |
| /// AGDSPURPOSE MET2_cshield none |
| /// AGDSPURPOSE MET1_cshield none |
| /// AGDSPURPOSE LI1_cshield none |
| /// AGDSCONT PAD_cond MET5_cond |
| /// AGDSCONT RDL_cond MET5_cond rdlcon |
| /// AGDSPURPOSE rdlcon via |
| /// AGDSCONT RDL_cond MET5_rdl rdl_MET5 |
| /// AGDSPURPOSE rdl_MET5 via |
| /// AGDSCONT MET5_cond MET4_cond via4 |
| /// AGDSCONT MET5_cond MET4_cond_nrc_temp via4 |
| /// AGDSCONT MET5_cond_nrc_temp MET4_cond via4 |
| /// AGDSCONT MET5_cond_nrc_temp MET4_cond_nrc_temp via4 |
| /// AGDSPURPOSE via4 via |
| /// AGDSCONT MET4_cond MET3_cond via3 |
| /// AGDSCONT MET4_cond MET3_cond_nrc via3 |
| /// AGDSCONT MET4_cond_nrc MET3_cond via3 |
| /// AGDSCONT MET4_cond_nrc MET3_cond_nrc via3 |
| /// AGDSPURPOSE via3 via |
| /// AGDSCONT MET3_cond MET2_cond via2 |
| /// AGDSCONT MET3_cond MET2_cond_nrc via2 |
| /// AGDSCONT MET3_cond_nrc MET2_cond via2 |
| /// AGDSCONT MET3_cond_nrc MET2_cond_nrc via2 |
| /// AGDSPURPOSE via2 via |
| /// AGDSCONT MET2_cond MET1_cond via |
| /// AGDSCONT MET2_cond MET1_cond_nrc via |
| /// AGDSCONT MET2_cond_nrc MET1_cond via |
| /// AGDSCONT MET2_cond_nrc MET1_cond_nrc via |
| /// AGDSPURPOSE via via |
| /// AGDSCONT MET1_cond LI1_cond mcon |
| /// AGDSCONT MET1_cond LI1_cond_nrc mcon |
| /// AGDSCONT MET1_cond_nrc LI1_cond mcon |
| /// AGDSCONT MET1_cond_nrc LI1_cond_nrc mcon |
| /// AGDSPURPOSE mcon via |
| /// AGDSCONT LI1_cond POLY_cond licon1_POLY |
| /// AGDSCONT LI1_cond POLY_cond_nrc licon1_POLY |
| /// AGDSCONT LI1_cond_nrc POLY_cond licon1_POLY |
| /// AGDSCONT LI1_cond_nrc POLY_cond_nrc licon1_POLY |
| /// AGDSPURPOSE licon1_POLY via |
| /// AGDSCONT LI1_cond NPNDIFF_cond licon1_NPNDIFF |
| /// AGDSPURPOSE licon1_NPNDIFF via |
| /// AGDSCONT LI1_cond PNPDIFF_cond licon1_PNPDIFF |
| /// AGDSPURPOSE licon1_PNPDIFF via |
| /// AGDSCONT LI1_cond PTAP_notbjt_cond licon1_PTAP_notbjt |
| /// AGDSCONT LI1_cond_nrc PTAP_notbjt_cond licon1_PTAP_notbjt |
| /// AGDSPURPOSE licon1_PTAP_notbjt via |
| /// AGDSCONT LI1_cond NTAP_notbjt_cond licon1_NTAP_notbjt |
| /// AGDSCONT LI1_cond_nrc NTAP_notbjt_cond licon1_NTAP_notbjt |
| /// AGDSPURPOSE licon1_NTAP_notbjt via |
| /// AGDSCONT LI1_cond PTAP_NotDnwell_cond licon1_PTAP_notDnwell |
| /// AGDSPURPOSE licon1_PTAP_notDnwell via |
| /// AGDSCONT LI1_cond PTAP_npn_cond licon1_PTAP_npn |
| /// AGDSPURPOSE licon1_PTAP_npn via |
| /// AGDSCONT LI1_cond PTAP_pnp_cond licon1_PTAP_pnp |
| /// AGDSPURPOSE licon1_PTAP_pnp via |
| /// AGDSCONT LI1_cond NTAP_npn_cond licon1_NTAP_npn |
| /// AGDSPURPOSE licon1_NTAP_npn via |
| /// AGDSCONT LI1_cond NTAP_pnp_cond licon1_NTAP_pnp |
| /// AGDSPURPOSE licon1_NTAP_pnp via |
| /// AGDSCONT LI1_cond PDIFF_cond licon1_PDIFF |
| /// AGDSCONT LI1_cond_nrc PDIFF_cond licon1_PDIFF |
| /// AGDSPURPOSE licon1_PDIFF via |
| /// AGDSCONT LI1_cond NDIFF_cond licon1_NDIFF |
| /// AGDSCONT LI1_cond_nrc NDIFF_cond licon1_NDIFF |
| /// AGDSPURPOSE licon1_NDIFF via |
| /// AGDSCONT PFOM_cond PTAP_NotDnwell_cond |
| /// AGDSCONT PFOM_cond PTAP_notbjt_cond |
| /// AGDSCONT PFOM_cond PTAP_pnp_cond |
| /// AGDSCONT PFOM_cond PDIFF_cond |
| /// AGDSCONT NFOM_cond NTAP_notbjt_cond |
| /// AGDSCONT NFOM_cond NTAP_pnp_cond |
| /// AGDSCONT NFOM_cond NDIFF_cond |
| /// AGDSCONT MosNwell pwresBiasTerm_cond |
| /// AGDSCONT MosNwell DNWELL_cond DNWELL_cont |
| /// AGDSPURPOSE DNWELL_cont via |
| /// AGDSCONT NTAP_notbjt_cond MosNwell NTAP_notbjt_cont |
| /// AGDSPURPOSE NTAP_notbjt_cont via |
| /// AGDSCONT NTAP_npn_cond NpnNwell NTAP_npn_cont |
| /// AGDSPURPOSE NTAP_npn_cont via |
| /// AGDSCONT NTAP_pnp_cond PnpNwell NTAP_pnp_cont |
| /// AGDSPURPOSE NTAP_pnp_cont via |
| /// AGDSCONT PTAP_NotDnwell_cond Substrate PTAP_NotDnwell_cont |
| /// AGDSPURPOSE PTAP_NotDnwell_cont via |
| /// AGDSCONT PTAP_notbjt_cond Substrate PTAP_notbjt_cont |
| /// AGDSPURPOSE PTAP_notbjt_cont via |
| /// AGDSCONT PTAP_npn_cond Substrate PTAP_npn_cont |
| /// AGDSPURPOSE PTAP_npn_cont via |
| /// AGDSCONT PTAP_pnp_cond Substrate PTAP_pnp_cont |
| /// AGDSPURPOSE PTAP_pnp_cont via |
| /// AGDSCONT Substrate SubstrateIso |
| /// AGDSCONT BulkTermCap_condVpp_M4 NpnNwell CAP3_Well_contVpp |
| /// AGDSCONT BulkTermCap_condVpp_M4 PnpNwell CAP3_Well_contVpp |
| /// AGDSCONT BulkTermCap_condVpp_M4 MosNwell CAP3_Well_contVpp |
| /// AGDSPURPOSE CAP3_Well_contVpp via |
| /// AGDSCONT BulkTermCap_condVpp_M4 Substrate CAP3_NoWell_contVpp |
| /// AGDSPURPOSE CAP3_NoWell_contVpp via |
| /// AGDSCONT BulkTermCap_condVpp_M5 NpnNwell CAP3_Well_contVpp |
| /// AGDSCONT BulkTermCap_condVpp_M5 PnpNwell CAP3_Well_contVpp |
| /// AGDSCONT BulkTermCap_condVpp_M5 MosNwell CAP3_Well_contVpp |
| /// AGDSPURPOSE CAP3_Well_contVpp via |
| /// AGDSCONT BulkTermCap_condVpp_M5 Substrate CAP3_NoWell_contVpp |
| /// AGDSPURPOSE CAP3_NoWell_contVpp via |
| /// AGDSCONT BulkTermCap_condVpp NpnNwell CAP3_Well_contVpp |
| /// AGDSCONT BulkTermCap_condVpp PnpNwell CAP3_Well_contVpp |
| /// AGDSCONT BulkTermCap_condVpp MosNwell CAP3_Well_contVpp |
| /// AGDSPURPOSE CAP3_Well_contVpp via |
| /// AGDSCONT BulkTermCap_condVpp Substrate CAP3_NoWell_contVpp |
| /// AGDSPURPOSE CAP3_NoWell_contVpp via |
| /// AGDSCONT BulkTermCapMos_cond POLY_cond_nrc CAP3_WellMos_cont |
| /// AGDSPURPOSE CAP3_WellMos_cont via |
| /// AGDSCONT BulkTermCapMos_cond POLY_cond_nrc CAP3_NoWellMos_cont |
| /// AGDSPURPOSE CAP3_NoWellMos_cont via |
| /// AGDSCONT BulkTermCap_cond NpnNwell CAP3_Well_cont |
| /// AGDSCONT BulkTermCap_cond PnpNwell CAP3_Well_cont |
| /// AGDSCONT BulkTermCap_cond MosNwell CAP3_Well_cont |
| /// AGDSPURPOSE CAP3_Well_cont via |
| /// AGDSCONT BulkTermCap_cond Substrate CAP3_NoWell_cont |
| /// AGDSPURPOSE CAP3_NoWell_cont via |
| /// AGDSPURPOSE GATE_shield none |
| /// AGDSPURPOSE RDL_gshield_upp none |
| /// AGDSPURPOSE RDL_gshield_low none |
| /// AGDSPURPOSE MET5_gshield_upp none |
| /// AGDSPURPOSE MET5_gshield_low none |
| /// AGDSPURPOSE MET4_gshield_upp none |
| /// AGDSPURPOSE MET4_gshield_low none |
| /// AGDSPURPOSE MET3_gshield_upp none |
| /// AGDSPURPOSE MET3_gshield_low none |
| /// AGDSPURPOSE MET2_gshield_upp none |
| /// AGDSPURPOSE MET2_gshield_low none |
| /// AGDSPURPOSE MET1_gshield_upp none |
| /// AGDSPURPOSE MET1_gshield_low none |
| /// AGDSPURPOSE LI1_gshield_upp none |
| /// AGDSPURPOSE LI1_gshield_low none |
| /// AGDSPURPOSE POLY_gshield_upp none |
| /// AGDSPURPOSE POLY_gshield_low none |
| /// AGDSSTACKUP rdl_pin RDL_cond |
| /// AGDSPURPOSE rdl_pin pin none |
| /// AHFPROCMAP RDL_cond_nrc none |
| /// AHFPROCMAP RDL_cond none |
| /// AGDSPURPOSE RDL_cond_nrc none |
| /// AGDSPURPOSE RDL_cond none |
| /// AGDSSTACKUP pad_pin PAD_cond |
| /// AGDSPURPOSE pad_pin pin none |
| /// AHFPROCMAP PAD_cond none |
| /// AGDSPURPOSE PAD_cond none |
| /// AGDSSTACKUP met5_pin MET5_cond |
| /// AGDSPURPOSE met5_pin pin none |
| /// AHFPROCMAP MET5_cond_nrc none |
| /// AHFPROCMAP MET5_cond none |
| /// AGDSPURPOSE MET5_cond_nrc none |
| /// AGDSPURPOSE MET5_cond none |
| /// AGDSSTACKUP met4_pin MET4_cond |
| /// AGDSPURPOSE met4_pin pin none |
| /// AHFPROCMAP MET4_cond_nrc none |
| /// AHFPROCMAP MET4_cond none |
| /// AGDSPURPOSE MET4_cond_nrc none |
| /// AGDSPURPOSE MET4_cond none |
| /// AGDSSTACKUP met3_pin MET3_cond |
| /// AGDSPURPOSE met3_pin pin none |
| /// AHFPROCMAP MET3_cond_nrc none |
| /// AHFPROCMAP MET3_cond none |
| /// AGDSPURPOSE MET3_cond_nrc none |
| /// AGDSPURPOSE MET3_cond none |
| /// AGDSSTACKUP met2_pin MET2_cond |
| /// AGDSPURPOSE met2_pin pin none |
| /// AHFPROCMAP MET2_cond_nrc none |
| /// AHFPROCMAP MET2_cond none |
| /// AGDSPURPOSE MET2_cond_nrc none |
| /// AGDSPURPOSE MET2_cond none |
| /// AGDSSTACKUP met1_pin MET1_cond |
| /// AGDSPURPOSE met1_pin pin none |
| /// AHFPROCMAP MET1_cond_nrc none |
| /// AHFPROCMAP MET1_cond none |
| /// AGDSPURPOSE MET1_cond_nrc none |
| /// AGDSPURPOSE MET1_cond none |
| /// AGDSSTACKUP li1_pin LI1_cond |
| /// AGDSPURPOSE li1_pin pin none |
| /// AHFPROCMAP LI1_cond_nrc none |
| /// AHFPROCMAP LI1_cond none |
| /// AGDSPURPOSE LI1_cond_nrc none |
| /// AGDSPURPOSE LI1_cond none |
| /// AGDSSTACKUP poly_pin POLY_cond |
| /// AGDSPURPOSE poly_pin pin none |
| /// AHFPROCMAP POLY_cond_nrc none |
| /// AHFPROCMAP POLY_cond none |
| /// AGDSPURPOSE POLY_cond_nrc none |
| /// AGDSPURPOSE POLY_cond none |
| /// AHFPROCMAP BulkTermCap_condVpp_M4 none |
| /// AGDSPURPOSE BulkTermCap_condVpp_M4 none |
| /// AHFPROCMAP BulkTermCap_condVpp_M5 none |
| /// AGDSPURPOSE BulkTermCap_condVpp_M5 none |
| /// AHFPROCMAP BulkTermCap_condVpp none |
| /// AGDSPURPOSE BulkTermCap_condVpp none |
| /// AHFPROCMAP BulkTermCapMos_cond none |
| /// AGDSPURPOSE BulkTermCapMos_cond none |
| /// AHFPROCMAP BulkTermCap_cond none |
| /// AGDSPURPOSE BulkTermCap_cond none |
| /// AHFPROCMAP NTAP_notbjt_cond none |
| /// AGDSPURPOSE NTAP_notbjt_cond none |
| /// AHFPROCMAP NTAP_npn_cond none |
| /// AGDSPURPOSE NTAP_npn_cond none |
| /// AHFPROCMAP NTAP_pnp_cond none |
| /// AGDSPURPOSE NTAP_pnp_cond none |
| /// AHFPROCMAP PTAP_NotDnwell_cond none |
| /// AGDSPURPOSE PTAP_NotDnwell_cond none |
| /// AHFPROCMAP PTAP_notbjt_cond none |
| /// AGDSPURPOSE PTAP_notbjt_cond none |
| /// AHFPROCMAP PTAP_npn_cond none |
| /// AGDSPURPOSE PTAP_npn_cond none |
| /// AHFPROCMAP PTAP_pnp_cond none |
| /// AGDSPURPOSE PTAP_pnp_cond none |
| /// AGDSSTACKUP diff_pin NPNDIFF_cond |
| /// AGDSPURPOSE diff_pin pin none |
| /// AHFPROCMAP NPNDIFF_cond none |
| /// AGDSPURPOSE NPNDIFF_cond none |
| /// AGDSSTACKUP diff_pin PNPDIFF_cond |
| /// AGDSPURPOSE diff_pin pin none |
| /// AHFPROCMAP PNPDIFF_cond none |
| /// AGDSPURPOSE PNPDIFF_cond none |
| /// AGDSSTACKUP diff_pin NDIFF_cond |
| /// AGDSPURPOSE diff_pin pin none |
| /// AHFPROCMAP NDIFF_cond none |
| /// AGDSPURPOSE NDIFF_cond none |
| /// AGDSSTACKUP diff_pin PDIFF_cond |
| /// AGDSPURPOSE diff_pin pin none |
| /// AHFPROCMAP PDIFF_cond none |
| /// AGDSPURPOSE PDIFF_cond none |
| /// AHFPROCMAP pwresBiasTerm_cond none |
| /// AGDSPURPOSE pwresBiasTerm_cond none |
| /// AGDSSTACKUP nwell_pin NpnNwell |
| /// AGDSPURPOSE nwell_pin pin none |
| /// AHFPROCMAP NpnNwell none |
| /// AGDSPURPOSE NpnNwell none |
| /// AGDSSTACKUP nwell_pin PnpNwell |
| /// AGDSPURPOSE nwell_pin pin none |
| /// AHFPROCMAP PnpNwell none |
| /// AGDSPURPOSE PnpNwell none |
| /// AGDSSTACKUP nwell_pin MosNwell |
| /// AGDSPURPOSE nwell_pin pin none |
| /// AHFPROCMAP MosNwell none |
| /// AGDSPURPOSE MosNwell none |
| /// AHFPROCMAP DNWELL_cond none |
| /// AGDSPURPOSE DNWELL_cond none |
| /// AGDSSTACKUP pwelliso_pin SubstrateIso |
| /// AGDSPURPOSE pwelliso_pin pin none |
| /// AHFPROCMAP SubstrateIso none |
| /// AGDSPURPOSE SubstrateIso none |
| /// AGDSSTACKUP pwell_pin Substrate |
| /// AGDSPURPOSE pwell_pin pin none |
| /// AHFPROCMAP Substrate none |
| /// AGDSPURPOSE Substrate none |
| /// DEV RESISTOR q0metop8 metop8 MET3_cond |
| /// DEV RESISTOR q0metop7 metop7 MET3_cond |
| /// DEV RESISTOR q0metop6 metop6 MET3_cond |
| /// DEV RESISTOR q0metop5 metop5 MET3_cond |
| /// DEV RESISTOR q0metop4 metop4 MET3_cond |
| /// DEV RESISTOR q0metop3 metop3 MET3_cond |
| /// DEV RESISTOR q0metop2 metop2 MET3_cond |
| /// DEV RESISTOR q0metop1 metop1 MET3_cond |
| /// DEV RESISTOR m4fuse fuse MET4_cond |
| /// DEV RESISTOR rdshort short RDL_cond |
| /// DEV RESISTOR m5short short MET5_cond |
| /// DEV RESISTOR m4short short MET4_cond |
| /// DEV RESISTOR m3short short MET3_cond |
| /// DEV RESISTOR m2short short MET2_cond |
| /// DEV RESISTOR m1short short MET1_cond |
| /// DEV RESISTOR lishort short LI1_cond |
| /// DEV RESISTOR pyshort short POLY_cond |
| /// DEV RESISTOR mrpw xpwres SubstrateIso |
| /// DEV RESISTOR xhrpoly_5p73_sub xhrpoly_5p73 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_2p85_sub xhrpoly_2p85 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_1p41_sub xhrpoly_1p41 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_0p69_sub xhrpoly_0p69 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_0p35_sub xhrpoly_0p35 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_5p73_nwell xhrpoly_5p73 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_2p85_nwell xhrpoly_2p85 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_1p41_nwell xhrpoly_1p41 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_0p69_nwell xhrpoly_0p69 POLY_cond_nrc |
| /// DEV RESISTOR xhrpoly_0p35_nwell xhrpoly_0p35 POLY_cond_nrc |
| /// DEV RESISTOR mrl1 mrl1 LI1_cond |
| /// DEV RESISTOR mrp1 mrp1 POLY_cond |
| /// DEV RESISTOR mrdp_hv mrdp_hv PDIFF_cond |
| /// DEV RESISTOR mrdp_lv mrdp PDIFF_cond |
| /// DEV RESISTOR mrdn_hv mrdn_hv NDIFF_cond |
| /// DEV RESISTOR mrdn_lv mrdn NDIFF_cond |
| /// DEV INDUCTOR xind4 xind4 (ind4T1_met5 ind4T2_met5 ind4Center_met3 ind4Shield) |
| /// DEV INDUCTOR xind4 xind4 (ind4T1_rdl ind4T2_rdl ind4Center_met5 ind4Shield) |
| /// DEV INDUCTOR xind4 xind4 (ind4T1_rdl ind4T2_rdl ind4Center_rdl ind4Shield) |
| /// DEV CAP cap35fF xcmvpp3 (vppTermBB vppTermBB BulkTermCap_condVpp) |
| /// DEV CAP cap10fF xcmvpp4 (vppTermBB vppTermBB BulkTermCap_condVpp) |
| /// DEV CAP cap5fF xcmvpp5 (vppTermBB vppTermBB BulkTermCap_condVpp) |
| /// DEV CAP cap12fF_noShield xcmvpp4p4x4p6_m1m2 (vppTermBB vppTermBB BulkTermCap_condVpp) |
| /// DEV CAP cap100fF_m1m2 xcmvpp11p5x11p7_m1m2 (vppTermBB vppTermBB BulkTermCap_condVpp) |
| /// DEV CAP cap100fF_m3m4 xcmvpp11p5x11p7_m1m4 (vppTermM1_M5 vppTermM1_M5 BulkTermCap_condVpp) |
| /// DEV CAP cap100fF_mm5shield xcmvpp11p5x11p7_m1m4m5shield (vppTermM1_M5 vppTermM1_M5 BulkTermCap_condVpp_M5 topMetVpp_M5) |
| /// DEV CAP cap1fF xcmvpp1p8x1p8_m3shield (vppTermli1 vppTermNoli1 BulkTermCap_condVpp topMetVpp) |
| /// DEV CAP cap12fF xcmvpp4p4x4p6_m3shield (vppTermpoly vppTermNopoly BulkTermCap_condVpp topMetVpp) |
| /// DEV CAP cap50fF xcmvpp8p6x7p9_m3shield (vppTermpoly vppTermNopoly BulkTermCap_condVpp topMetVpp) |
| /// DEV CAP cap100fF xcmvpp11p5x11p7_m3shield (vppTermpoly vppTermNopoly BulkTermCap_condVpp topMetVpp) |
| /// DEV CAP cap100fF_liShield xcmvpp11p5x11p7_m3_lishield (vppTermli1 vppTermNoli1 BulkTermCap_condVpp) |
| /// DEV CAP cap50fF_liShield xcmvpp8p6x7p9_m3_lishield (vppTermli1 vppTermNoli1 BulkTermCap_condVpp) |
| /// DEV CAP cap12fF_liShield xcmvpp4p4x4p6_m3_lishield (vppTermli1 vppTermNoli1 BulkTermCap_condVpp) |
| /// DEV CAP cap1fF_liShield xcmvpp1p8x1p8 (vppTermli1 vppTermNoli1 BulkTermCap_condVpp) |
| /// DEV CAP vppM4shield1 xcmvpp11p5x11p7_m4shield (vppTermli1_M4 vppTermli1_M4 BulkTermCap_condVpp_M4 topMetVpp_M4) |
| /// DEV CAP vppM4shield2 xcmvpp11p5x11p7_polym4shield (vppTermpoly_M4 vppTermNopoly_M4 BulkTermCap_condVpp_M4 topMetVpp_M4) |
| /// DEV CAP vppM4shield3 xcmvpp6p8x6p1_polym4shield (vppTermpoly_M4 vppTermNopoly_M4 BulkTermCap_condVpp_M4 topMetVpp_M4) |
| /// DEV CAP vppM4shield4 xcmvpp6p8x6p1_lim4shield (vppTermli1_M4 vppTermM1_M4 BulkTermCap_condVpp_M4 topMetVpp_M4) |
| /// DEV CAP cap140fF_1 xcmvpp11p5x11p7_m5shield (vppTermli1_M5 vppTermli1_M5 BulkTermCap_condVpp_M5 topMetVpp_M5) |
| /// DEV CAP cap140fF_2 xcmvpp11p5x11p7_polym5shield (vppTermpoly_M5 vppTermNopoly_M5 BulkTermCap_condVpp_M5 topMetVpp_M5) |
| /// DEV CAP cap140fF_3 xcmvpp11p5x11p7_lim5shield (vppTermli1_M5 vppTermM1_M5 BulkTermCap_condVpp_M5 topMetVpp_M5) |
| /// DEV CAP cap140fF_4 xcmvpp8p6x7p9_m3_lim5shield (vppTermli1_M5_noM4 vppTermM1_M5_noM4 BulkTermCap_condVpp_M5 topMetVpp_M5) |
| /// DEV CAP cap140fF_5 xcmvpp11p5x11p7_m3_lim5shield (vppTermli1_M5_noM4 vppTermM1_M5_noM4 BulkTermCap_condVpp_M5 topMetVpp_M5) |
| /// DEV CAP cap140fF_6 xcmvpp4p4x4p6_m3_lim5shield (vppTermli1_M5_noM4 vppTermM1_M5_noM4 BulkTermCap_condVpp_M5 topMetVpp_M5) |
| /// DEV CAP cap140fF_7 xcmvpp11p5x11p7_polym50p4shield (vppTermpoly_M5 vppTermNoPoly_M5 BulkTermCap_condVpp_M5 topMetVpp_M5_shrunk) |
| /// DEV CAP vppcapNHVnative xcmvppx4_2xnhvnative10x4 (vppTermpoly_M5 vppTermNopoly_M5 BulkTermCap_condVpp_M5 topMetVpp_M5) |
| /// DEV CAP vppcap_hd5_a xcmvpp_hd5_1x1 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_b xcmvpp_hd5_1x2 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_c xcmvpp_hd5_2x1 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_d xcmvpp_hd5_2x2 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_e xcmvpp_hd5_3x1 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_f xcmvpp_hd5_3x2 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_g xcmvpp_hd5_4x1 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_h xcmvpp_hd5_4x2 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_i xcmvpp_hd5_5x1 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_j xcmvpp_hd5_5x1_met5pullin (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_k xcmvpp_hd5_5x2 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_l xcmvpp_hd5_5x2_met5pullin (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_m xcmvpp_hd5_atlas_fingercap_l5 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_n xcmvpp_hd5_atlas_fingercap_l10 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_o xcmvpp_hd5_atlas_fingercap_l20 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_p xcmvpp_hd5_atlas_fingercap_l40 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_q xcmvpp_hd5_atlas_wafflecap1 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_r xcmvpp_hd5_atlas_wafflecap2 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP vppcap_hd5_s xcmvpp_hd5_atlas_fingercap2_l5 (vppTerm_classN vppTerm_classN BulkTermCap_condVpp_M5) |
| /// DEV CAP xcmvpp_2phv xcmvpp2_phv5x4 (vppTermBBMos vppTermBBMos BulkTermCapMos_cond) |
| /// DEV CAP xcmvpp_2nhvnative xcmvpp2_nhvnative10x4 (vppTermBBMos vppTermBBMos BulkTermCapMos_cond) |
| /// DEV CAP xcmvpp_2 xcmvpp_2 (vppTermBB vppTermBB BulkTermCap_cond) |
| /// DEV CAP xcmvpp xcmvpp (vppTermBB vppTermBB BulkTermCap_cond) |
| /// DEV DIODE pwDioHV300 xesd_ndiode_h_dnwl_300 SubstrateIso NDIFF_cond |
| /// DEV DIODE pwDioHV200 xesd_ndiode_h_dnwl_200 SubstrateIso NDIFF_cond |
| /// DEV DIODE pwDioHV100 xesd_ndiode_h_dnwl_100 SubstrateIso NDIFF_cond |
| /// DEV DIODE photoDiode dnwdiode_psub SubstrateSpecial DNWELL_cond |
| /// DEV DIODE pDioHV300 xesd_pdiode_h_300 PDIFF_cond MosNwell |
| /// DEV DIODE pDioHV200 xesd_pdiode_h_200 PDIFF_cond MosNwell |
| /// DEV DIODE pDioHV100 xesd_pdiode_h_100 PDIFF_cond MosNwell |
| /// DEV DIODE pDiodeHV pdiode_h PDIFF_cond MosNwell |
| /// DEV DIODE pDiode pdiode PDIFF_cond MosNwell |
| /// DEV DIODE nDioHV300 xesd_ndiode_h_300 Substrate NDIFF_cond |
| /// DEV DIODE nDioHV200 xesd_ndiode_h_200 Substrate NDIFF_cond |
| /// DEV DIODE nDioHV100 xesd_ndiode_h_100 Substrate NDIFF_cond |
| /// DEV DIODE nDiodeHV ndiode_h Substrate NDIFF_cond |
| /// DEV DIODE diode_pw2nd_05v5 diode_pw2nd_05v5 Substrate NDIFF_cond |
| /// DEV BJT pnppar5x pnppar5x PTAP_pnp_cond PnpNwell PNPDIFF_cond |
| /// DEV BJT pnppar1x pnppar PTAP_pnp_cond PnpNwell PNPDIFF_cond |
| /// DEV BJT npn_1x1_2p0_HV npn_1x1_2p0_hv NTAP_npn_cond PTAP_npn_cond NPNDIFF_cond |
| /// DEV BJT npnpar1x2 npnpar1x2 NTAP_npn_cond PTAP_npn_cond NPNDIFF_cond |
| /// DEV BJT npnpar1x1 npnpar1x1 NTAP_npn_cond PTAP_npn_cond NPNDIFF_cond |
| /// AGDSCONT Substrate SubstrateNpn |
| /// DEV CAP xchvnwc xchvnwc (POLY_cond_nrc NTAP_notbjt_cond Substrate) |
| /// DEV CAP xcnwvc2 xcnwvc2 (POLY_cond_nrc NTAP_notbjt_cond Substrate) |
| /// DEV CAP xcnwvc xcnwvc (POLY_cond_nrc NTAP_notbjt_cond Substrate) |
| /// DEV MOSFET phvesdnormGate phvesd POLY_cond PFOM_cond MosNwell |
| /// DEV MOSFET phvesdwaffleCap phvesd POLY_cond PFOM_cond MosNwell |
| /// DEV MOSFET phvesddrainOnly phvesd POLY_cond PFOM_cond MosNwell |
| /// DEV MOSFET phvesdhalfFieldless phvesd POLY_cond PFOM_cond MosNwell |
| /// DEV MOSFET phvesdfixedBlackBox phvesd POLY_cond PFOM_cond MosNwell |
| /// DEV MOSFET nhvnativeesdnormGate nhvnativeesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvnativeesdwaffleCap nhvnativeesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvnativeesddrainOnly nhvnativeesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvnativeesdhalfFieldless nhvnativeesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvnativeesdfixedBlackBox nhvnativeesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvesdnormGate nhvesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvesdwaffleCap nhvesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvesddrainOnly nhvesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvesdhalfFieldless nhvesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nhvesdfixedBlackBox nhvesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nshortesdnormGate nshortesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nshortesdwaffleCap nshortesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nshortesddrainOnly nshortesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nshortesdhalfFieldless nshortesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET nshortesdfixedBlackBox nshortesd POLY_cond NFOM_cond Substrate |
| /// DEV MOSFET phvnormGate phv POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phvwaffleCap phv POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phvdrainOnly phv POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phvhalfFieldless phv POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phvfixedBlackBox phv POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET plowvtnormGate plowvt POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET plowvtwaffleCap plowvt POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET plowvtdrainOnly plowvt POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET plowvthalfFieldless plowvt POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET plowvtfixedBlackBox plowvt POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phighvtnormGate PFET_01V8_HVT POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phighvtwaffleCap PFET_01V8_HVT POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phighvtdrainOnly PFET_01V8_HVT POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phighvthalfFieldless PFET_01V8_HVT POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET phighvtfixedBlackBox PFET_01V8_HVT POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET pshortnormGate pshort POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET pshortwaffleCap pshort POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET pshortdrainOnly pshort POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET pshorthalfFieldless pshort POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET pshortfixedBlackBox pshort POLY_cond PDIFF_cond MosNwell |
| /// DEV MOSFET ntvnativenormGate ntvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET ntvnativewaffleCap ntvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET ntvnativedrainOnly ntvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET ntvnativehalfFieldless ntvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET ntvnativefixedBlackBox ntvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvnativenormGate nhvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvnativewaffleCap nhvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvnativedrainOnly nhvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvnativehalfFieldless nhvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvnativefixedBlackBox nhvnative POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvnormGate nhv POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvwaffleCap nhv POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvdrainOnly nhv POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvhalfFieldless nhv POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nhvfixedBlackBox nhv POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET fnpassnormGate fnpass POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET fnpasswaffleCap fnpass POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET fnpassdrainOnly fnpass POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET fnpasshalfFieldless fnpass POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET fnpassfixedBlackBox fnpass POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET sonos_enormGate sonos_e POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET sonos_ewaffleCap sonos_e POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET sonos_edrainOnly sonos_e POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET sonos_ehalfFieldless sonos_e POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET sonos_efixedBlackBox sonos_e POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nlowvtnormGate nlowvt POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nlowvtwaffleCap nlowvt POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nlowvtdrainOnly nlowvt POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nlowvthalfFieldless nlowvt POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nlowvtfixedBlackBox nlowvt POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nshortnormGate nfet_01v8 POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nshortwaffleCap nfet_01v8 POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nshortdrainOnly nfet_01v8 POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nshorthalfFieldless nfet_01v8 POLY_cond NDIFF_cond Substrate |
| /// DEV MOSFET nshortfixedBlackBox nfet_01v8 POLY_cond NDIFF_cond Substrate |
| /// --END AGDS TABLE-- |
| |
| // ;ss these should match lvsRules |
| |
| /// --BEGIN DFII LAYER MAP TABLE-- |
| /// ind4Minus ("y0" "drawing") |
| /// ind4Bias ("y0" "drawing") |
| /// ind4Plus ("y0" "drawing") |
| /// deFETpsource ("y0" "drawing") |
| /// deFETpdrain ("y0" "drawing") |
| /// deFETnsource ("y0" "drawing") |
| /// deFETndrain ("y0" "drawing") |
| /// SubstrateIso ("y0" "drawing") |
| /// SubstrateSpecialCont ("y0" "drawing") |
| /// SubstrateSpecial ("y0" "drawing") |
| /// Substrate ("y0" "drawing") |
| /// PFOM_cond ("y0" "drawing") |
| /// NFOM_cond ("y0" "drawing") |
| /// rdlcon ("rdl" "drawing") |
| /// rdl_MET5 ("rdl" "drawing") |
| /// via4 ("via4" "drawing") |
| /// via3 ("via3" "drawing") |
| /// via2 ("via2" "drawing") |
| /// via ("via" "drawing") |
| /// mcon ("mcon" "drawing") |
| /// licon1_POLY ("licon1" "drawing") |
| /// licon1_NPNDIFF ("licon1" "drawing") |
| /// licon1_PNPDIFF ("licon1" "drawing") |
| /// licon1_PTAP_notbjt ("licon1" "drawing") |
| /// licon1_NTAP_notbjt ("licon1" "drawing") |
| /// licon1_PTAP_notDnwell ("licon1" "drawing") |
| /// licon1_PTAP_npn ("licon1" "drawing") |
| /// licon1_PTAP_pnp ("licon1" "drawing") |
| /// licon1_NTAP_npn ("licon1" "drawing") |
| /// licon1_NTAP_pnp ("licon1" "drawing") |
| /// licon1_PDIFF ("licon1" "drawing") |
| /// licon1_NDIFF ("licon1" "drawing") |
| /// DNWELL_cont ("y0" "drawing") |
| /// NTAP_notbjt_cont ("y0" "drawing") |
| /// NTAP_npn_cont ("y0" "drawing") |
| /// NTAP_pnp_cont ("y0" "drawing") |
| /// PTAP_NotDnwell_cont ("y0" "drawing") |
| /// PTAP_notbjt_cont ("y0" "drawing") |
| /// PTAP_npn_cont ("y0" "drawing") |
| /// PTAP_pnp_cont ("y0" "drawing") |
| /// CAP3_Well_contVpp ("y0" "drawing") |
| /// CAP3_NoWell_contVpp ("y0" "drawing") |
| /// CAP3_Well_contVpp ("y0" "drawing") |
| /// CAP3_NoWell_contVpp ("y0" "drawing") |
| /// CAP3_Well_contVpp ("y0" "drawing") |
| /// CAP3_NoWell_contVpp ("y0" "drawing") |
| /// CAP3_WellMos_cont ("y0" "drawing") |
| /// CAP3_NoWellMos_cont ("y0" "drawing") |
| /// CAP3_Well_cont ("y0" "drawing") |
| /// CAP3_NoWell_cont ("y0" "drawing") |
| /// GATE_shield ("y0" "drawing") |
| /// RDL_gshield_upp ("y0" "drawing") |
| /// RDL_gshield_low ("y0" "drawing") |
| /// MET5_gshield_upp ("y0" "drawing") |
| /// MET5_gshield_low ("y0" "drawing") |
| /// MET4_gshield_upp ("y0" "drawing") |
| /// MET4_gshield_low ("y0" "drawing") |
| /// MET3_gshield_upp ("y0" "drawing") |
| /// MET3_gshield_low ("y0" "drawing") |
| /// MET2_gshield_upp ("y0" "drawing") |
| /// MET2_gshield_low ("y0" "drawing") |
| /// MET1_gshield_upp ("y0" "drawing") |
| /// MET1_gshield_low ("y0" "drawing") |
| /// LI1_gshield_upp ("y0" "drawing") |
| /// LI1_gshield_low ("y0" "drawing") |
| /// POLY_gshield_upp ("y0" "drawing") |
| /// POLY_gshield_low ("y0" "drawing") |
| /// q6rdl ("y0" "drawing") |
| /// q7rdl ("y0" "drawing") |
| /// rdl_pin ("rdl" "pin") |
| /// RDL_cond_nrc ("rdl" "drawing") |
| /// RDL_cond ("rdl" "drawing") |
| /// q6pad ("y0" "drawing") |
| /// q7pad ("y0" "drawing") |
| /// pad_pin ("pad" "pin") |
| /// PAD_cond ("pad" "drawing") |
| /// q6met5 ("y0" "drawing") |
| /// q7met5 ("y0" "drawing") |
| /// met5_pin ("met5" "pin") |
| /// MET5_cond_nrc ("met5" "drawing") |
| /// MET5_cond ("met5" "drawing") |
| /// q6met4 ("y0" "drawing") |
| /// q7met4 ("y0" "drawing") |
| /// met4_pin ("met4" "pin") |
| /// MET4_cond_nrc ("met4" "drawing") |
| /// MET4_cond ("met4" "drawing") |
| /// q6met3 ("y0" "drawing") |
| /// q7met3 ("y0" "drawing") |
| /// met3_pin ("met3" "pin") |
| /// MET3_cond_nrc ("met3" "drawing") |
| /// MET3_cond ("met3" "drawing") |
| /// q6met2 ("y0" "drawing") |
| /// q7met2 ("y0" "drawing") |
| /// met2_pin ("met2" "pin") |
| /// MET2_cond_nrc ("met2" "drawing") |
| /// MET2_cond ("met2" "drawing") |
| /// q6met1 ("y0" "drawing") |
| /// q7met1 ("y0" "drawing") |
| /// met1_pin ("met1" "pin") |
| /// MET1_cond_nrc ("met1" "drawing") |
| /// MET1_cond ("met1" "drawing") |
| /// q6li1 ("y0" "drawing") |
| /// q7li1 ("y0" "drawing") |
| /// li1_pin ("li1" "pin") |
| /// LI1_cond_nrc ("li1" "drawing") |
| /// LI1_cond ("li1" "drawing") |
| /// q6poly ("y0" "drawing") |
| /// q7poly ("y0" "drawing") |
| /// poly_pin ("poly" "pin") |
| /// POLY_cond_nrc ("poly" "drawing") |
| /// POLY_cond ("poly" "drawing") |
| /// BulkTermCap_condVpp_M4 ("y0" "drawing") |
| /// BulkTermCap_condVpp_M5 ("y0" "drawing") |
| /// BulkTermCap_condVpp ("y0" "drawing") |
| /// BulkTermCapMos_cond ("y0" "drawing") |
| /// BulkTermCap_cond ("y0" "drawing") |
| /// NTAP_notbjt_cond ("tap" "drawing") |
| /// NTAP_npn_cond ("y0" "drawing") |
| /// NTAP_pnp_cond ("tap" "drawing") |
| /// PTAP_NotDnwell_cond ("y0" "drawing") |
| /// PTAP_notbjt_cond ("y0" "drawing") |
| /// PTAP_npn_cond ("tap" "drawing") |
| /// PTAP_pnp_cond ("tap" "drawing") |
| /// diff_pin ("diff" "pin") |
| /// NPNDIFF_cond ("diff" "drawing") |
| /// diff_pin ("diff" "pin") |
| /// PNPDIFF_cond ("diff" "drawing") |
| /// diff_pin ("diff" "pin") |
| /// NDIFF_cond ("diff" "drawing") |
| /// diff_pin ("diff" "pin") |
| /// PDIFF_cond ("diff" "drawing") |
| /// pwresBiasTerm_cond ("y0" "drawing") |
| /// nwell_pin ("nwell" "pin") |
| /// NpnNwell ("nwell" "drawing") |
| /// nwell_pin ("nwell" "pin") |
| /// PnpNwell ("nwell" "drawing") |
| /// nwell_pin ("nwell" "pin") |
| /// MosNwell ("nwell" "drawing") |
| /// DNWELL_cond ("y0" "drawing") |
| /// pwelliso_pin ("y0" "drawing") |
| /// SubstrateIso ("y0" "drawing") |
| /// pwell_pin ("y0" "drawing") |
| /// Substrate ("y0" "drawing") |
| /// m5probe ("y0" "drawing") |
| /// MET5_PROBE_cond ("y0" "drawing") |
| /// m4probe ("y0" "drawing") |
| /// MET4_PROBE_cond ("y0" "drawing") |
| /// m3probe ("y0" "drawing") |
| /// MET3_PROBE_cond ("y0" "drawing") |
| /// m2probe ("y0" "drawing") |
| /// MET2_PROBE_cond ("y0" "drawing") |
| /// m1probe ("y0" "drawing") |
| /// MET1_PROBE_cond ("y0" "drawing") |
| /// pyprobe ("y0" "drawing") |
| /// POLY_PROBE_cond ("y0" "drawing") |
| /// liprobe ("y0" "drawing") |
| /// LI1_PROBE_cond ("y0" "drawing") |
| /// q0metop8 ("y0" "drawing") |
| /// q0metop7 ("y0" "drawing") |
| /// q0metop6 ("y0" "drawing") |
| /// q0metop5 ("y0" "drawing") |
| /// q0metop4 ("y0" "drawing") |
| /// q0metop3 ("y0" "drawing") |
| /// q0metop2 ("y0" "drawing") |
| /// q0metop1 ("y0" "drawing") |
| /// m4fuse ("y0" "drawing") |
| /// rdshort ("y0" "drawing") |
| /// m5short ("y0" "drawing") |
| /// m4short ("y0" "drawing") |
| /// m3short ("y0" "drawing") |
| /// m2short ("y0" "drawing") |
| /// m1short ("y0" "drawing") |
| /// lishort ("y0" "drawing") |
| /// pyshort ("y0" "drawing") |
| /// mrpw ("y0" "drawing") |
| /// xhrpoly_5p73_sub ("y0" "drawing") |
| /// xhrpoly_2p85_sub ("y0" "drawing") |
| /// xhrpoly_1p41_sub ("y0" "drawing") |
| /// xhrpoly_0p69_sub ("y0" "drawing") |
| /// xhrpoly_0p35_sub ("y0" "drawing") |
| /// xhrpoly_5p73_nwell ("y0" "drawing") |
| /// xhrpoly_2p85_nwell ("y0" "drawing") |
| /// xhrpoly_1p41_nwell ("y0" "drawing") |
| /// xhrpoly_0p69_nwell ("y0" "drawing") |
| /// xhrpoly_0p35_nwell ("y0" "drawing") |
| /// mrl1 ("y0" "drawing") |
| /// mrp1 ("y0" "drawing") |
| /// mrdp_hv ("y0" "drawing") |
| /// mrdp_lv ("y0" "drawing") |
| /// mrdn_hv ("y0" "drawing") |
| /// mrdn_lv ("y0" "drawing") |
| /// xind4 ("y0" "drawing") |
| /// xind4 ("y0" "drawing") |
| /// xind4 ("y0" "drawing") |
| /// balun ("y0" "drawing") |
| /// cap35fF ("y0" "drawing") |
| /// cap10fF ("y0" "drawing") |
| /// cap5fF ("y0" "drawing") |
| /// cap12fF_noShield ("y0" "drawing") |
| /// cap100fF_m1m2 ("y0" "drawing") |
| /// cap100fF_m3m4 ("y0" "drawing") |
| /// cap100fF_mm5shield ("y0" "drawing") |
| /// cap1fF ("y0" "drawing") |
| /// cap12fF ("y0" "drawing") |
| /// cap50fF ("y0" "drawing") |
| /// cap100fF ("y0" "drawing") |
| /// cap100fF_liShield ("y0" "drawing") |
| /// cap50fF_liShield ("y0" "drawing") |
| /// cap12fF_liShield ("y0" "drawing") |
| /// cap1fF_liShield ("y0" "drawing") |
| /// vppM4shield1 ("y0" "drawing") |
| /// vppM4shield2 ("y0" "drawing") |
| /// vppM4shield3 ("y0" "drawing") |
| /// vppM4shield4 ("y0" "drawing") |
| /// cap140fF_1 ("y0" "drawing") |
| /// cap140fF_2 ("y0" "drawing") |
| /// cap140fF_3 ("y0" "drawing") |
| /// cap140fF_4 ("y0" "drawing") |
| /// cap140fF_5 ("y0" "drawing") |
| /// cap140fF_6 ("y0" "drawing") |
| /// cap140fF_7 ("y0" "drawing") |
| /// vppcapNHVnative ("y0" "drawing") |
| /// vppcap_hd5_a ("y0" "drawing") |
| /// vppcap_hd5_b ("y0" "drawing") |
| /// vppcap_hd5_c ("y0" "drawing") |
| /// vppcap_hd5_d ("y0" "drawing") |
| /// vppcap_hd5_e ("y0" "drawing") |
| /// vppcap_hd5_f ("y0" "drawing") |
| /// vppcap_hd5_g ("y0" "drawing") |
| /// vppcap_hd5_h ("y0" "drawing") |
| /// vppcap_hd5_i ("y0" "drawing") |
| /// vppcap_hd5_j ("y0" "drawing") |
| /// vppcap_hd5_k ("y0" "drawing") |
| /// vppcap_hd5_l ("y0" "drawing") |
| /// vppcap_hd5_m ("y0" "drawing") |
| /// vppcap_hd5_n ("y0" "drawing") |
| /// vppcap_hd5_o ("y0" "drawing") |
| /// vppcap_hd5_p ("y0" "drawing") |
| /// vppcap_hd5_q ("y0" "drawing") |
| /// vppcap_hd5_r ("y0" "drawing") |
| /// vppcap_hd5_s ("y0" "drawing") |
| /// xcmvpp_2phv ("y0" "drawing") |
| /// xcmvpp_2nhvnative ("y0" "drawing") |
| /// xcmvpp_2 ("y0" "drawing") |
| /// xcmvpp ("y0" "drawing") |
| /// localSub ("y0" "drawing") |
| /// pw_dnw_par ("y0" "drawing") |
| /// dnw_psub_par ("y0" "drawing") |
| /// q2nwdio_par_noDnwell ("y0" "drawing") |
| /// q1nwdio_par_noDnwell ("y0" "drawing") |
| /// q0nwdio_par_noDnwell ("y0" "drawing") |
| /// nwdio_par ("y0" "drawing") |
| /// pdiode_par_highvt ("y0" "drawing") |
| /// pdiode_par_lvtn ("y0" "drawing") |
| /// pdiode_par_hv ("y0" "drawing") |
| /// pdiode_par_lv ("y0" "drawing") |
| /// ndiode_par_hv_lvtn ("y0" "drawing") |
| /// ndiode_par_lvtn ("y0" "drawing") |
| /// ndiode_par_hv ("y0" "drawing") |
| /// ndiode_par ("y0" "drawing") |
| /// pwDioHV300 ("y0" "drawing") |
| /// pwDioHV200 ("y0" "drawing") |
| /// pwDioHV100 ("y0" "drawing") |
| /// photoDiode ("y0" "drawing") |
| /// pDioHV300 ("y0" "drawing") |
| /// pDioHV200 ("y0" "drawing") |
| /// pDioHV100 ("y0" "drawing") |
| /// pDiodeHV ("y0" "drawing") |
| /// pDiode ("y0" "drawing") |
| /// nDioHV300 ("y0" "drawing") |
| /// nDioHV200 ("y0" "drawing") |
| /// nDioHV100 ("y0" "drawing") |
| /// nDiodeHV ("y0" "drawing") |
| /// diode_pw2nd_05v5 ("y0" "drawing") |
| /// pnppar5x ("y0" "drawing") |
| /// pnppar1x ("y0" "drawing") |
| /// npn_1x1_2p0_HV ("y0" "drawing") |
| /// npnpar1x2 ("y0" "drawing") |
| /// npnpar1x1 ("y0" "drawing") |
| /// xchvnwc ("y0" "drawing") |
| /// xcnwvc2 ("y0" "drawing") |
| /// xcnwvc ("y0" "drawing") |
| /// pfetExtDr ("y0" "drawing") |
| /// nfetExtDr ("y0" "drawing") |
| /// condiode ("y0" "drawing") |
| /// phvesdnormGate ("y0" "drawing") |
| /// phvesdnormGate ("y0" "drawing") |
| /// phvesdwaffleCap ("y0" "drawing") |
| /// phvesdwaffleCap ("y0" "drawing") |
| /// phvesddrainOnly ("y0" "drawing") |
| /// phvesddrainOnly ("y0" "drawing") |
| /// phvesdhalfFieldless ("y0" "drawing") |
| /// phvesdhalfFieldless ("y0" "drawing") |
| /// phvesdfixedBlackBox ("y0" "drawing") |
| /// phvesdfixedBlackBox ("y0" "drawing") |
| /// nhvnativeesdnormGate ("y0" "drawing") |
| /// nhvnativeesdnormGate ("y0" "drawing") |
| /// nhvnativeesdwaffleCap ("y0" "drawing") |
| /// nhvnativeesdwaffleCap ("y0" "drawing") |
| /// nhvnativeesddrainOnly ("y0" "drawing") |
| /// nhvnativeesddrainOnly ("y0" "drawing") |
| /// nhvnativeesdhalfFieldless ("y0" "drawing") |
| /// nhvnativeesdhalfFieldless ("y0" "drawing") |
| /// nhvnativeesdfixedBlackBox ("y0" "drawing") |
| /// nhvnativeesdfixedBlackBox ("y0" "drawing") |
| /// nhvesdnormGate ("y0" "drawing") |
| /// nhvesdnormGate ("y0" "drawing") |
| /// nhvesdwaffleCap ("y0" "drawing") |
| /// nhvesdwaffleCap ("y0" "drawing") |
| /// nhvesddrainOnly ("y0" "drawing") |
| /// nhvesddrainOnly ("y0" "drawing") |
| /// nhvesdhalfFieldless ("y0" "drawing") |
| /// nhvesdhalfFieldless ("y0" "drawing") |
| /// nhvesdfixedBlackBox ("y0" "drawing") |
| /// nhvesdfixedBlackBox ("y0" "drawing") |
| /// nshortesdnormGate ("y0" "drawing") |
| /// nshortesdnormGate ("y0" "drawing") |
| /// nshortesdwaffleCap ("y0" "drawing") |
| /// nshortesdwaffleCap ("y0" "drawing") |
| /// nshortesddrainOnly ("y0" "drawing") |
| /// nshortesddrainOnly ("y0" "drawing") |
| /// nshortesdhalfFieldless ("y0" "drawing") |
| /// nshortesdhalfFieldless ("y0" "drawing") |
| /// nshortesdfixedBlackBox ("y0" "drawing") |
| /// nshortesdfixedBlackBox ("y0" "drawing") |
| /// phvnormGate ("y0" "drawing") |
| /// phvnormGate ("y0" "drawing") |
| /// phvwaffleCap ("y0" "drawing") |
| /// phvwaffleCap ("y0" "drawing") |
| /// phvdrainOnly ("y0" "drawing") |
| /// phvdrainOnly ("y0" "drawing") |
| /// phvhalfFieldless ("y0" "drawing") |
| /// phvhalfFieldless ("y0" "drawing") |
| /// phvfixedBlackBox ("y0" "drawing") |
| /// phvfixedBlackBox ("y0" "drawing") |
| /// plowvtnormGate ("y0" "drawing") |
| /// plowvtnormGate ("y0" "drawing") |
| /// plowvtwaffleCap ("y0" "drawing") |
| /// plowvtwaffleCap ("y0" "drawing") |
| /// plowvtdrainOnly ("y0" "drawing") |
| /// plowvtdrainOnly ("y0" "drawing") |
| /// plowvthalfFieldless ("y0" "drawing") |
| /// plowvthalfFieldless ("y0" "drawing") |
| /// plowvtfixedBlackBox ("y0" "drawing") |
| /// plowvtfixedBlackBox ("y0" "drawing") |
| /// phighvtnormGate ("y0" "drawing") |
| /// phighvtnormGate ("y0" "drawing") |
| /// phighvtwaffleCap ("y0" "drawing") |
| /// phighvtwaffleCap ("y0" "drawing") |
| /// phighvtdrainOnly ("y0" "drawing") |
| /// phighvtdrainOnly ("y0" "drawing") |
| /// phighvthalfFieldless ("y0" "drawing") |
| /// phighvthalfFieldless ("y0" "drawing") |
| /// phighvtfixedBlackBox ("y0" "drawing") |
| /// phighvtfixedBlackBox ("y0" "drawing") |
| /// pshortnormGate ("y0" "drawing") |
| /// pshortnormGate ("y0" "drawing") |
| /// pshortwaffleCap ("y0" "drawing") |
| /// pshortwaffleCap ("y0" "drawing") |
| /// pshortdrainOnly ("y0" "drawing") |
| /// pshortdrainOnly ("y0" "drawing") |
| /// pshorthalfFieldless ("y0" "drawing") |
| /// pshorthalfFieldless ("y0" "drawing") |
| /// pshortfixedBlackBox ("y0" "drawing") |
| /// pshortfixedBlackBox ("y0" "drawing") |
| /// ntvnativenormGate ("y0" "drawing") |
| /// ntvnativenormGate ("y0" "drawing") |
| /// ntvnativewaffleCap ("y0" "drawing") |
| /// ntvnativewaffleCap ("y0" "drawing") |
| /// ntvnativedrainOnly ("y0" "drawing") |
| /// ntvnativedrainOnly ("y0" "drawing") |
| /// ntvnativehalfFieldless ("y0" "drawing") |
| /// ntvnativehalfFieldless ("y0" "drawing") |
| /// ntvnativefixedBlackBox ("y0" "drawing") |
| /// ntvnativefixedBlackBox ("y0" "drawing") |
| /// nhvnativenormGate ("y0" "drawing") |
| /// nhvnativenormGate ("y0" "drawing") |
| /// nhvnativewaffleCap ("y0" "drawing") |
| /// nhvnativewaffleCap ("y0" "drawing") |
| /// nhvnativedrainOnly ("y0" "drawing") |
| /// nhvnativedrainOnly ("y0" "drawing") |
| /// nhvnativehalfFieldless ("y0" "drawing") |
| /// nhvnativehalfFieldless ("y0" "drawing") |
| /// nhvnativefixedBlackBox ("y0" "drawing") |
| /// nhvnativefixedBlackBox ("y0" "drawing") |
| /// nhvnormGate ("y0" "drawing") |
| /// nhvnormGate ("y0" "drawing") |
| /// nhvwaffleCap ("y0" "drawing") |
| /// nhvwaffleCap ("y0" "drawing") |
| /// nhvdrainOnly ("y0" "drawing") |
| /// nhvdrainOnly ("y0" "drawing") |
| /// nhvhalfFieldless ("y0" "drawing") |
| /// nhvhalfFieldless ("y0" "drawing") |
| /// nhvfixedBlackBox ("y0" "drawing") |
| /// nhvfixedBlackBox ("y0" "drawing") |
| /// fnpassnormGate ("y0" "drawing") |
| /// fnpassnormGate ("y0" "drawing") |
| /// fnpasswaffleCap ("y0" "drawing") |
| /// fnpasswaffleCap ("y0" "drawing") |
| /// fnpassdrainOnly ("y0" "drawing") |
| /// fnpassdrainOnly ("y0" "drawing") |
| /// fnpasshalfFieldless ("y0" "drawing") |
| /// fnpasshalfFieldless ("y0" "drawing") |
| /// fnpassfixedBlackBox ("y0" "drawing") |
| /// fnpassfixedBlackBox ("y0" "drawing") |
| /// sonos_enormGate ("y0" "drawing") |
| /// sonos_enormGate ("y0" "drawing") |
| /// sonos_ewaffleCap ("y0" "drawing") |
| /// sonos_ewaffleCap ("y0" "drawing") |
| /// sonos_edrainOnly ("y0" "drawing") |
| /// sonos_edrainOnly ("y0" "drawing") |
| /// sonos_ehalfFieldless ("y0" "drawing") |
| /// sonos_ehalfFieldless ("y0" "drawing") |
| /// sonos_efixedBlackBox ("y0" "drawing") |
| /// sonos_efixedBlackBox ("y0" "drawing") |
| /// nlowvtnormGate ("y0" "drawing") |
| /// nlowvtnormGate ("y0" "drawing") |
| /// nlowvtwaffleCap ("y0" "drawing") |
| /// nlowvtwaffleCap ("y0" "drawing") |
| /// nlowvtdrainOnly ("y0" "drawing") |
| /// nlowvtdrainOnly ("y0" "drawing") |
| /// nlowvthalfFieldless ("y0" "drawing") |
| /// nlowvthalfFieldless ("y0" "drawing") |
| /// nlowvtfixedBlackBox ("y0" "drawing") |
| /// nlowvtfixedBlackBox ("y0" "drawing") |
| /// nshortnormGate ("y0" "drawing") |
| /// nshortnormGate ("y0" "drawing") |
| /// nshortwaffleCap ("y0" "drawing") |
| /// nshortwaffleCap ("y0" "drawing") |
| /// nshortdrainOnly ("y0" "drawing") |
| /// nshortdrainOnly ("y0" "drawing") |
| /// nshorthalfFieldless ("y0" "drawing") |
| /// nshorthalfFieldless ("y0" "drawing") |
| /// nshortfixedBlackBox ("y0" "drawing") |
| /// nshortfixedBlackBox ("y0" "drawing") |
| /// --END DFII LAYER MAP TABLE-- |
| /// --BEGIN SCHEMATIC DEVICE MAP TABLE-- |
| /// probe_rdltt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_padtt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met5tt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met4tt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met3tt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met2tt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met1tt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_li1tt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_polytt tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met5probe tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met4probe tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met3probe tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met2probe tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_met1probe tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_polyprobe tech res symbol probe r0 conductor r1 probetype=probeType |
| /// probe_li1probe tech res symbol probe r0 conductor r1 probetype=probeType |
| /// metop tech metop symbol neg m1 pos m0 w=w l=l metopnumber=metopNumber |
| /// fuse tech fuse symbol neg f1 pos f0 w=rw l=rl |
| /// short tech short symbol neg m1 pos m0 w=rw l=rl |
| /// xpwres tech respw symbol neg r1 pos r0 sub b w=rw l=rl |
| /// xhrpoly_5p73 tech res3 symbol neg r1 pos r0 sub b w=rw l=rl |
| /// xhrpoly_2p85 tech res3 symbol neg r1 pos r0 sub b w=rw l=rl |
| /// xhrpoly_1p41 tech res3 symbol neg r1 pos r0 sub b w=rw l=rl |
| /// xhrpoly_0p69 tech res3 symbol neg r1 pos r0 sub b w=rw l=rl |
| /// xhrpoly_0p35 tech res3 symbol neg r1 pos r0 sub b w=rw l=rl |
| /// mrl1 tech res symbol neg r1 pos r0 w=rw l=rl |
| /// mrp1 tech res symbol neg r1 pos r0 w=rw l=rl |
| /// mrdp_hv tech res symbol neg r1 pos r0 w=rw l=rl |
| /// mrdp tech res symbol neg r1 pos r0 w=rw l=rl |
| /// mrdn_hv tech res symbol neg r1 pos r0 w=rw l=rl |
| /// mrdn tech res symbol neg r1 pos r0 w=rw l=rl |
| /// xind4 tech ind4 symbol pin0 t1 pin1 t2 pin2 t3 pin3 body |
| /// xcmvpp3 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp4 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp5 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp4p4x4p6_m1m2 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp11p5x11p7_m1m2 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp11p5x11p7_m1m4 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp11p5x11p7_m1m4m5shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp1p8x1p8_m3shield tech vppcap symbol c0 c0 c1 c1 b b term4 term4 |
| /// xcmvpp4p4x4p6_m3shield tech vppcap symbol c0 c0 c1 c1 b b term4 term4 |
| /// xcmvpp8p6x7p9_m3shield tech vppcap symbol c0 c0 c1 c1 b b term4 term4 |
| /// xcmvpp11p5x11p7_m3shield tech vppcap symbol c0 c0 c1 c1 b b term4 term4 |
| /// xcmvpp11p5x11p7_m3_lishield tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp8p6x7p9_m3_lishield tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp4p4x4p6_m3_lishield tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp1p8x1p8 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp11p5x11p7_m4shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp11p5x11p7_polym4shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp6p8x6p1_polym4shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp6p8x6p1_lim4shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp11p5x11p7_m5shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp11p5x11p7_polym5shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp11p5x11p7_lim5shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp8p6x7p9_m3_lim5shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp11p5x11p7_m3_lim5shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp4p4x4p6_m3_lim5shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp11p5x11p7_polym50p4shield tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvppx4_2xnhvnative10x4 tech vppcap symbol pin0 c0 pin1 c1 pin2 b pin3 term4 |
| /// xcmvpp_hd5_1x1 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_1x2 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_2x1 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_2x2 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_3x1 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_3x2 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_4x1 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_4x2 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_5x1 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_5x1_met5pullin tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_5x2 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_5x2_met5pullin tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_atlas_fingercap_l5 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_atlas_fingercap_l10 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_atlas_fingercap_l20 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_atlas_fingercap_l40 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_atlas_wafflecap1 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_atlas_wafflecap2 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp_hd5_atlas_fingercap2_l5 tech cap_int3 symbol pin0 c0 pin1 c1 pin2 b m=cm |
| /// xcmvpp2_phv5x4 tech capbn_b symbol pin0 c0 pin1 c1 pin2 b |
| /// xcmvpp2_nhvnative10x4 tech capbn_b symbol pin0 c0 pin1 c1 pin2 b |
| /// reslocsub tech reslocsub symbol neg r0 pos r1 a=w p=l |
| /// dnwdiode_pw tech diode symbol pos d0 neg d1 a=area p=perim |
| /// nwdiode tech diode symbol pos d0 neg d1 a=area p=perim |
| /// pdiode_hvt tech diode symbol pos d0 neg d1 a=area p=perim |
| /// pdiode_lvt tech diode symbol pos d0 neg d1 a=area p=perim |
| /// ndiode_native tech diode symbol pos d0 neg d1 a=area p=perim |
| /// ndiode_lvt tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_ndiode_h_dnwl_300 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_ndiode_h_dnwl_200 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_ndiode_h_dnwl_100 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// dnwdiode_psub tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_pdiode_h_300 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_pdiode_h_200 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_pdiode_h_100 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// pdiode_h tech diode symbol pos d0 neg d1 a=area p=perim |
| /// pdiode tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_ndiode_h_300 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_ndiode_h_200 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// xesd_ndiode_h_100 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// ndiode_h tech diode symbol pos d0 neg d1 a=area p=perim |
| /// diode_pw2nd_05v5 tech diode symbol pos d0 neg d1 a=area p=perim |
| /// pnppar5x tech pnp4 symbol c c b b e e s body barea=bArea bperi=bPeri earea=eArea eperi=ePeri |
| /// pnppar tech pnp4 symbol c c b b e e s body barea=bArea bperi=bPeri earea=eArea eperi=ePeri |
| /// npn_1x1_2p0_hv tech npn4 symbol c c b b e e s body gext_dummy=gext_dummy |
| /// npnpar1x2 tech npn4 symbol c c b b e e s body gext_dummy=gext_dummy |
| /// npnpar1x1 tech npn4 symbol c c b b e e s body gext_dummy=gext_dummy |
| /// xcnwvc2 tech capbn_b symbol pin0 c0 pin1 c1 pin2 b w=cw l=cl m=cm |
| /// xcnwvc tech capbn_b symbol pin0 c0 pin1 c1 pin2 b w=cw l=cl m=cm |
| /// pvhv tech pfetextd symbol pin0 d pin1 g pin2 s pin3 b w=w l=l |
| /// nvhv tech nfetextd symbol pin0 d pin1 g pin2 s pin3 b w=w l=l |
| /// condiode tech condiode symbol pin0 d0 pin1 d |
| /// phvesd tech pfet symbol d d g g s s b b w=w l=l |
| /// nhvnativeesd tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvesd tech nfet symbol d d g g s s b b w=w l=l |
| /// nshortesd tech nfet symbol d d g g s s b b w=w l=l |
| /// phv tech pfet symbol d d g g s s b b w=w l=l |
| /// plowvt tech pfet symbol d d g g s s b b w=w l=l |
| /// PFET_01V8_HVT tech pfet symbol d d g g s s b b w=w l=l |
| /// pshort tech pfet symbol d d g g s s b b w=w l=l |
| /// ntvnative tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvnative tech nfet symbol d d g g s s b b w=w l=l |
| /// nhv tech nfet symbol d d g g s s b b w=w l=l |
| /// fnpass tech nfet symbol d d g g s s b b w=w l=l |
| /// sonos_e tech nfet symbol d d g g s s b b w=w l=l |
| /// nlowvt tech nfet symbol d d g g s s b b w=w l=l |
| /// nfet_01v8 tech nfet symbol d d g g s s b b w=w l=l |
| /// pmedlvtrf_1p68p15nf4 tech pfet symbol d d g g s s b b w=w l=l |
| /// pmedlvtrf_1p68p15nf2 tech pfet symbol d d g g s s b b w=w l=l |
| /// pmedlvtrf_p84p15nf2 tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_5p15nf2 tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_3p15nf2 tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_1p68p15nf4 tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_1p68p15nf2 tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_p84p15nf2 tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_5p25m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_5p25m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_5p18m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_5p18m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_5p15m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_5p15m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_3p25m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_3p25m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_3p18m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_3p18m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_3p15m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_3p15m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_1p65p25m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_1p65p25m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_1p65p18m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_1p65p18m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_1p65p15m4_b tech pfet symbol d d g g s s b b w=w l=l |
| /// psrf_1p65p15m2_b tech pfet symbol d d g g s s b b w=w l=l |
| /// nsrf_5p25m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_5p25m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_5p18m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_5p18m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_5p15m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_5p15m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_3p25m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_3p25m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_3p18m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_3p18m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_3p15m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_3p15m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_1p65p25m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_1p65p25m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_1p65p18m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_1p65p18m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_1p65p15m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nsrf_1p65p15m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p15nf8 tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p15nf4 tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p15nf2 tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_p84p15nf8 tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_p84p15nf4 tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_p84p15nf2 tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_p42p15nf2 tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_5p25m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_5p25m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_5p18m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_5p18m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_5p15m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_5p15m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p25m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p25m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p18m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p18m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p15m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_3p15m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_1p65p25m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_1p65p25m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_1p65p18m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_1p65p18m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_1p65p15m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nlrf_1p65p15m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvrf_7p50m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvrf_7p50m10_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvrf_5p50m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvrf_5p50m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvrf_5p50m10_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvrf_3p50m4_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvrf_3p50m10_b tech nfet symbol d d g g s s b b w=w l=l |
| /// nhvrf_3p50m2_b tech nfet symbol d d g g s s b b w=w l=l |
| /// --END SCHEMATIC DEVICE MAP TABLE-- |
| |
| // ;ss Values should be checked |
| |
| /// --BEGIN FET DIFF SHEET TABLE-- |
| /// phvesd 191.0 phvesd |
| /// nhvnativeesd 114.0 nhvnativeesd |
| /// nhvesd 114.0 nhvesd |
| /// nshortesd 120.0 nshortesd |
| /// phv 191.0 phv |
| /// plowvt 197.0 plowvt |
| /// PFET_01V8_HVT 197.0 PFET_01V8_HVT |
| /// pshort 197.0 pshort |
| /// ntvnative 114.0 ntvnative |
| /// nhvnative 114.0 nhvnative |
| /// nhv 114.0 nhv |
| /// fnpass 120.0 fnpass |
| /// sonos_e 120.0 sonos_e |
| /// nlowvt 120.0 nlowvt |
| /// nfet_01v8 120.0 nfet_01v8 |
| /// --END FET DIFF SHEET TABLE-- |
| /// --BEGIN SHEET RESISTANCE TABLE-- |
| /// RDL_cond 0.005 0.0 |
| /// PAD_cond 0.0 nil |
| /// MET5_cond 0.0285 0.09 |
| /// MET4_cond 0.047 0.025 |
| /// MET3_cond 0.047 0.025 |
| /// MET2_cond 0.125 0.039 |
| /// MET1_cond 0.125 0.039 |
| /// LI1_cond 12.2 -0.017 |
| /// POLY_cond 48.2 0.056 |
| /// --END SHEET RESISTANCE TABLE-- |
| /// --BEGIN CONTACT RESISTANCE TABLE-- |
| /// rdlcon 0.0058 20 |
| /// rdl_MET5 0.0058 20 |
| /// via4 0.38 0.64 |
| /// via3 3.41 0.04 |
| /// via2 3.41 0.04 |
| /// via 4.5 0.0225 |
| /// mcon 9.3 0.0289 |
| /// licon1_POLY 145.28 0.0289 |
| /// licon1_PTAP_notbjt 600.0 0.0289 |
| /// licon1_NTAP_notbjt 182.0 0.0289 |
| /// licon1_PDIFF 600.0 0.0289 |
| /// licon1_NDIFF 182.0 0.0289 |
| /// --END CONTACT RESISTANCE TABLE-- |
