| ; |
| ; S8 5LM Calibre xRC cell map file |
| ; 12/14/2018 - Steven Soares |
| ; 03/24/2020 - Robert Yurman |
| ; |
| |
| ; Format for devices: |
| ; |
| ; ( LVS_name |
| ; ( library cell view ) |
| ; ( |
| ; ( LVS_terminal1 cellview_terminal1 ) ; also can use nil |
| ; ( LVS_terminal2 cellview_terminal2 ) |
| ; ( ... ) |
| ; ) ;end terminals |
| ; ( |
| ; ( LVS_param1 cellview_param1 ) |
| ; ( LVS_param1 cellview_param1 ) |
| ; ( ... ) |
| ; ) ;end paramters |
| ; ) ;end device |
| ; |
| ; NOTES |
| ; terminals and paramters don't need to be mapped if the names are the same |
| |
| ( nshort (s8phirs_10r nfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); nshort |
| |
| ( nlowvt (s8phirs_10r nfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); nlowvt |
| |
| ( sonos_e (s8phirs_10r nfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); sonos_e |
| |
| ;( fnpass (s8phirs_10r fnpass symbol) |
| ; ( (d d) (g g) (s s) (b b) ) |
| ;); fnpass |
| |
| ( nhv (s8phirs_10r nfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); nhv |
| |
| ( nhvnative (s8phirs_10r nfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); nhvnative |
| |
| ( ntvnative (s8phirs_10r nfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); ntvnative |
| |
| ( pshort (s8phirs_10r pfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); pshort |
| |
| ( phighvt (s8phirs_10r phighvt symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); phighvt |
| |
| ( plowvt (s8phirs_10r plowvt symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); plowvt |
| |
| ( phv (s8phirs_10r phv symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); phv |
| |
| ;( nshortesd (s8phirs_10r nshortesd symbol) |
| ; ( (d d) (g g) (s s) (b b) ) |
| ;); nshortesd |
| |
| ( nhvesd (s8phirs_10r nfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); nhvesd |
| |
| ( nhvnativeesd (s8phirs_10r nfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); nhvnativeesd |
| |
| ( phvesd (s8phirs_10r pfet symbol) |
| ( (d d) (g g) (s s) (b b) ) |
| ); phvesd |
| |
| ( condiode (s8phirs_10r condiode symbol) |
| ( (pin0 d0) (pin1 d1) ) |
| ); condiode |
| |
| ( condiodeHvPsub (s8phirs_10r condiodeHvPsub symbol) |
| ( (pin0 d0) (pin1 d1) ) |
| ); condiodeHvPsub |
| |
| ( nvhv (s8phirs_10r nfetextd symbol) |
| ( (pin0 d) (pin1 s) (pin2 g) (pin3 b) ) |
| ); nvhv |
| |
| ;( n20vhv1 (s8phirs_10r n20vhv1 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) (pin3 pin3) ) |
| ;); n20vhv1 |
| |
| ;( n20nativevhv1 (s8phirs_10r n20nativevhv1 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) (pin3 pin3) ) |
| ;); n20nativevhv1 |
| |
| ( n20vhviso1 (s8phirs_10r n20vhviso1 symbol) |
| ( (pin0 d) (pin1 g) (pin2 s) (pin3 b) (pin4 sub) ) |
| ); n20vhviso1 |
| |
| ( n20nativevhviso1 (s8phirs_10r n20nativevhviso1 symbol) |
| ( (pin0 d) (pin1 g) (pin2 s) (pin3 b) (pin4 sub) ) |
| ); n20nativevhviso1 |
| |
| ( pvhv (s8phirs_10r pfet symbol) |
| ( (pin0 d) (pin1 g) (pin2 s) (pin3 b) ) |
| ); pvhv |
| |
| ( p20vhv1 (s8phirs_10r p20vhv1 symbol) |
| ( (pin0 d) (pin1 g) (pin2 s) (pin3 b) ) |
| ); p20vhv1 |
| |
| ;( xcnwvc (s8phirs_10r xcnwvc symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcnwvc |
| |
| ;( xcnwvc2 (s8phirs_10r xcnwvc2 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcnwvc2 |
| |
| ;( xchvnwc (s8phirs_10r xchvnwc symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xchvnwc |
| |
| ( npnpar1x1 (s8phirs_10r npn4 symbol) |
| ( (C c) (B b) (E e) (S body) ) |
| ); npnpar1x1 |
| |
| ( npnpar1x2 (s8phirs_10r npn4 symbol) |
| ( (C c) (B b) (E e) (S body) ) |
| ); npnpar1x2 |
| |
| ;( npn_1x1_2p0_hv (s8phirs_10r npn_1x1_2p0_hv symbol) |
| ; ( (C C) (B B) (E E) (S S) ) |
| ;); npn_1x1_2p0_hv |
| |
| ( pnppar (s8phirs_10r pnp4 symbol) |
| ( (C c) (B b) (E e) (S body) ) |
| ); pnppar |
| |
| ( pnppar5x (s8phirs_10r pnp4 symbol) |
| ( (C c) (B b) (E e) (S body) ) |
| ); pnppar5x |
| |
| ( ndiode (s8phirs_10r ndiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); ndiode |
| |
| ( ndiode_h (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); ndiode_h |
| |
| ( xesd_ndiode_h_100 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_ndiode_h_100 |
| |
| ( xesd_ndiode_h_200 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_ndiode_h_200 |
| |
| ( xesd_ndiode_h_300 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_ndiode_h_300 |
| |
| ( pdiode (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); pdiode |
| |
| ( pdiode_h (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); pdiode_h |
| |
| ( xesd_pdiode_h_100 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_pdiode_h_100 |
| |
| ( xesd_pdiode_h_200 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_pdiode_h_200 |
| |
| ( xesd_pdiode_h_300 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_pdiode_h_300 |
| |
| ( dnwdiode_psub (s8phirs_10r lvdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); dnwdiode_psub |
| |
| ( xesd_ndiode_h_dnwl_100 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_ndiode_h_dnwl_100 |
| |
| ( xesd_ndiode_h_dnwl_200 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_ndiode_h_dnwl_200 |
| |
| ( xesd_ndiode_h_dnwl_300 (s8phirs_10r lvsdiode symbol) |
| ( (POS d0) (NEG d1) ) |
| ); xesd_ndiode_h_dnwl_300 |
| |
| ( ndiode_lvt (s8phirs_10r diode symbol) |
| ( (d0 d0) (d1 d1) ) |
| ); ndiode_lvt |
| |
| ( ndiode_native (s8phirs_10r diode symbol) |
| ( (d0 d0) (d1 d1) ) |
| ); ndiode_native |
| |
| ( pdiode_lvt (s8phirs_10r diode symbol) |
| ( (d0 d0) (d1 d1) ) |
| ); pdiode_lvt |
| |
| ( pdiode_hvt (s8phirs_10r diode symbol) |
| ( (d0 d0) (d1 d1) ) |
| ); pdiode_hvt |
| |
| ( nwdiode (s8phirs_10r diode symbol) |
| ( (d0 d0) (d1 d1) ) |
| ); nwdiode |
| |
| ( dnwdiode_pw (s8phirs_10r condiode symbol) |
| ( (d0 d0) (d1 d1) ) |
| ); dnwdiode_pw |
| |
| ( dnwhvdiode_psub (s8phirs_10r condiodeHvPsub symbol) |
| ( (d0 d0) (d1 d1) ) |
| ); dnwhvdiode_psub |
| |
| ;( reslocsub (s8phirs_10r reslocsub symbol) |
| ; ( (d0 d0) (d1 d1) ) |
| ;); reslocsub |
| |
| ;( xcmvpp (s8phirs_10r xcmvpp symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp |
| |
| ;( xcmvpp_2 (s8phirs_10r xcmvpp_2 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_2 |
| |
| ;( xcmvpp2_nhvnative10x4 (s8phirs_10r xcmvpp2_nhvnative10x4 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp2_nhvnative10x4 |
| |
| ;( xcmvpp2_phv5x4 (s8phirs_10r xcmvpp2_phv5x4 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp2_phv5x4 |
| |
| ( xcmvpp_hd5_atlas_fingercap2_l5 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp_hd5_atlas_fingercap2_l5 |
| |
| ( xcmvpp_hd5_atlas_wafflecap2 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp_hd5_atlas_wafflecap2 |
| |
| ( xcmvpp_hd5_atlas_wafflecap1 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp_hd5_atlas_wafflecap1 |
| |
| ( xcmvpp_hd5_atlas_fingercap_l40 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp_hd5_atlas_fingercap_l40 |
| |
| ( xcmvpp_hd5_atlas_fingercap_l20 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp_hd5_atlas_fingercap_l20 |
| |
| ( xcmvpp_hd5_atlas_fingercap_l10 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp_hd5_atlas_fingercap_l10 |
| |
| ( xcmvpp_hd5_atlas_fingercap_l5 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp_hd5_atlas_fingercap_l5 |
| |
| ;( xcmvpp_hd5_5x2_met5pullin (s8phirs_10r xcmvpp_hd5_5x2_met5pullin symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_5x2_met5pullin |
| |
| ;( xcmvpp_hd5_5x2 (s8phirs_10r xcmvpp_hd5_5x2 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_5x2 |
| |
| ;( xcmvpp_hd5_5x1_met5pullin (s8phirs_10r xcmvpp_hd5_5x1_met5pullin symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_5x1_met5pullin |
| |
| ;( xcmvpp_hd5_5x1 (s8phirs_10r xcmvpp_hd5_5x1 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_5x1 |
| |
| ( xcmvpp_hd5_4x2 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp_hd5_4x2 |
| |
| ;( xcmvpp_hd5_4x1 (s8phirs_10r xcmvpp_hd5_4x1 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_4x1 |
| |
| ;( xcmvpp_hd5_3x2 (s8phirs_10r xcmvpp_hd5_3x2 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_3x2 |
| |
| ;( xcmvpp_hd5_3x1 (s8phirs_10r xcmvpp_hd5_3x1 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_3x1 |
| |
| ;( xcmvpp_hd5_2x2 (s8phirs_10r xcmvpp_hd5_2x2 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_2x2 |
| |
| ( xcmvpp_hd5_2x1 (s8phirs_10r xcmvpp_hd5_2x1 symbol) |
| ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ); xcmvpp_hd5_2x1 |
| |
| ;( xcmvpp_hd5_1x2 (s8phirs_10r xcmvpp_hd5_1x2 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_1x2 |
| |
| ;( xcmvpp_hd5_1x1 (s8phirs_10r xcmvpp_hd5_1x1 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp_hd5_1x1 |
| |
| ( xcmvppx4_2xnhvnative10x4 (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvppx4_2xnhvnative10x4 |
| |
| ( xcmvpp11p5x11p7_polym50p4shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp11p5x11p7_polym50p4shield |
| |
| ( xcmvpp4p4x4p6_m3_lim5shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp4p4x4p6_m3_lim5shield |
| |
| ( xcmvpp11p5x11p7_m3_lim5shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp11p5x11p7_m3_lim5shield |
| |
| ( xcmvpp8p6x7p9_m3_lim5shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp8p6x7p9_m3_lim5shield |
| |
| ( xcmvpp11p5x11p7_lim5shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp11p5x11p7_lim5shield |
| |
| ( xcmvpp11p5x11p7_polym5shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp11p5x11p7_polym5shield |
| |
| ( xcmvpp11p5x11p7_m5shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp11p5x11p7_m5shield |
| |
| ( xcmvpp6p8x6p1_lim4shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp6p8x6p1_lim4shield |
| |
| ( xcmvpp6p8x6p1_polym4shield (s8phirs_10r vppcapp symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp6p8x6p1_polym4shield |
| |
| ( xcmvpp11p5x11p7_polym4shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp11p5x11p7_polym4shield |
| |
| ( xcmvpp11p5x11p7_m4shield (s8phirs_10r vppcap symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) (pin3 term4) ) |
| ); xcmvpp11p5x11p7_m4shield |
| |
| ;( xcmvpp1p8x1p8 (s8phirs_10r xcmvpp1p8x1p8 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) ) |
| ;); xcmvpp1p8x1p8 |
| |
| ( xcmvpp4p4x4p6_m3_lishield (s8rf xcmvpp4p4x4p6_m3_lishield cdlSchematic) |
| ( (pin0 c0) (pin1 c1) (pin2 sub) ) |
| ); xcmvpp4p4x4p6_m3_lishield |
| |
| ( xcmvpp8p6x7p9_m3_lishield (s8rf xcmvpp8p6x7p9_m3_lishield cdlSchematic) |
| ( (pin0 c0) (pin1 c1) (pin2 sub) ) |
| ); xcmvpp8p6x7p9_m3_lishield |
| |
| ( xcmvpp11p5x11p7_m3_lishield (s8rf xcmvpp11p5x11p7_m3_lishield cdlSchematic) |
| ( (pin0 c0) (pin1 c1) (pin2 sub) ) |
| ); xcmvpp11p5x11p7_m3_lishield |
| |
| ( xcmvpp11p5x11p7_m3shield (s8rf xcmvpp11p5x11p7_m3shield cdlSchematic) |
| ( (pin0 c0) (pin1 c1) (pin2 sub) ) |
| ); xcmvpp11p5x11p7_m3shield |
| |
| ( xcmvpp8p6x7p9_m3shield (s8rf xcmvpp8p6x7p9_m3shield cdlSchematic) |
| ( (pin0 c0) (pin1 c1) (pin2 sub) ) |
| ); xcmvpp8p6x7p9_m3shield |
| |
| ( xcmvpp4p4x4p6_m3shield (s8rf xcmvpp4p4x4p6_m3shield cdlSchematic) |
| ( (pin0 c0) (pin1 c1) (pin2 sub) ) |
| ); xcmvpp4p4x4p6_m3shield |
| |
| ( xcmvpp1p8x1p8_m3shield (s8rf xcmvpp1p8x1p8_m3shield cdlSchematic) |
| ( (pin0 c0) (pin1 c1) (pin2 sub) ) |
| ); xcmvpp1p8x1p8_m3shield |
| |
| ( xcmvpp11p5x11p7_m1m4m5shield (s8rf2 xcmvpp11p5x11p7_m1m4m5shield cfdlSchematic) |
| ( (pin0 c0) (pin1 c1) (pin2 met5) (pin3 sub) ) |
| ); xcmvpp11p5x11p7_m1m4m5shield |
| |
| ( xcmvpp11p5x11p7_m1m4 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp11p5x11p7_m1m4 |
| |
| ( xcmvpp11p5x11p7_m1m2 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp11p5x11p7_m1m2 |
| |
| ( xcmvpp4p4x4p6_m1m2 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp4p4x4p6_m1m2 |
| |
| ( xcmvpp5 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp5 |
| |
| ( xcmvpp4 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp4 |
| |
| ( xcmvpp3 (s8phirs_10r cap_int3 symbol) |
| ( (pin0 c0) (pin1 c1) (pin2 b) ) |
| ); xcmvpp3 |
| |
| ;( balun (s8phirs_10r balun symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) (pin3 pin3) (pin4 pin4) (pin5 pin5) ) |
| ;); balun |
| |
| ;( xind4 (s8phirs_10r xind4 symbol) |
| ; ( (pin0 pin0) (pin1 pin1) (pin2 pin2) (pin3 pin3) ) |
| ;); xind4 |
| |
| ( xcmimc1 (s8phirs_10r xcmimc symbol) |
| ( (POS c0) (NEG c1) ) |
| ); xcmimc1 |
| |
| ( xcmimc2 (s8phirs_10r xcmimc symbol) |
| ( (POS c0) (NEG c1) ) |
| ); xcmimc2 |
| |
| ( mrdn (s8phirs_10r res3 symbol) |
| ( (POS r0) (NEG r1) (SUB b) ) |
| ); mrdn |
| |
| ( mrdn_hv (s8phirs_10r res3 symbol) |
| ( (POS POS) (NEG NEG) (SUB b) ) |
| ); mrdn_hv |
| |
| ; PARASITIC DEVICES |
| |
| ((p cap c) (s8phirs_10r pcapacitor symbol) ((PLUS) (MINUS))) |
| ((p res r) (s8phirs_10r presistor symbol) ((PLUS) (MINUS))) |
| |
| ; ( (p ind l) (analogLib ind symbol) |
| ; ( (MINUS) (PLUS) ) ;apparently this is the needed order |
| ; ) ;ind |
| |
| ; ( (p mutk k) (analogLib mind symbol) |
| ; ( (ind1) (ind2) ) ;ind1 & ind2 are parameters of the mutual inductor |
| ; ) ;ind |
| |
| |
| ; LAYERS for layout view |
| |
| ; list( "calibre_layer_name" '(CDS_layer_name CDS_layer_purpose)) |
| ; calibre layer should be connected layer or device layer |
| |
| mgc_layer_map( list( |
| ; basic conducting layers |
| list( "MosNwell" '(nwell drawing) ) |
| list( "Substrate" '(psdm drawin) ) |
| list( "POLY_cond" '(poly drawing) ) |
| ; list( "DDLI_cond" '(ddli drawing) ) |
| ; list( "LITR_cond" '(litr drawing) ) |
| list( "MET1_cond" '(met1 drawing) ) |
| list( "MET2_cond" '(met2 drawing) ) |
| list( "MET3_cond" '(met3 drawing) ) |
| list( "MET4_cond" '(met4 drawing) ) |
| list( "MET5_cond" '(met5 drawing) ) |
| ; other conducting layers |
| ; list( "NDIFF_rcon" '(nsdm drawing) ) |
| ; list( "NDIFF_nrcon" '(nsdm drawing) ) |
| ; list( "PDIFF_rcon" '(psdm drawing) ) |
| ; list( "NFOM_cond" '(nsdm drawing) ) |
| ; list( "PFOM_cond" '(psdm drawing) ) |
| ; list( "ddlicon_POLY" '(ddlicon drawing) ) |
| ; list( "ddlicon_LITR" '(ddlicon drawing) ) |
| ; list( "DDLI_cond_nr_nrcon" '(ddli drawing) ) |
| ; list( "LITR_NOPOLY_cond" '(litr drawing) ) |
| ; list( "litr_NFOM" '(litr drawing) ) |
| ; list( "litr_PFOM" '(litr drawing) ) |
| ; list( "LITR_cond_nr_nrcon" '(litr drawing) ) |
| list( "MET1_cond_nrc" '(met1 drawing) ) |
| list( "MET2_cond_nrc" '(met2 drawing) ) |
| list( "MET3_cond_nrc" '(met3 drawing) ) |
| list( "MET4_cond_nrc" '(met4 drawing) ) |
| list( "MET5_cond_nrc" '(met5 drawing) ) |
| ; via layers |
| list( "mcon" '(mcon drawing) ) |
| list( "via" '(via drawing) ) |
| list( "via2" '(via2 drawing) ) |
| list( "via3" '(via3 drawing) ) |
| ; list( "capmvia3" '(via3 drawing) ) |
| ; list( "via3_notcapm" '(via3 drawing) ) |
| ; list( "via4" '(via4 drawing) ) |
| ; list( "cap2mvia4" '(via4 drawing) ) |
| ; list( "via4_notcap2m" '(via4 drawing) ) |
| ; list( "via5" '(via5 drawing) ) |
| ; list( "via6" '(via6 drawing) ) |
| ; other via related layers |
| ; list( "NTAP_cont" '(tap drawing) ) |
| ; list( "NTAP_cond" '(tap drawing) ) |
| ; list( "PTAP_cont" '(tap drawing) ) |
| ; list( "PTAP_cond" '(tap drawing) ) |
| ; MOS device recognition layers |
| list( "nshortnormGate" '(poly drawing) ) |
| ; list( "nshort_lnormGate" '(poly drawing) ) |
| ; list( "nthicknormGate" '(poly drawing) ) |
| ; list( "lvnnativenormGate" '(poly drawing) ) |
| list( "pshortnormGate" '(poly drawing) ) |
| ; list( "pshort_lnormGate" '(poly drawing) ) |
| ; list( "pthicknormGate" '(poly drawing) ) |
| ; other device recognition layers |
| ; list( "rdn" '(nsdm drawing) ) |
| ; list( "rdp" '(psdm drawing) ) |
| ; list( "rp1" '(poly drawing) ) |
| ; list( "cintdig1" '(poly drawing) ) |
| ; list( "cintdig2" '(poly drawing) ) |
| ; list( "capm_mimcap" '(met3 drawing) ) |
| ; list( "cap2m_mimcap" '(met4 drawing) ) |
| ; list( "pnppar" '(poly drawing) ) |
| ; list( "nDiode_par_lv" '(poly drawing) ) |
| ; list( "pDiode_par_lv" '(poly drawing) ) |
| ; list( "q1nwDiode_par" '(poly drawing) ) |
| ; list( "rdn_8_2_new" '(instance drawing) ) |
| ; list( "rdn_6_2_new" '(instance drawing) ) |
| ; list( "rdn_6_1_new" '(instance drawing) ) |
| ; list( "rdn_4_1_new" '(instance drawing) ) |
| ; list( "rdp_8_2_new" '(instance drawing) ) |
| ; list( "rdp_8_3_new" '(instance drawing) ) |
| ; list( "rdn_6_2_new" '(instance drawing) ) |
| ; list( "rdn_6_3_new" '(instance drawing) ) |
| ; list( "m5fuse " '(met5 drawing) ) |
| ; list( "m7fuse " '(met7 drawing) ) |
| ; list( "m1short " '(met1 short) ) |
| ; list( "m2short " '(met2 short) ) |
| ; list( "m3short " '(met3 short) ) |
| ; list( "m4short " '(met4 short) ) |
| ; list( "m5short " '(met5 short) ) |
| ; list( "m6short " '(met6 short) ) |
| ; list( "m7short " '(met7 short) ) |
| ; other connected layers |
| ; list( "POLY_cshield" '(poly drawing) ) |
| ; list( "POLY_gshield_low" '(poly drawing) ) |
| ; list( "POLY_gshield_upp" '(poly drawing) ) |
| ; list( "LITR_cshield" '(poly drawing) ) |
| ; list( "LITR_gshield_low" '(poly drawing) ) |
| ; list( "LITR_gshield_upp" '(poly drawing) ) |
| ; list( "MET1_cshield" '(met1 drawing) ) |
| ; list( "MET1_gshield_low" '(met1 drawing) ) |
| ; list( "MET1_gshield_upp" '(met1 drawing) ) |
| ; list( "MET2_cshield" '(met2 drawing) ) |
| ; list( "MET2_gshield_low" '(met2 drawing) ) |
| ; list( "MET2_gshield_upp" '(met2 drawing) ) |
| ; list( "MET3_cshield" '(met3 drawing) ) |
| ; list( "MET3_gshield_low" '(met3 drawing) ) |
| ; list( "MET3_gshield_upp" '(met3 drawing) ) |
| ; list( "MET4_cshield" '(met4 drawing) ) |
| ; list( "MET4_gshield_low" '(met4 drawing) ) |
| ; list( "MET4_gshield_upp" '(met4 drawing) ) |
| ; list( "MET5_cshield" '(met5 drawing) ) |
| ; list( "MET5_gshield_low" '(met5 drawing) ) |
| ; list( "MET5_gshield_upp" '(met5 drawing) ) |
| ; list( "MET6_cshield" '(met6 drawing) ) |
| ; list( "MET6_gshield_low" '(met6 drawing) ) |
| ; list( "MET6_gshield_upp" '(met6 drawing) ) |
| ; list( "MET7_cshield" '(met7 drawing) ) |
| ; list( "MET7_gshield_low" '(met7 drawing) ) |
| ; list( "MET7_gshield_upp" '(met7 drawing) ) |
| ; list( "CAP3_Well_cont" '(nwell drawing) ) |
| ; list( "CAP3_NoWell_cont" '(pwell drawing) ) |
| ; pin layers |
| ; list( "ddli_pin" '(ddli pin) ) |
| list( "text_li1_pin" '(li1 label) ) |
| list( "text_met1_pin" '(met1 label) ) |
| list( "text_met2_pin" '(met2 label) ) |
| list( "text_met3_pin" '(met3 label) ) |
| list( "text_met4_pin" '(met4 label) ) |
| list( "text_met5_pin" '(met5 label) ) |
| list( "met1_pin" '(met1 pin) ) |
| list( "met2_pin" '(met2 pin) ) |
| list( "met3_pin" '(met3 pin) ) |
| list( "met4_pin" '(met4 pin) ) |
| list( "met5_pin" '(met5 pin) ) |
| ; list( "met6_pin" '(met6 pin) ) |
| ; list( "met7_pin" '(met7 pin) ) |
| ; device terminal layers |
| ; MOS |
| ; list( "POLY_res" '(poly drawing) ) |
| list( "NDIFF_cond" '(nsdm drawing) ) |
| list( "PDIFF_cond" '(psdm drawing) ) |
| ; CAP |
| ; list( "BulkTermCap_int3_cond" '(pwell drawing) ) |
| ; list( "capm_cond" '(met3 drawing) ) |
| ; list( "cap2m_cond" '(met4 drawing) ) |
| ; BJT |
| ; list( "PTAP_cond" '(psdm drawing) ) |
| ; list( "PnpNwell" '(nwell drawing) ) |
| ; list( "PNPDIFF_cond" '(psdm drawing) ) |
| ; DIODE |
| ; list( "pdiode" '(diff drawing) ) |
| list( "ndiode" '(diff drawing) ) |
| ; list( "ndiode_h" '(diff drawing) ) |
| ; list( "pdiode_h" '(diff drawing) ) |
| ; list( "xndiode" '(diff drawing) ) |
| ; list( "xpdiode" '(diff drawing) ) |
| ; list( "xpdiode_h" '(diff drawing) ) |
| ; list( "xndiode_h" '(diff drawing) ) |
| ; list( "nDiode_par_hv" '(diff drawing) ) |
| ; list( "pDiode_par_hv" '(diff drawing) ) |
| ; list( "nDiode_par_lv" '(diff drawing) ) |
| ; list( "pDiode_par_lv" '(diff drawing) ) |
| ; list( "q0nwDiode_par" '(diff drawing) ) |
| ; list( "q1nwDiode_par" '(diff drawing) ) |
| ; list( "q2nwDiode_par" '(diff drawing) ) |
| ; RES |
| ; list( "NPRECRES_cond" '(pwell drawing) ) |
| ; list( "PPRECRES_cond" '(pwell drawing) ) |
| ; other layers |
| ; list( "q0ddli" '(ddli drawing) ) |
| ; list( "Substrate" '(pwell drawing) ) |
| ) ;list |
| ) ;mgc_layer_map |
