180IC/GF180IC-Part1/018IC.DRC.PVS.pv054.1.yi162dr002.04/LOGIC/018/DRC-PV-000054/addendum/Include/yi162dr002_dvnwell.pvs

// This rule is created at Fri Aug 18 13:52:40 2017


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// DVNwell
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group_rules DVNWELL_CHK DVN.?
rule "DVN.1" {
    caption  Min. Width >= 4.0  ;
    inte DVNwell DVNwell -lt 4 -abut lt 90 -single_point -output region;
}

//Coded under the connectivity module
//DVN.2a {@ Min. Space to equi-potential DVNwell (Merge if less than this design rule) < 10.0
//DVN.2b {@ Min. Space to different potential DVNwell < 13.0
rule "DVN.3a" {
    caption  Min. Space to NWELL outside DVNwell < 7.0;
    not Nwell DVNwell -outputlayer _CPTMPL450000;
    exte DVNwell _CPTMPL450000 -lt 7 -abut lt 90 -single_point -output region;
}

rule "DVN.3b" {
    caption  Min. Space to NCOMP outside DVNwell >= 7.0;
    not nactive DVNwell -outputlayer _CPTMPL450001;
    exte DVNwell _CPTMPL450001 -lt 7 -abut lt 90 -single_point -output region;
}

rule "DVN.4" {
    caption  Min. DVNwell overlap to Nplus Guard-Ring (inside DVNwell) >= 3.0;
    select -outside nactive DVNwell -not -outputlayer a;
    enc a DVNwell -lt 3 -abut lt 90 -single_point -output region -inside_also -outside_also;
    not a DVNwell;
}

rule "DVN.5" {
    caption  Min. Space between Pplus Guard-Ring in P-substrate to DVNwell >= 4.0;
    exte DVNwell ptap_all -lt 4 -abut lt 90 -single_point -output region -outputlayer y;
    not pactive nTypeWell -outputlayer x;
    exte DVNwell x -lt 4 -abut lt 90 -single_point -output region -outputlayer z;
    or y z -outputlayer;
}

not ptap_all DNWELL -outputlayer ptap_all_sub; 	//because DNWELL without Nwell is isolated well 
holes ptap_all_sub -outputlayer ptap_all_sub_big_hole:1;
select -donut ptap_all_sub -outputlayer ptap_all_sub_big_hole:2;
not ptap_all_sub_big_hole:1 ptap_all_sub_big_hole:2 -outputlayer ptap_all_sub_big_hole;
select -outside ptap_all_sub_big_hole DVNwell -not -outputlayer dvn:ptap_big_hole_dvnwell;
rule "DVN.6a" {
    caption  All DVNwell shall be surrounded by Pplus guard-rings in P-substrate without any disconnect;
    caption  Debug1 : No or broken Pplus guard-rings;
    select -inside DVNwell dvn:ptap_big_hole_dvnwell -not;
}

rule "DVN.6b" {
    caption  Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential;
    caption  Debug1 : Pplus guard-ring is surrounding 2 or more DVNwells;
    select -enclose dvn:ptap_big_hole_dvnwell DVNwell -gt 1 -outputlayer dvn.6a:a; 	//ensure only 1 DVNwell
    select -outside DVNwell dvn.6a:a -not;
}

rule "DVN.6c" {
    caption  No device or any drawing layer are allowed in between DVNwell to Pplus guard ring;
    caption  Debug1 : Refer to diagram for list of not allowed layers: Nwell, Poly2, NCOMP, HVNDDD, NAT;
    not dvn:ptap_big_hole_dvnwell DVNwell -outputlayer x;
    and x Nwell;
    and x Poly2;
    and x nactive;
    and x HVNDDD;
    and x NAT;
}

rule "DVN.6c_no_direct_dvnwell_without_Pgring" {
    caption  No device or any drawing layer are allowed in between DVNwell to Pplus guard ring;
    caption  Debug1 : Refer to diagram for list of not allowed layers: Nwell, Poly2, NCOMP, HVNDDD, NAT;
    caption  Debug2 : This is to detect all DVNwell without Pplus guard-ring that cause error to DVN.6c;
    not dvn:ptap_big_hole_dvnwell DVNwell -outputlayer x;
    and x Nwell -outputlayer y1;
    and x Poly2 -outputlayer y2;
    and x nactive -outputlayer y3;
    and x HVNDDD -outputlayer y4;
    and x NAT -outputlayer y5;
    or y1 y2 -outputlayer _CPTMPL450019;
    or _CPTMPL450019 y3 -outputlayer _CPTMPL450020;
    or _CPTMPL450020 y4 -outputlayer _CPTMPL450021;
    or _CPTMPL450021 y5 -outputlayer y;
    select -outside dvn:ptap_big_hole_dvnwell y -not -outputlayer z;
    and z DVNwell;
}

rule "DVN.7" {
    caption  All DVNwell should be lied in LDMOS_XTOR (except for SCH diode device);
    select -outside DVNwell Schottky_diode -outputlayer dvnwell_xsdiode;
    not dvnwell_xsdiode LDMOS_XTOR;
}

rule "DVN.8" {
    caption  No Nwell layer is allowed inside DVNwell (DVNwell for device region will be identified with HVPDDD layer);
    select -outside DVNwell HVPDDD -not -outputlayer dvnwell_hvpddd;
    and Nwell dvnwell_hvpddd;
}