Fix the graphic references in the cell documentation.
Also remove unneeded directive in images.
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
diff --git a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.rst b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.rst
index 1130dca..1101adf 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__addf_1 symbol**
-.. image:: sc9_sym/ADDF_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__addf_1 schematic**
-.. image:: sc9_sch/ADDF_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__addf_1 layout**
-.. image:: sc9_lay/ADDF_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_1 layout
-.. include:: images.rst
+
| ADDF_X1 is a 1 bit Full Adder with 1X drive strength
|
diff --git a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.rst b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.rst
index 35de376..23d99bf 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__addf_2 symbol**
-.. image:: sc9_sym/ADDF_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__addf_2 schematic**
-.. image:: sc9_sch/ADDF_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__addf_2 layout**
-.. image:: sc9_lay/ADDF_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_2 layout
-.. include:: images.rst
+
| ADDF_X2 is a 1 bit Full Adder with 2X drive strength
|
@@ -77,7 +68,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image11|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.rst b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.rst
index 92e08fd..c26cae3 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__addf_4 symbol**
-.. image:: sc9_sym/ADDF_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__addf_4 schematic**
-.. image:: sc9_sch/ADDF_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__addf_4 layout**
-.. image:: sc9_lay/ADDF_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addf_4 layout
-.. include:: images.rst
+
| ADDF_X4 is a 1 bit Full Adder with 4X drive strength
|
@@ -77,7 +68,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image14|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addf_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.rst b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.rst
index 166297f..68e78c1 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__addh_1 symbol**
-.. image:: sc9_sym/ADDH_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__addh_1 schematic**
-.. image:: sc9_sch/ADDH_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__addh_1 layout**
-.. image:: sc9_lay/ADDH_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_1 layout
-.. include:: images.rst
+
| ADDH_X1 is a 1 bit Half Adder with 1X drive strength
|
@@ -70,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image17|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.rst b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.rst
index f538cfc..4fc81e4 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__addh_2 symbol**
-.. image:: sc9_sym/ADDH_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__addh_2 schematic**
-.. image:: sc9_sch/ADDH_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__addh_2 layout**
-.. image:: sc9_lay/ADDH_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_2 layout
-.. include:: images.rst
+
| ADDH_X2 is a 1 bit Half Adder with 2X drive strength
|
@@ -70,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image20|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.rst b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.rst
index 1a29b1c..a38e976 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__addh_4 symbol**
-.. image:: sc9_sym/ADDH_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__addh_4 schematic**
-.. image:: sc9_sch/ADDH_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__addh_4 layout**
-.. image:: sc9_lay/ADDH_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__addh_4 layout
-.. include:: images.rst
+
| ADDH_X4 is a 1 bit Half Adder with 4X drive strength
|
@@ -70,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image23|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__addh_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.rst b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.rst
index cc21e7b..82e84cf 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and2_1 symbol**
-.. image:: sc9_sym/AND2_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__and2_1 schematic**
-.. image:: sc9_sch/AND2_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__and2_1 layout**
-.. image:: sc9_lay/AND2_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_1 layout
-.. include:: images.rst
+
| AND2_X1 is a 2-input AND with 1X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image26|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.rst b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.rst
index b052a57..b731f04 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and2_2 symbol**
-.. image:: sc9_sym/AND2_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__and2_2 schematic**
-.. image:: sc9_sch/AND2_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__and2_2 layout**
-.. image:: sc9_lay/AND2_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_2 layout
-.. include:: images.rst
+
| AND2_X2 is a 2-input AND with 2X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image29|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.rst b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.rst
index b853f9d..efd18ed 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and2_4 symbol**
-.. image:: sc9_sym/AND2_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__and2_4 schematic**
-.. image:: sc9_sch/AND2_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__and2_4 layout**
-.. image:: sc9_lay/AND2_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and2_4 layout
-.. include:: images.rst
+
| AND2_X4 is a 2-input AND with 4X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image32|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and2_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.rst b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.rst
index e001c29..71a2062 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and3_1 symbol**
-.. image:: sc9_sym/AND3_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__and3_1 schematic**
-.. image:: sc9_sch/AND3_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__and3_1 layout**
-.. image:: sc9_lay/AND3_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_1 layout
-.. include:: images.rst
+
| AND3_X1 is a 3-input AND with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image35|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.rst b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.rst
index e07d549..f47fd56 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and3_2 symbol**
-.. image:: sc9_sym/AND3_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__and3_2 schematic**
-.. image:: sc9_sch/AND3_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__and3_2 layout**
-.. image:: sc9_lay/AND3_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_2 layout
-.. include:: images.rst
+
| AND3_X2 is a 3-input AND with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image38|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.rst b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.rst
index fcc62b4..2d840b9 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and3_4 symbol**
-.. image:: sc9_sym/AND3_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__and3_4 schematic**
-.. image:: sc9_sch/AND3_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__and3_4 layout**
-.. image:: sc9_lay/AND3_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and3_4 layout
-.. include:: images.rst
+
| AND3_X4 is a 3-input AND with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image41|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and3_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.rst b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.rst
index 9fd106e..e81e574 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and4_1 symbol**
-.. image:: sc9_sym/AND4_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__and4_1 schematic**
-.. image:: sc9_sch/AND4_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__and4_1 layout**
-.. image:: sc9_lay/AND4_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_1 layout
-.. include:: images.rst
+
| AND4_X1 is a 4-input AND with 1X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image44|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.rst b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.rst
index 1954e43..4138a36 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and4_2 symbol**
-.. image:: sc9_sym/AND4_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__and4_2 schematic**
-.. image:: sc9_sch/AND4_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__and4_2 layout**
-.. image:: sc9_lay/AND4_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_2 layout
-.. include:: images.rst
+
| AND4_X2 is a 4-input AND with 2X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image47|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.rst b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.rst
index 312aa27..37326a3 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__and4_4 symbol**
-.. image:: sc9_sym/AND4_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__and4_4 schematic**
-.. image:: sc9_sch/AND4_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__and4_4 layout**
-.. image:: sc9_lay/AND4_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__and4_4 layout
-.. include:: images.rst
+
| AND4_X4 is a 4-input AND with 4X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image50|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__and4_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.rst b/cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.rst
index eff2565..633fe4b 100644
--- a/cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.rst
+++ b/cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__antenna symbol**
-.. image:: sc9_sym/ANTENNA_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__antenna.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__antenna symbol
**gf180mcu_fd_sc_mcu9t5v0__antenna schematic**
-.. image:: sc9_sch/ANTENNA_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__antenna.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__antenna schematic
**gf180mcu_fd_sc_mcu9t5v0__antenna layout**
-.. image:: sc9_lay/ANTENNA_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__antenna.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__antenna layout
-.. include:: images.rst
+
| ANTENNA is an antenna cell
|
@@ -40,7 +31,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image53|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__antenna.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.rst b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.rst
index a866a4d..954ae27 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi21_1 symbol**
-.. image:: sc9_sym/AOI21_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi21_1 schematic**
-.. image:: sc9_sch/AOI21_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi21_1 layout**
-.. image:: sc9_lay/AOI21_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_1 layout
-.. include:: images.rst
+
| AOI21_X1 is a 2-input AND into 2-input NOR with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image65|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.rst b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.rst
index 9de8bcd..0f7a61f 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi21_2 symbol**
-.. image:: sc9_sym/AOI21_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi21_2 schematic**
-.. image:: sc9_sch/AOI21_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi21_2 layout**
-.. image:: sc9_lay/AOI21_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_2 layout
-.. include:: images.rst
+
| AOI21_X2 is a 2-input AND into 2-input NOR with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image68|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.rst b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.rst
index e338c26..551a84c 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi21_4 symbol**
-.. image:: sc9_sym/AOI21_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi21_4 schematic**
-.. image:: sc9_sch/AOI21_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi21_4 layout**
-.. image:: sc9_lay/AOI21_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi21_4 layout
-.. include:: images.rst
+
| AOI21_X4 is a 2-input AND into 2-input NOR with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image71|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi21_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.rst b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.rst
index d43ee1a..3825568 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi211_1 symbol**
-.. image:: sc9_sym/AOI211_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi211_1 schematic**
-.. image:: sc9_sch/AOI211_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi211_1 layout**
-.. image:: sc9_lay/AOI211_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_1 layout
-.. include:: images.rst
+
| AOI211_X1 is a 2-input AND into 3-input NOR with 1X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image56|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.rst b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.rst
index 4a92bdb..d79ceb9 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi211_2 symbol**
-.. image:: sc9_sym/AOI211_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi211_2 schematic**
-.. image:: sc9_sch/AOI211_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi211_2 layout**
-.. image:: sc9_lay/AOI211_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_2 layout
-.. include:: images.rst
+
| AOI211_X2 is a 2-input AND into 3-input NOR with 2X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image59|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.rst b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.rst
index cbfd099..4435a5d 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi211_4 symbol**
-.. image:: sc9_sym/AOI211_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi211_4 schematic**
-.. image:: sc9_sch/AOI211_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi211_4 layout**
-.. image:: sc9_lay/AOI211_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi211_4 layout
-.. include:: images.rst
+
| AOI211_X4 is a 2-input AND into 3-input NOR with 4X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image62|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi211_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.rst b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.rst
index 94dbc1e..f25c82a 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi22_1 symbol**
-.. image:: sc9_sym/AOI22_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi22_1 schematic**
-.. image:: sc9_sch/AOI22_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi22_1 layout**
-.. image:: sc9_lay/AOI22_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_1 layout
-.. include:: images.rst
+
| AOI22_X1 is a two 2-input AND into 2-input NOR with 1X drive strength
|
@@ -61,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image92|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.rst b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.rst
index 58a50ee..4adcecc 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi22_2 symbol**
-.. image:: sc9_sym/AOI22_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi22_2 schematic**
-.. image:: sc9_sch/AOI22_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi22_2 layout**
-.. image:: sc9_lay/AOI22_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_2 layout
-.. include:: images.rst
+
| AOI22_X2 is a two 2-input AND into 2-input NOR with 2X drive strength
|
@@ -61,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image95|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.rst b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.rst
index 33dfe26..59e4cf6 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi22_4 symbol**
-.. image:: sc9_sym/AOI22_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi22_4 schematic**
-.. image:: sc9_sch/AOI22_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi22_4 layout**
-.. image:: sc9_lay/AOI22_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi22_4 layout
-.. include:: images.rst
+
| AOI22_X4 is a two 2-input AND into 2-input NOR with 4X drive strength
|
@@ -61,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image98|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi22_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.rst b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.rst
index 74c8534..aac9c12 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi221_1 symbol**
-.. image:: sc9_sym/AOI221_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi221_1 schematic**
-.. image:: sc9_sch/AOI221_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi221_1 layout**
-.. image:: sc9_lay/AOI221_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_1 layout
-.. include:: images.rst
+
| AOI221_X1 is a two 2-input AND into 3-input NOR with 1X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image74|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.rst b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.rst
index 0c985fa..5382c47 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi221_2 symbol**
-.. image:: sc9_sym/AOI221_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi221_2 schematic**
-.. image:: sc9_sch/AOI221_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi221_2 layout**
-.. image:: sc9_lay/AOI221_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_2 layout
-.. include:: images.rst
+
| AOI221_X2 is a two 2-input AND into 3-input NOR with 2X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image77|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.rst b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.rst
index 37d04f0..4a7080e 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi221_4 symbol**
-.. image:: sc9_sym/AOI221_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi221_4 schematic**
-.. image:: sc9_sch/AOI221_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi221_4 layout**
-.. image:: sc9_lay/AOI221_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi221_4 layout
-.. include:: images.rst
+
| AOI221_X4 is a two 2-input AND into 3-input NOR with 4X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image80|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi221_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.rst b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.rst
index 654354b..75082a3 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi222_1 symbol**
-.. image:: sc9_sym/AOI222_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi222_1 schematic**
-.. image:: sc9_sch/AOI222_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi222_1 layout**
-.. image:: sc9_lay/AOI222_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_1 layout
-.. include:: images.rst
+
| AOI222_X1 is a three 2-input AND into 3-input NOR with 1X drive strength
|
@@ -67,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image83|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.rst b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.rst
index 45a6fdc..a9a3cd2 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi222_2 symbol**
-.. image:: sc9_sym/AOI222_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi222_2 schematic**
-.. image:: sc9_sch/AOI222_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi222_2 layout**
-.. image:: sc9_lay/AOI222_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_2 layout
-.. include:: images.rst
+
| AOI222_X2 is a three 2-input AND into 3-input NOR with 2X drive strength
|
@@ -67,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image86|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.rst b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.rst
index da584e7..77302f6 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__aoi222_4 symbol**
-.. image:: sc9_sym/AOI222_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__aoi222_4 schematic**
-.. image:: sc9_sch/AOI222_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__aoi222_4 layout**
-.. image:: sc9_lay/AOI222_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__aoi222_4 layout
-.. include:: images.rst
+
| AOI222_X4 is a three 2-input AND into 3-input NOR with 4X drive strength
|
@@ -67,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image89|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__aoi222_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.rst b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.rst
index d0016e4..2e0fd1b 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__buf_1 symbol**
-.. image:: sc9_sym/BUF_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__buf_1 schematic**
-.. image:: sc9_sch/BUF_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__buf_1 layout**
-.. image:: sc9_lay/BUF_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_1 layout
-.. include:: images.rst
+
| BUF_X1 is a buffer with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image122|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.rst b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.rst
index e2688a0..2818d9c 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__buf_x12 symbol**
-.. image:: sc9_sym/BUF_X12_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_12.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x12 symbol
**gf180mcu_fd_sc_mcu9t5v0__buf_x12 schematic**
-.. image:: sc9_sch/BUF_X12_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_12.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x12 schematic
**gf180mcu_fd_sc_mcu9t5v0__buf_x12 layout**
-.. image:: sc9_lay/BUF_X12_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_12.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x12 layout
-.. include:: images.rst
+
| BUF_X12 is a buffer with 12X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image125|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_12.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.rst b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.rst
index e545e67..1a6fd55 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__buf_x16 symbol**
-.. image:: sc9_sym/BUF_X16_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_16.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x16 symbol
**gf180mcu_fd_sc_mcu9t5v0__buf_x16 schematic**
-.. image:: sc9_sch/BUF_X16_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_16.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x16 schematic
**gf180mcu_fd_sc_mcu9t5v0__buf_x16 layout**
-.. image:: sc9_lay/BUF_X16_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_16.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x16 layout
-.. include:: images.rst
+
| BUF_X16 is a buffer with 16X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image128|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_16.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.rst b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.rst
index abf1571..c2ed508 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__buf_2 symbol**
-.. image:: sc9_sym/BUF_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__buf_2 schematic**
-.. image:: sc9_sch/BUF_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__buf_2 layout**
-.. image:: sc9_lay/BUF_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_2 layout
-.. include:: images.rst
+
| BUF_X2 is a buffer with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image131|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.rst b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.rst
index 0f901a5..b5596e6 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__buf_x20 symbol**
-.. image:: sc9_sym/BUF_X20_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_20.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x20 symbol
**gf180mcu_fd_sc_mcu9t5v0__buf_x20 schematic**
-.. image:: sc9_sch/BUF_X20_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_20.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x20 schematic
**gf180mcu_fd_sc_mcu9t5v0__buf_x20 layout**
-.. image:: sc9_lay/BUF_X20_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_20.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_x20 layout
-.. include:: images.rst
+
BUF_X20 is a buffer with 20X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image134|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_20.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.rst b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.rst
index f8bf7e4..024b296 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__buf_3 symbol**
-.. image:: sc9_sym/BUF_X3_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_3.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_3 symbol
**gf180mcu_fd_sc_mcu9t5v0__buf_3 schematic**
-.. image:: sc9_sch/BUF_X3_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_3.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_3 schematic
**gf180mcu_fd_sc_mcu9t5v0__buf_3 layout**
-.. image:: sc9_lay/BUF_X3_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_3.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_3 layout
-.. include:: images.rst
+
| BUF_X3 is a buffer with 3X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image137|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_3.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.rst b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.rst
index e349342..af8b3ee 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__buf_4 symbol**
-.. image:: sc9_sym/BUF_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__buf_4 schematic**
-.. image:: sc9_sch/BUF_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__buf_4 layout**
-.. image:: sc9_lay/BUF_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_4 layout
-.. include:: images.rst
+
| BUF_X4 is a buffer with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image140|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.rst b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.rst
index eaed5b9..034996b 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__buf_8 symbol**
-.. image:: sc9_sym/BUF_X8_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_8.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_8 symbol
**gf180mcu_fd_sc_mcu9t5v0__buf_8 schematic**
-.. image:: sc9_sch/BUF_X8_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_8.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_8 schematic
**gf180mcu_fd_sc_mcu9t5v0__buf_8 layout**
-.. image:: sc9_lay/BUF_X8_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_8.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__buf_8 layout
-.. include:: images.rst
+
| BUF_X8 is a buffer with 8X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image143|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__buf_8.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.rst b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.rst
index 765635b..d1db40b 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__bufz_1 symbol**
-.. image:: sc9_sym/BUFZ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__bufz_1 schematic**
-.. image:: sc9_sch/BUFZ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__bufz_1 layout**
-.. image:: sc9_lay/BUFZ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_1 layout
-.. include:: images.rst
+
| BUFZ_X1 is a tri-state buffer with 1X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image101|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.rst b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.rst
index 2eb1bae..6fd61b1 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__bufz_x12 symbol**
-.. image:: sc9_sym/BUFZ_X12_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_12.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_x12 symbol
**gf180mcu_fd_sc_mcu9t5v0__bufz_x12 schematic**
-.. image:: sc9_sch/BUFZ_X12_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_12.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_x12 schematic
**gf180mcu_fd_sc_mcu9t5v0__bufz_x12 layout**
-.. image:: sc9_lay/BUFZ_X12_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_12.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_x12 layout
-.. include:: images.rst
+
| BUFZ_X12 is a tri-state buffer with 12X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image104|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_12.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.rst b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.rst
index cdc2a24..60d442c 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__bufz_x16 symbol**
-.. image:: sc9_sym/BUFZ_X16_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_16.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_x16 symbol
**gf180mcu_fd_sc_mcu9t5v0__bufz_x16 schematic**
-.. image:: sc9_sch/BUFZ_X16_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_16.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_x16 schematic
**gf180mcu_fd_sc_mcu9t5v0__bufz_x16 layout**
-.. image:: sc9_lay/BUFZ_X16_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_16.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_x16 layout
-.. include:: images.rst
+
| BUFZ_X16 is a tri-state buffer with 16X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image107|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_16.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.rst b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.rst
index 572c8c1..ad09ef7 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__bufz_2 symbol**
-.. image:: sc9_sym/BUFZ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__bufz_2 schematic**
-.. image:: sc9_sch/BUFZ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__bufz_2 layout**
-.. image:: sc9_lay/BUFZ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_2 layout
-.. include:: images.rst
+
| BUFZ_X2 is a tri-state buffer with 2X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image110|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.rst b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.rst
index da2029f..32a9278 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__bufz_3 symbol**
-.. image:: sc9_sym/BUFZ_X3_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_3.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_3 symbol
**gf180mcu_fd_sc_mcu9t5v0__bufz_3 schematic**
-.. image:: sc9_sch/BUFZ_X3_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_3.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_3 schematic
**gf180mcu_fd_sc_mcu9t5v0__bufz_3 layout**
-.. image:: sc9_lay/BUFZ_X3_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_3.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_3 layout
-.. include:: images.rst
+
| BUFZ_X3 is a tri-state buffer with 3X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image113|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_3.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.rst b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.rst
index 6736128..501da60 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__bufz_4 symbol**
-.. image:: sc9_sym/BUFZ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__bufz_4 schematic**
-.. image:: sc9_sch/BUFZ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__bufz_4 layout**
-.. image:: sc9_lay/BUFZ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_4 layout
-.. include:: images.rst
+
| BUFZ_X4 is a tri-state buffer with 4X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image116|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.rst b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.rst
index c9ba8ca..137297c 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__bufz_8 symbol**
-.. image:: sc9_sym/BUFZ_X8_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_8.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_8 symbol
**gf180mcu_fd_sc_mcu9t5v0__bufz_8 schematic**
-.. image:: sc9_sch/BUFZ_X8_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_8.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_8 schematic
**gf180mcu_fd_sc_mcu9t5v0__bufz_8 layout**
-.. image:: sc9_lay/BUFZ_X8_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_8.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__bufz_8 layout
-.. include:: images.rst
+
| BUFZ_X8 is a tri-state buffer with 8X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image119|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__bufz_8.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.rst
index 6cbd7ab..8e5c9a4 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_1 symbol**
-.. image:: sc9_sym/CLKBUF_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_1 schematic**
-.. image:: sc9_sch/CLKBUF_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_1 layout**
-.. image:: sc9_lay/CLKBUF_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_1 layout
-.. include:: images.rst
+
| CLKBUF_X1 is a clock buffer with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image146|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.rst
index 0777b95..578d231 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x12 symbol**
-.. image:: sc9_sym/CLKBUF_X12_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x12 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x12 schematic**
-.. image:: sc9_sch/CLKBUF_X12_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x12 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x12 layout**
-.. image:: sc9_lay/CLKBUF_X12_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x12 layout
-.. include:: images.rst
+
| CLKBUF_X12 is a clock buffer with 12X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image149|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.rst
index 89f8938..f288c2b 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x16 symbol**
-.. image:: sc9_sym/CLKBUF_X16_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x16 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x16 schematic**
-.. image:: sc9_sch/CLKBUF_X16_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x16 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x16 layout**
-.. image:: sc9_lay/CLKBUF_X16_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x16 layout
-.. include:: images.rst
+
| CLKBUF_X16 is a clock buffer with 16X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image152|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.rst
index e52ca5a..1c30a86 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_2 symbol**
-.. image:: sc9_sym/CLKBUF_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_2 schematic**
-.. image:: sc9_sch/CLKBUF_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_2 layout**
-.. image:: sc9_lay/CLKBUF_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_2 layout
-.. include:: images.rst
+
| CLKBUF_X2 is a clock buffer with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image155|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.rst
index c4be0d0..529bbc8 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x20 symbol**
-.. image:: sc9_sym/CLKBUF_X20_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x20 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x20 schematic**
-.. image:: sc9_sch/CLKBUF_X20_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x20 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_x20 layout**
-.. image:: sc9_lay/CLKBUF_X20_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_x20 layout
-.. include:: images.rst
+
| CLKBUF_X20 is a clock buffer with 20X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image158|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.rst
index 1ff5eb8..86f6eed 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_3 symbol**
-.. image:: sc9_sym/CLKBUF_X3_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_3 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_3 schematic**
-.. image:: sc9_sch/CLKBUF_X3_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_3 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_3 layout**
-.. image:: sc9_lay/CLKBUF_X3_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_3 layout
-.. include:: images.rst
+
| CLKBUF_X3 is a clock buffer with 3X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image161|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.rst
index f08462d..7a9ddd5 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_4 symbol**
-.. image:: sc9_sym/CLKBUF_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_4 schematic**
-.. image:: sc9_sch/CLKBUF_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_4 layout**
-.. image:: sc9_lay/CLKBUF_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_4 layout
-.. include:: images.rst
+
| CLKBUF_X4 is a clock buffer with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image164|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.rst
index f4a885e..29aebe3 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_8 symbol**
-.. image:: sc9_sym/CLKBUF_X8_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_8 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_8 schematic**
-.. image:: sc9_sch/CLKBUF_X8_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_8 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkbuf_8 layout**
-.. image:: sc9_lay/CLKBUF_X8_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkbuf_8 layout
-.. include:: images.rst
+
| CLKBUF_X8 is a clock buffer with 8X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image167|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.rst b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.rst
index 2e5cafc..70c5e0a 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkinv_1 symbol**
-.. image:: sc9_sym/CLKINV_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkinv_1 schematic**
-.. image:: sc9_sch/CLKINV_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkinv_1 layout**
-.. image:: sc9_lay/CLKINV_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_1 layout
-.. include:: images.rst
+
| CLKINV_X1 is a clock inverter with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image170|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.rst b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.rst
index 37cde36..3cb8e60 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x12 symbol**
-.. image:: sc9_sym/CLKINV_X12_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_12.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x12 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x12 schematic**
-.. image:: sc9_sch/CLKINV_X12_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_12.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x12 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x12 layout**
-.. image:: sc9_lay/CLKINV_X12_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_12.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x12 layout
-.. include:: images.rst
+
| CLKINV_X12 is a clock inverter with 12X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image173|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_12.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.rst b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.rst
index ddcf7a1..8d96eed 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x16 symbol**
-.. image:: sc9_sym/CLKINV_X16_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_16.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x16 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x16 schematic**
-.. image:: sc9_sch/CLKINV_X16_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_16.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x16 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x16 layout**
-.. image:: sc9_lay/CLKINV_X16_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_16.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x16 layout
-.. include:: images.rst
+
| CLKINV_X16 is a clock inverter with 16X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image176|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_16.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.rst b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.rst
index f19b1f9..3122165 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkinv_2 symbol**
-.. image:: sc9_sym/CLKINV_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkinv_2 schematic**
-.. image:: sc9_sch/CLKINV_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkinv_2 layout**
-.. image:: sc9_lay/CLKINV_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_2 layout
-.. include:: images.rst
+
| CLKINV_X2 is a clock inverter with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image179|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.rst b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.rst
index 4b1cd53..6501e6a 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x20 symbol**
-.. image:: sc9_sym/CLKINV_X20_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_20.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x20 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x20 schematic**
-.. image:: sc9_sch/CLKINV_X20_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_20.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x20 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkinv_x20 layout**
-.. image:: sc9_lay/CLKINV_X20_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_20.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_x20 layout
-.. include:: images.rst
+
| CLKINV_X20 is a clock inverter with 20X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image182|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_20.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_3.rst b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_3.rst
index febe6c8..1250439 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_3.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_3.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkinv_3 symbol**
-.. image:: sc9_sym/CLKINV_X3_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_3.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_3 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkinv_3 schematic**
-.. image:: sc9_sch/CLKINV_X3_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_3.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_3 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkinv_3 layout**
-.. image:: sc9_lay/CLKINV_X3_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_3.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_3 layout
-.. include:: images.rst
+
| CLKINV_X3 is a clock inverter with 3X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image185|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_3.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.rst b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.rst
index 43cf6bf..a4e73b6 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkinv_4 symbol**
-.. image:: sc9_sym/CLKINV_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkinv_4 schematic**
-.. image:: sc9_sch/CLKINV_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkinv_4 layout**
-.. image:: sc9_lay/CLKINV_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_4 layout
-.. include:: images.rst
+
| CLKINV_X4 is a clock inverter with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image188|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.rst b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.rst
index 1b1446c..cd04831 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__clkinv_8 symbol**
-.. image:: sc9_sym/CLKINV_X8_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_8.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_8 symbol
**gf180mcu_fd_sc_mcu9t5v0__clkinv_8 schematic**
-.. image:: sc9_sch/CLKINV_X8_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_8.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_8 schematic
**gf180mcu_fd_sc_mcu9t5v0__clkinv_8 layout**
-.. image:: sc9_lay/CLKINV_X8_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_8.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__clkinv_8 layout
-.. include:: images.rst
+
| CLKINV_X8 is a clock inverter with 8X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image191|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__clkinv_8.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.rst b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.rst
index 6d3ce7e..ba5c8a0 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnq_1 symbol**
-.. image:: sc9_sym/DFFNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnq_1 schematic**
-.. image:: sc9_sch/DFFNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnq_1 layout**
-.. image:: sc9_lay/DFFNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_1 layout
-.. include:: images.rst
+
| DFFNQ_X1 is a negative edge triggered D-type flip flop with 1X drive strength
|
@@ -50,7 +41,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image194|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.rst b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.rst
index 0fd81b1..f7595f1 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnq_2 symbol**
-.. image:: sc9_sym/DFFNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnq_2 schematic**
-.. image:: sc9_sch/DFFNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnq_2 layout**
-.. image:: sc9_lay/DFFNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_2 layout
-.. include:: images.rst
+
| DFFNQ_X2 is a negative edge triggered D-type flip flop with 2X drive strength
|
@@ -50,7 +41,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image197|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.rst b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.rst
index ff939d2..4049b0b 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnq_4 symbol**
-.. image:: sc9_sym/DFFNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnq_4 schematic**
-.. image:: sc9_sch/DFFNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnq_4 layout**
-.. image:: sc9_lay/DFFNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnq_4 layout
-.. include:: images.rst
+
| DFFNQ_X4 is a negative edge triggered D-type flip flop with 4X drive strength
|
@@ -50,7 +41,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image200|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.rst
index ca9f4ee..98d25f8 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1 symbol**
-.. image:: sc9_sym/DFFNRNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1 schematic**
-.. image:: sc9_sch/DFFNRNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1 layout**
-.. image:: sc9_lay/DFFNRNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1 layout
-.. include:: images.rst
+
| DFFNRNQ_X1 is a negative edge triggered D-type flip flop with active low reset and 1X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image203|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.rst
index ffc5b90..ed4907c 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2 symbol**
-.. image:: sc9_sym/DFFNRNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2 schematic**
-.. image:: sc9_sch/DFFNRNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2 layout**
-.. image:: sc9_lay/DFFNRNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2 layout
-.. include:: images.rst
+
| DFFNRNQ_X2 is a negative edge triggered D-type flip flop with active low reset and 2X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image206|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.rst
index d3af366..c943121 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4 symbol**
-.. image:: sc9_sym/DFFNRNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4 schematic**
-.. image:: sc9_sch/DFFNRNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4 layout**
-.. image:: sc9_lay/DFFNRNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4 layout
-.. include:: images.rst
+
| DFFNRNQ_X4 is a negative edge triggered D-type flip flop with active low reset and 4X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image209|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.rst
index 2ab1f2b..8ba68d3 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1 symbol**
-.. image:: sc9_sym/DFFNRSNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1 schematic**
-.. image:: sc9_sch/DFFNRSNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1 layout**
-.. image:: sc9_lay/DFFNRSNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1 layout
-.. include:: images.rst
+
| DFFNRSNQ_X1 is a negative edge triggered D-type flip flop with active low set/reset and 1X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image212|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.rst
index b2b2587..0ca3d99 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2 symbol**
-.. image:: sc9_sym/DFFNRSNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2 schematic**
-.. image:: sc9_sch/DFFNRSNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2 layout**
-.. image:: sc9_lay/DFFNRSNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2 layout
-.. include:: images.rst
+
| DFFNRSNQ_X2 is a negative edge triggered D-type flip flop with active low set/reset and 2X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image215|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.rst
index 7e23aac..7606ecf 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4 symbol**
-.. image:: sc9_sym/DFFNRSNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4 schematic**
-.. image:: sc9_sch/DFFNRSNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4 layout**
-.. image:: sc9_lay/DFFNRSNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4 layout
-.. include:: images.rst
+
| DFFNRSNQ_X4 is a negative edge triggered D-type flip flop with active low set/reset and 4X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image218|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.rst
index 1481fa3..4d47b45 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1 symbol**
-.. image:: sc9_sym/DFFNSNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1 schematic**
-.. image:: sc9_sch/DFFNSNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1 layout**
-.. image:: sc9_lay/DFFNSNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1 layout
-.. include:: images.rst
+
| DFFNSNQ_X1 is a negative edge triggered D-type flip flop with active low set and 1X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image221|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.rst
index 684317b..80e5997 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2 symbol**
-.. image:: sc9_sym/DFFNSNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2 schematic**
-.. image:: sc9_sch/DFFNSNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2 layout**
-.. image:: sc9_lay/DFFNSNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2 layout
-.. include:: images.rst
+
| DFFNSNQ_X2 is a negative edge triggered D-type flip flop with active low set and 2X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image224|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.rst
index 7a4f8e9..fd732c0 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4 symbol**
-.. image:: sc9_sym/DFFNSNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4 schematic**
-.. image:: sc9_sch/DFFNSNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4 layout**
-.. image:: sc9_lay/DFFNSNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4 layout
-.. include:: images.rst
+
| DFFNSNQ_X4 is a negative edge triggered D-type flip flop with active low set and 4X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image227|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.rst b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.rst
index 30f9806..49f3ed1 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffq_1 symbol**
-.. image:: sc9_sym/DFFQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffq_1 schematic**
-.. image:: sc9_sch/DFFQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffq_1 layout**
-.. image:: sc9_lay/DFFQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_1 layout
-.. include:: images.rst
+
| DFFQ_X1 is a positive edge triggered D-type flip flop with 1X drive strength
|
@@ -50,7 +41,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image230|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.rst b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.rst
index d9f4a7a..a09e429 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffq_2 symbol**
-.. image:: sc9_sym/DFFQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffq_2 schematic**
-.. image:: sc9_sch/DFFQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffq_2 layout**
-.. image:: sc9_lay/DFFQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_2 layout
-.. include:: images.rst
+
| DFFQ_X2 is a Poisitive edge triggered D-type flip flop with 2X drive strength
|
@@ -50,7 +41,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image233|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.rst b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.rst
index 11c7931..d7ea726 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffq_4 symbol**
-.. image:: sc9_sym/DFFQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffq_4 schematic**
-.. image:: sc9_sch/DFFQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffq_4 layout**
-.. image:: sc9_lay/DFFQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffq_4 layout
-.. include:: images.rst
+
| DFFQ_X4 is a Poisitive edge triggered D-type flip flop with 4X drive strength
|
@@ -50,7 +41,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image236|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.rst
index dd3f56e..5bd67ac 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_1 symbol**
-.. image:: sc9_sym/DFFRNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_1 schematic**
-.. image:: sc9_sch/DFFRNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_1 layout**
-.. image:: sc9_lay/DFFRNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_1 layout
-.. include:: images.rst
+
| DFFRNQ_X1 is a positive edge triggered D-type flip flop with active low reset and 1X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image239|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.rst
index 6ccdaec..2a92bff 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_2 symbol**
-.. image:: sc9_sym/DFFRNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_2 schematic**
-.. image:: sc9_sch/DFFRNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_2 layout**
-.. image:: sc9_lay/DFFRNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_2 layout
-.. include:: images.rst
+
| DFFRNQ_X2 is a positive edge triggered D-type flip flop with active low reset and 2X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image242|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.rst
index bc380fd..50d7084 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_4 symbol**
-.. image:: sc9_sym/DFFRNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_4 schematic**
-.. image:: sc9_sch/DFFRNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffrnq_4 layout**
-.. image:: sc9_lay/DFFRNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrnq_4 layout
-.. include:: images.rst
+
| DFFRNQ_X4 is a positive edge triggered D-type flip flop with active low reset and 4X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image245|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.rst
index 49f0d90..975102a 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1 symbol**
-.. image:: sc9_sym/DFFRSNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1 schematic**
-.. image:: sc9_sch/DFFRSNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1 layout**
-.. image:: sc9_lay/DFFRSNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1 layout
-.. include:: images.rst
+
| DFFRSNQ_X1 is a positive edge triggered D-type flip flop with active low set/reset and 1X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image248|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.rst
index 291c26e..d0b44e9 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2 symbol**
-.. image:: sc9_sym/DFFRSNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2 schematic**
-.. image:: sc9_sch/DFFRSNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2 layout**
-.. image:: sc9_lay/DFFRSNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2 layout
-.. include:: images.rst
+
| DFFRSNQ_X2 is a positive edge triggered D-type flip flop with active low set/reset and 2X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image251|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.rst
index d3747c7..f149268 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4 symbol**
-.. image:: sc9_sym/DFFRSNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4 schematic**
-.. image:: sc9_sch/DFFRSNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4 layout**
-.. image:: sc9_lay/DFFRSNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4 layout
-.. include:: images.rst
+
| DFFRSNQ_X4 is a positive edge triggered D-type flip flop with active low set/reset and 4X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image254|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.rst
index c14267f..1ffe69c 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_1 symbol**
-.. image:: sc9_sym/DFFSNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_1 schematic**
-.. image:: sc9_sch/DFFSNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_1 layout**
-.. image:: sc9_lay/DFFSNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_1 layout
-.. include:: images.rst
+
| DFFSNQ_X1 is a positive edge triggered D-type flip flop with active low set and 1X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image257|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.rst
index 5fa0bc7..8f5ab30 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_2 symbol**
-.. image:: sc9_sym/DFFSNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_2 schematic**
-.. image:: sc9_sch/DFFSNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_2 layout**
-.. image:: sc9_lay/DFFSNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_2 layout
-.. include:: images.rst
+
| DFFSNQ_X2 is a positivee edge triggered D-type flip flop with active low set and 2X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image260|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.rst
index cc66835..3fcb003 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_4 symbol**
-.. image:: sc9_sym/DFFSNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_4 schematic**
-.. image:: sc9_sch/DFFSNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dffsnq_4 layout**
-.. image:: sc9_lay/DFFSNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dffsnq_4 layout
-.. include:: images.rst
+
| DFFSNQ_X4 is a positive edge triggered D-type flip flop with active low set and 4X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image263|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.rst b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.rst
index 0dd40ea..389f5b1 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlya_1 symbol**
-.. image:: sc9_sym/DLYA_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlya_1 schematic**
-.. image:: sc9_sch/DLYA_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlya_1 layout**
-.. image:: sc9_lay/DLYA_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_1 layout
-.. include:: images.rst
+
| DLYA_X1 is a 2 buffer delay cell with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image266|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.rst b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.rst
index d775845..b688f81 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlya_2 symbol**
-.. image:: sc9_sym/DLYA_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlya_2 schematic**
-.. image:: sc9_sch/DLYA_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlya_2 layout**
-.. image:: sc9_lay/DLYA_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_2 layout
-.. include:: images.rst
+
| DLYA_X2 is a 2 buffer delay cell with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image269|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.rst b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.rst
index d46c051..31f69cf 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlya_4 symbol**
-.. image:: sc9_sym/DLYA_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlya_4 schematic**
-.. image:: sc9_sch/DLYA_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlya_4 layout**
-.. image:: sc9_lay/DLYA_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlya_4 layout
-.. include:: images.rst
+
| DLYA_X4 is a 2 buffer delay cell with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image272|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlya_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.rst b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.rst
index c9c48ea..c4c12f3 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyb_1 symbol**
-.. image:: sc9_sym/DLYB_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyb_1 schematic**
-.. image:: sc9_sch/DLYB_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyb_1 layout**
-.. image:: sc9_lay/DLYB_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_1 layout
-.. include:: images.rst
+
| DLYB_X1 is a 4 buffer delay cell with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image275|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.rst b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.rst
index fbfcdfe..5675b38 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyb_2 symbol**
-.. image:: sc9_sym/DLYB_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyb_2 schematic**
-.. image:: sc9_sch/DLYB_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyb_2 layout**
-.. image:: sc9_lay/DLYB_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_2 layout
-.. include:: images.rst
+
| DLYB_X2 is a 4 buffer delay cell with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image278|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.rst b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.rst
index dbca526..66416dd 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyb_4 symbol**
-.. image:: sc9_sym/DLYB_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyb_4 schematic**
-.. image:: sc9_sch/DLYB_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyb_4 layout**
-.. image:: sc9_lay/DLYB_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyb_4 layout
-.. include:: images.rst
+
| DLYB_X4 is a 4 buffer delay cell with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image281|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyb_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.rst b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.rst
index f74037a..8d57d72 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyc_1 symbol**
-.. image:: sc9_sym/DLYC_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyc_1 schematic**
-.. image:: sc9_sch/DLYC_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyc_1 layout**
-.. image:: sc9_lay/DLYC_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_1 layout
-.. include:: images.rst
+
| DLYC_X1 is a 8 buffer delay cell with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image284|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.rst b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.rst
index fc68581..3ef30d4 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyc_2 symbol**
-.. image:: sc9_sym/DLYC_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyc_2 schematic**
-.. image:: sc9_sch/DLYC_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyc_2 layout**
-.. image:: sc9_lay/DLYC_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_2 layout
-.. include:: images.rst
+
| DLYC_X2 is a 8 buffer delay cell with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image287|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.rst b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.rst
index 3283f1b..e5253db 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyc_4 symbol**
-.. image:: sc9_sym/DLYC_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyc_4 schematic**
-.. image:: sc9_sch/DLYC_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyc_4 layout**
-.. image:: sc9_lay/DLYC_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyc_4 layout
-.. include:: images.rst
+
| DLYC_X4 is a 8 buffer delay cell with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image290|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyc_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_1.rst b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_1.rst
index c7e92fb..64792c5 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_1.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyd_1 symbol**
-.. image:: sc9_sym/DLYD_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyd_1 schematic**
-.. image:: sc9_sch/DLYD_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyd_1 layout**
-.. image:: sc9_lay/DLYD_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_1 layout
-.. include:: images.rst
+
| DLYD_X1 is a 16 buffer delay cell with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image293|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.rst b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.rst
index 1e20b4a..035352c 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyd_2 symbol**
-.. image:: sc9_sym/DLYD_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyd_2 schematic**
-.. image:: sc9_sch/DLYD_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyd_2 layout**
-.. image:: sc9_lay/DLYD_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_2 layout
-.. include:: images.rst
+
| DLYD_X2 is a 16 buffer delay cell with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image296|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.rst b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.rst
index 4d9146d..3fde56d 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__dlyd_4 symbol**
-.. image:: sc9_sym/DLYD_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__dlyd_4 schematic**
-.. image:: sc9_sch/DLYD_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__dlyd_4 layout**
-.. image:: sc9_lay/DLYD_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__dlyd_4 layout
-.. include:: images.rst
+
| DLYD_X4 is a 16 buffer delay cell with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image299|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__dlyd_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/endcap/gf180mcu_fd_sc_mcu9t5v0__endcap.rst b/cells/endcap/gf180mcu_fd_sc_mcu9t5v0__endcap.rst
index 6ba4715..c56c911 100644
--- a/cells/endcap/gf180mcu_fd_sc_mcu9t5v0__endcap.rst
+++ b/cells/endcap/gf180mcu_fd_sc_mcu9t5v0__endcap.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__endcap symbol**
-.. image:: sc9_sym/ENDCAP_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__endcap.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__endcap symbol
**gf180mcu_fd_sc_mcu9t5v0__endcap schematic**
-.. image:: sc9_sch/ENDCAP_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__endcap.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__endcap schematic
**gf180mcu_fd_sc_mcu9t5v0__endcap layout**
-.. image:: sc9_lay/ENDCAP_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__endcap.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__endcap layout
-.. include:: images.rst
+
| ENDCAP is a row end closure cell
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image302|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__endcap.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_1.rst b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_1.rst
index 5caeef5..a9ea813 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_1.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fill_1 symbol**
-.. image:: sc9_sym/FILL_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__fill_1 schematic**
-.. image:: sc9_sch/FILL_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__fill_1 layout**
-.. image:: sc9_lay/FILL_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_1 layout
-.. include:: images.rst
+
| FILL_X1 is a filler whose cell width is .56um
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image323|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_1.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_16.rst b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_16.rst
index 05877dc..719213e 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_16.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_16.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fill_x16 symbol**
-.. image:: sc9_sym/FILL_X16_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_16.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x16 symbol
**gf180mcu_fd_sc_mcu9t5v0__fill_x16 schematic**
-.. image:: sc9_sch/FILL_X16_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_16.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x16 schematic
**gf180mcu_fd_sc_mcu9t5v0__fill_x16 layout**
-.. image:: sc9_lay/FILL_X16_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_16.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x16 layout
-.. include:: images.rst
+
| FILL_X16 is a filler whose cell width is 8.96um
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image326|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_16.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_2.rst b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_2.rst
index 9a44469..bbefec3 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_2.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fill_2 symbol**
-.. image:: sc9_sym/FILL_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__fill_2 schematic**
-.. image:: sc9_sch/FILL_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__fill_2 layout**
-.. image:: sc9_lay/FILL_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_2 layout
-.. include:: images.rst
+
| FILL_X2 is a filler whose cell width is 1.12um
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image329|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_2.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_32.rst b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_32.rst
index 6d5bcba..0434c30 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_32.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_32.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fill_x32 symbol**
-.. image:: sc9_sym/FILL_X32_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_32.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x32 symbol
**gf180mcu_fd_sc_mcu9t5v0__fill_x32 schematic**
-.. image:: sc9_sch/FILL_X32_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_32.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x32 schematic
**gf180mcu_fd_sc_mcu9t5v0__fill_x32 layout**
-.. image:: sc9_lay/FILL_X32_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_32.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x32 layout
-.. include:: images.rst
+
| FILL_X32 is a filler whose cell width is 17.92um
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image332|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_32.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_4.rst b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_4.rst
index c840354..6f79d4a 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_4.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fill_4 symbol**
-.. image:: sc9_sym/FILL_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__fill_4 schematic**
-.. image:: sc9_sch/FILL_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__fill_4 layout**
-.. image:: sc9_lay/FILL_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_4 layout
-.. include:: images.rst
+
| FILL_X4 is a filler whose cell width is 2.24um
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image335|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_4.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_64.rst b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_64.rst
index 7a4b798..501e4f5 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_64.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_64.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fill_x64 symbol**
-.. image:: sc9_sym/FILL_X64_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_64.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x64 symbol
**gf180mcu_fd_sc_mcu9t5v0__fill_x64 schematic**
-.. image:: sc9_sch/FILL_X64_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_64.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x64 schematic
**gf180mcu_fd_sc_mcu9t5v0__fill_x64 layout**
-.. image:: sc9_lay/FILL_X64_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_64.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_x64 layout
-.. include:: images.rst
+
| FILL_X64 is a filler whose cell width is 35.84um
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image338|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_64.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_8.rst b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_8.rst
index 7a08a7e..063103a 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_8.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_8.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fill_8 symbol**
-.. image:: sc9_sym/FILL_X8_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_8.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_8 symbol
**gf180mcu_fd_sc_mcu9t5v0__fill_8 schematic**
-.. image:: sc9_sch/FILL_X8_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_8.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_8 schematic
**gf180mcu_fd_sc_mcu9t5v0__fill_8 layout**
-.. image:: sc9_lay/FILL_X8_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_8.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fill_8 layout
-.. include:: images.rst
+
| FILL_X8 is a filler whose cell width is 4.48um
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image341|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fill_8.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.rst b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.rst
index 824f2ff..14819cd 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x16 symbol**
-.. image:: sc9_sym/FILLCAP_X16_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_16.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x16 symbol
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x16 schematic**
-.. image:: sc9_sch/FILLCAP_X16_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_16.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x16 schematic
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x16 layout**
-.. image:: sc9_lay/FILLCAP_X16_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_16.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x16 layout
-.. include:: images.rst
+
| FILLCAP_X16 is a filler whose cell width is 8.96um with decoupling cap between VDD and VSS
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image305|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_16.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.rst b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.rst
index f76f7fa..964d2a0 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x32 symbol**
-.. image:: sc9_sym/FILLCAP_X32_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_32.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x32 symbol
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x32 schematic**
-.. image:: sc9_sch/FILLCAP_X32_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_32.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x32 schematic
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x32 layout**
-.. image:: sc9_lay/FILLCAP_X32_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_32.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x32 layout
-.. include:: images.rst
+
| FILLCAP_X32 is a filler whose cell width is 17.92um with decoupling cap between VDD and VSS
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image308|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_32.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.rst b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.rst
index a8e63f5..e373f9f 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fillcap_4 symbol**
-.. image:: sc9_sym/FILLCAP_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__fillcap_4 schematic**
-.. image:: sc9_sch/FILLCAP_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__fillcap_4 layout**
-.. image:: sc9_lay/FILLCAP_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_4 layout
-.. include:: images.rst
+
| FILLCAP_X4 is a filler whose cell width is 2.24um with decoupling cap between VDD and VSS
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image311|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_4.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.rst b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.rst
index 05159fd..d530e67 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x64 symbol**
-.. image:: sc9_sym/FILLCAP_X64_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_64.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x64 symbol
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x64 schematic**
-.. image:: sc9_sch/FILLCAP_X64_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_64.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x64 schematic
**gf180mcu_fd_sc_mcu9t5v0__fillcap_x64 layout**
-.. image:: sc9_lay/FILLCAP_X64_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_64.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_x64 layout
-.. include:: images.rst
+
| FILLCAP_X64 is a filler whose cell width is 35.84um with decoupling cap between VDD and VSS
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image314|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_64.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.rst b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.rst
index b6d0afd..cc92f02 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__fillcap_8 symbol**
-.. image:: sc9_sym/FILLCAP_X8_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_8.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_8 symbol
**gf180mcu_fd_sc_mcu9t5v0__fillcap_8 schematic**
-.. image:: sc9_sch/FILLCAP_X8_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_8.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_8 schematic
**gf180mcu_fd_sc_mcu9t5v0__fillcap_8 layout**
-.. image:: sc9_lay/FILLCAP_X8_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_8.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__fillcap_8 layout
-.. include:: images.rst
+
| FILLCAP_X8 is a filler whose width is 4.48um with decoupling cap between VDD and VSS
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image317|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__fillcap_8.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/filltie/gf180mcu_fd_sc_mcu9t5v0__filltie.rst b/cells/filltie/gf180mcu_fd_sc_mcu9t5v0__filltie.rst
index 71b740c..1974b60 100644
--- a/cells/filltie/gf180mcu_fd_sc_mcu9t5v0__filltie.rst
+++ b/cells/filltie/gf180mcu_fd_sc_mcu9t5v0__filltie.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__filltie symbol**
-.. image:: sc9_sym/FILLTIE_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__filltie.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__filltie symbol
**gf180mcu_fd_sc_mcu9t5v0__filltie schematic**
-.. image:: sc9_sch/FILLTIE_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__filltie.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__filltie schematic
**gf180mcu_fd_sc_mcu9t5v0__filltie layout**
-.. image:: sc9_lay/FILLTIE_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__filltie.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__filltie layout
-.. include:: images.rst
+
| FILLTIE is a filler with well and substrate tap
|
@@ -39,7 +30,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image320|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__filltie.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.rst b/cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.rst
index 48eb8c9..c21cab4 100644
--- a/cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.rst
+++ b/cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__hold symbol**
-.. image:: sc9_sym/HOLD_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__hold.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__hold symbol
**gf180mcu_fd_sc_mcu9t5v0__hold schematic**
-.. image:: sc9_sch/HOLD_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__hold.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__hold schematic
**gf180mcu_fd_sc_mcu9t5v0__hold layout**
-.. image:: sc9_lay/HOLD_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__hold.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__hold layout
-.. include:: images.rst
+
| HOLD is a state holder cell
|
@@ -56,7 +47,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image344|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__hold.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.rst b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.rst
index ac6cfc4..2b9ba19 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__icgtn_1 symbol**
-.. image:: sc9_sym/ICGTN_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__icgtn_1 schematic**
-.. image:: sc9_sch/ICGTN_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__icgtn_1 layout**
-.. image:: sc9_lay/ICGTN_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_1 layout
-.. include:: images.rst
+
| ICGTN_X1 is a negative-edge triggered clock-gating latch with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image347|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.rst b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.rst
index ee636c6..8bf4e81 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__icgtn_2 symbol**
-.. image:: sc9_sym/ICGTN_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__icgtn_2 schematic**
-.. image:: sc9_sch/ICGTN_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__icgtn_2 layout**
-.. image:: sc9_lay/ICGTN_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_2 layout
-.. include:: images.rst
+
| ICGTN_X2 is a negative-edge triggered clock-gating latch with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image350|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.rst b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.rst
index 526f20f..50453eb 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__icgtn_4 symbol**
-.. image:: sc9_sym/ICGTN_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__icgtn_4 schematic**
-.. image:: sc9_sch/ICGTN_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__icgtn_4 layout**
-.. image:: sc9_lay/ICGTN_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtn_4 layout
-.. include:: images.rst
+
| ICGTN_X4 is a negative-edge triggered clock-gating latch with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image353|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtn_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.rst b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.rst
index 6324f81..bc6095d 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__icgtp_1 symbol**
-.. image:: sc9_sym/ICGTP_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__icgtp_1 schematic**
-.. image:: sc9_sch/ICGTP_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__icgtp_1 layout**
-.. image:: sc9_lay/ICGTP_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_1 layout
-.. include:: images.rst
+
| ICGTP_X1 is a positive-edge triggered clock-gating latch with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image356|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.rst b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.rst
index 0bc768d..ce218c3 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__icgtp_2 symbol**
-.. image:: sc9_sym/ICGTP_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__icgtp_2 schematic**
-.. image:: sc9_sch/ICGTP_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__icgtp_2 layout**
-.. image:: sc9_lay/ICGTP_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_2 layout
-.. include:: images.rst
+
| ICGTP_X2 is a positive-edge triggered clock-gating latch with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image359|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.rst b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.rst
index 938762a..8bc68ed 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__icgtp_4 symbol**
-.. image:: sc9_sym/ICGTP_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__icgtp_4 schematic**
-.. image:: sc9_sch/ICGTP_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__icgtp_4 layout**
-.. image:: sc9_lay/ICGTP_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__icgtp_4 layout
-.. include:: images.rst
+
| ICGTP_X4 is a positive-edge triggered clock-gating latch with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image362|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__icgtp_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.rst b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.rst
index 56fe75e..16a606f 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__inv_1 symbol**
-.. image:: sc9_sym/INV_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__inv_1 schematic**
-.. image:: sc9_sch/INV_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__inv_1 layout**
-.. image:: sc9_lay/INV_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_1 layout
-.. include:: images.rst
+
| INV_X1 is an inverter with 1X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image386|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.rst b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.rst
index a1e609d..a02f34d 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__inv_x12 symbol**
-.. image:: sc9_sym/INV_X12_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_12.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x12 symbol
**gf180mcu_fd_sc_mcu9t5v0__inv_x12 schematic**
-.. image:: sc9_sch/INV_X12_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_12.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x12 schematic
**gf180mcu_fd_sc_mcu9t5v0__inv_x12 layout**
-.. image:: sc9_lay/INV_X12_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_12.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x12 layout
-.. include:: images.rst
+
| INV_X12 is an inverter with 12X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image389|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_12.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.rst b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.rst
index 840f2c3..955c20f 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__inv_x16 symbol**
-.. image:: sc9_sym/INV_X16_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_16.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x16 symbol
**gf180mcu_fd_sc_mcu9t5v0__inv_x16 schematic**
-.. image:: sc9_sch/INV_X16_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_16.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x16 schematic
**gf180mcu_fd_sc_mcu9t5v0__inv_x16 layout**
-.. image:: sc9_lay/INV_X16_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_16.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x16 layout
-.. include:: images.rst
+
| INV_X16 is an inverter with 16X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image392|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_16.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.rst b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.rst
index a656b80..e0c7b77 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__inv_2 symbol**
-.. image:: sc9_sym/INV_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__inv_2 schematic**
-.. image:: sc9_sch/INV_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__inv_2 layout**
-.. image:: sc9_lay/INV_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_2 layout
-.. include:: images.rst
+
| INV_X2 is an inverter with 2X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image395|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.rst b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.rst
index e469991..423a1b4 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__inv_x20 symbol**
-.. image:: sc9_sym/INV_X20_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_20.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x20 symbol
**gf180mcu_fd_sc_mcu9t5v0__inv_x20 schematic**
-.. image:: sc9_sch/INV_X20_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_20.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x20 schematic
**gf180mcu_fd_sc_mcu9t5v0__inv_x20 layout**
-.. image:: sc9_lay/INV_X20_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_20.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_x20 layout
-.. include:: images.rst
+
| INV_X20 is an inverter with 20X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image398|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_20.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.rst b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.rst
index fc8c2ac..86efd7c 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__inv_3 symbol**
-.. image:: sc9_sym/INV_X3_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_3.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_3 symbol
**gf180mcu_fd_sc_mcu9t5v0__inv_3 schematic**
-.. image:: sc9_sch/INV_X3_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_3.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_3 schematic
**gf180mcu_fd_sc_mcu9t5v0__inv_3 layout**
-.. image:: sc9_lay/INV_X3_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_3.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_3 layout
-.. include:: images.rst
+
| INV_X3 is an inverter with 3X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image401|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_3.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.rst b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.rst
index f62552e..806bba1 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__inv_4 symbol**
-.. image:: sc9_sym/INV_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__inv_4 schematic**
-.. image:: sc9_sch/INV_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__inv_4 layout**
-.. image:: sc9_lay/INV_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_4 layout
-.. include:: images.rst
+
| INV_X4 is an inverter with 4X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image404|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.rst b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.rst
index 87ab039..4b4c93a 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__inv_8 symbol**
-.. image:: sc9_sym/INV_X8_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_8.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_8 symbol
**gf180mcu_fd_sc_mcu9t5v0__inv_8 schematic**
-.. image:: sc9_sch/INV_X8_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_8.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_8 schematic
**gf180mcu_fd_sc_mcu9t5v0__inv_8 layout**
-.. image:: sc9_lay/INV_X8_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_8.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__inv_8 layout
-.. include:: images.rst
+
| INV_X8 is an inverter with 8X drive strength
|
@@ -57,7 +48,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image407|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__inv_8.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.rst b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.rst
index 3ed118c..8990569 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__invz_1 symbol**
-.. image:: sc9_sym/INVZ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__invz_1 schematic**
-.. image:: sc9_sch/INVZ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__invz_1 layout**
-.. image:: sc9_lay/INVZ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_1 layout
-.. include:: images.rst
+
| INVZ_X1 is a tri-state inverter with 1X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image365|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.rst b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.rst
index bacf216..3ea8236 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__invz_x12 symbol**
-.. image:: sc9_sym/INVZ_X12_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_12.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_x12 symbol
**gf180mcu_fd_sc_mcu9t5v0__invz_x12 schematic**
-.. image:: sc9_sch/INVZ_X12_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_12.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_x12 schematic
**gf180mcu_fd_sc_mcu9t5v0__invz_x12 layout**
-.. image:: sc9_lay/INVZ_X12_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_12.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_x12 layout
-.. include:: images.rst
+
| INVZ_X12 is a tri-state inverter with 12X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image368|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_12.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.rst b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.rst
index d1e17b0..14894c6 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__invz_x16 symbol**
-.. image:: sc9_sym/INVZ_X16_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_16.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_x16 symbol
**gf180mcu_fd_sc_mcu9t5v0__invz_x16 schematic**
-.. image:: sc9_sch/INVZ_X16_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_16.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_x16 schematic
**gf180mcu_fd_sc_mcu9t5v0__invz_x16 layout**
-.. image:: sc9_lay/INVZ_X16_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_16.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_x16 layout
-.. include:: images.rst
+
| INVZ_X16 is a tri-state inverter with 16X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image371|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_16.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.rst b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.rst
index 52da272..2d2ee02 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__invz_2 symbol**
-.. image:: sc9_sym/INVZ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__invz_2 schematic**
-.. image:: sc9_sch/INVZ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__invz_2 layout**
-.. image:: sc9_lay/INVZ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_2 layout
-.. include:: images.rst
+
| INVZ_X2 is a tri-state inverter with 2X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image374|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.rst b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.rst
index cfe2f60..a3da0c0 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__invz_3 symbol**
-.. image:: sc9_sym/INVZ_X3_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_3.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_3 symbol
**gf180mcu_fd_sc_mcu9t5v0__invz_3 schematic**
-.. image:: sc9_sch/INVZ_X3_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_3.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_3 schematic
**gf180mcu_fd_sc_mcu9t5v0__invz_3 layout**
-.. image:: sc9_lay/INVZ_X3_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_3.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_3 layout
-.. include:: images.rst
+
| INVZ_X3 is a tri-state inverter with 3X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image377|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_3.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.rst b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.rst
index e60c879..23fa8f1 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__invz_4 symbol**
-.. image:: sc9_sym/INVZ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__invz_4 schematic**
-.. image:: sc9_sch/INVZ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__invz_4 layout**
-.. image:: sc9_lay/INVZ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_4 layout
-.. include:: images.rst
+
| INVZ_X4 is a tri-state inverter with 4X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image380|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.rst b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.rst
index 133b0cb..9162800 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__invz_8 symbol**
-.. image:: sc9_sym/INVZ_X8_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_8.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_8 symbol
**gf180mcu_fd_sc_mcu9t5v0__invz_8 schematic**
-.. image:: sc9_sch/INVZ_X8_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_8.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_8 schematic
**gf180mcu_fd_sc_mcu9t5v0__invz_8 layout**
-.. image:: sc9_lay/INVZ_X8_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_8.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__invz_8 layout
-.. include:: images.rst
+
| INVZ_X8 is a tri-state inverter with 8X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image383|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__invz_8.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.rst b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.rst
index e4924b4..0e413af 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latq_1 symbol**
-.. image:: sc9_sym/LATQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__latq_1 schematic**
-.. image:: sc9_sch/LATQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__latq_1 layout**
-.. image:: sc9_lay/LATQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_1 layout
-.. include:: images.rst
+
| LATQ_X1 is a positive D-latch with 1X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image410|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.rst b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.rst
index 8ac7c65..0c90a31 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latq_2 symbol**
-.. image:: sc9_sym/LATQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__latq_2 schematic**
-.. image:: sc9_sch/LATQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__latq_2 layout**
-.. image:: sc9_lay/LATQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_2 layout
-.. include:: images.rst
+
| LATQ_X2 is a positive D-latch with 2X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image413|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.rst b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.rst
index cea36d8..8151e89 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latq_4 symbol**
-.. image:: sc9_sym/LATQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__latq_4 schematic**
-.. image:: sc9_sch/LATQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__latq_4 layout**
-.. image:: sc9_lay/LATQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latq_4 layout
-.. include:: images.rst
+
| LATQ_X4 is a positive D-latch with 4X drive strength
|
@@ -51,7 +42,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image416|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.rst b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.rst
index a711ee6..8bd9f46 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latrnq_1 symbol**
-.. image:: sc9_sym/LATRNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__latrnq_1 schematic**
-.. image:: sc9_sch/LATRNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__latrnq_1 layout**
-.. image:: sc9_lay/LATRNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_1 layout
-.. include:: images.rst
+
| LATRNQ_X1 is a positive D-latch with active low reset and 1X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image419|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.rst b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.rst
index e3e76f5..b608aee 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latrnq_2 symbol**
-.. image:: sc9_sym/LATRNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__latrnq_2 schematic**
-.. image:: sc9_sch/LATRNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__latrnq_2 layout**
-.. image:: sc9_lay/LATRNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_2 layout
-.. include:: images.rst
+
| LATRNQ_X2 is a positive D-latch with active low reset and 2X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image422|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.rst b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.rst
index b07824b..2080877 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latrnq_4 symbol**
-.. image:: sc9_sym/LATRNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__latrnq_4 schematic**
-.. image:: sc9_sch/LATRNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__latrnq_4 layout**
-.. image:: sc9_lay/LATRNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrnq_4 layout
-.. include:: images.rst
+
| LATRNQ_X4 is a positive D-latch with active low reset and 4X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image425|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.rst
index ce4a002..f285302 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_1 symbol**
-.. image:: sc9_sym/LATRSNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_1 schematic**
-.. image:: sc9_sch/LATRSNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_1 layout**
-.. image:: sc9_lay/LATRSNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_1 layout
-.. include:: images.rst
+
| LATRSNQ_X1 is a positive D-latch with active low set/reset and 1X drive strength
|
@@ -54,7 +45,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image428|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.rst
index a51f1f6..b2a83ed 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_2 symbol**
-.. image:: sc9_sym/LATRSNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_2 schematic**
-.. image:: sc9_sch/LATRSNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_2 layout**
-.. image:: sc9_lay/LATRSNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_2 layout
-.. include:: images.rst
+
| LATRSNQ_X2 is a positive D-latch with active low set/reset and 2X drive strength
|
@@ -54,7 +45,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image431|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.rst
index d481350..a5c24bd 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_4 symbol**
-.. image:: sc9_sym/LATRSNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_4 schematic**
-.. image:: sc9_sch/LATRSNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__latrsnq_4 layout**
-.. image:: sc9_lay/LATRSNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latrsnq_4 layout
-.. include:: images.rst
+
| LATRSNQ_X4 is a positive D-latch with active low set/reset and 4X drive strength
|
@@ -54,7 +45,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image434|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.rst b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.rst
index 6bd4be8..78c632d 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latsnq_1 symbol**
-.. image:: sc9_sym/LATSNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__latsnq_1 schematic**
-.. image:: sc9_sch/LATSNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__latsnq_1 layout**
-.. image:: sc9_lay/LATSNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_1 layout
-.. include:: images.rst
+
| LATSNQ_X1 is a positive D-latch with active low set and 1X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image437|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.rst b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.rst
index 84c97a6..01f4002 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latsnq_2 symbol**
-.. image:: sc9_sym/LATSNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__latsnq_2 schematic**
-.. image:: sc9_sch/LATSNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__latsnq_2 layout**
-.. image:: sc9_lay/LATSNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_2 layout
-.. include:: images.rst
+
| LATSNQ_X2 is a positive D-latch with active low set and 2X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image440|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.rst b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.rst
index b7b17d3..430b510 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__latsnq_4 symbol**
-.. image:: sc9_sym/LATSNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__latsnq_4 schematic**
-.. image:: sc9_sch/LATSNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__latsnq_4 layout**
-.. image:: sc9_lay/LATSNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__latsnq_4 layout
-.. include:: images.rst
+
| LATSNQ_X4 is a positive D-latch with active low set and 4X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image443|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__latsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.rst b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.rst
index bb30a25..4c54737 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__mux2_1 symbol**
-.. image:: sc9_sym/MUX2_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__mux2_1 schematic**
-.. image:: sc9_sch/MUX2_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__mux2_1 layout**
-.. image:: sc9_lay/MUX2_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_1 layout
-.. include:: images.rst
+
| MUX2_X1 is a 2-to-1 multiplexer with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image446|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.rst b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.rst
index 958c4a4..e286f92 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__mux2_2 symbol**
-.. image:: sc9_sym/MUX2_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__mux2_2 schematic**
-.. image:: sc9_sch/MUX2_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__mux2_2 layout**
-.. image:: sc9_lay/MUX2_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_2 layout
-.. include:: images.rst
+
| MUX2_X2 is a 2-to-1 multiplexer with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image449|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.rst b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.rst
index d3bf30e..5bdaa89 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__mux2_4 symbol**
-.. image:: sc9_sym/MUX2_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__mux2_4 schematic**
-.. image:: sc9_sch/MUX2_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__mux2_4 layout**
-.. image:: sc9_lay/MUX2_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux2_4 layout
-.. include:: images.rst
+
| MUX2_X4 is a 2-to-1 multiplexer with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image452|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux2_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.rst b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.rst
index 72a3c05..fbba4db 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__mux4_1 symbol**
-.. image:: sc9_sym/MUX4_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__mux4_1 schematic**
-.. image:: sc9_sch/MUX4_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__mux4_1 layout**
-.. image:: sc9_lay/MUX4_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_1 layout
-.. include:: images.rst
+
| MUX4_X1 is a 4-to-1 multiplexer with 1X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image455|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.rst b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.rst
index 54f78aa..5645343 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__mux4_2 symbol**
-.. image:: sc9_sym/MUX4_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__mux4_2 schematic**
-.. image:: sc9_sch/MUX4_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__mux4_2 layout**
-.. image:: sc9_lay/MUX4_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_2 layout
-.. include:: images.rst
+
| MUX4_X2 is a 4-to-1 multiplexer with 2X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image458|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.rst b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.rst
index d0a5831..f09c266 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__mux4_4 symbol**
-.. image:: sc9_sym/MUX4_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__mux4_4 schematic**
-.. image:: sc9_sch/MUX4_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__mux4_4 layout**
-.. image:: sc9_lay/MUX4_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__mux4_4 layout
-.. include:: images.rst
+
| MUX4_X4 is a 4-to-1 multiplexer with 4X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image461|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__mux4_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.rst b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.rst
index 515d4d7..db13a7b 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand2_1 symbol**
-.. image:: sc9_sym/NAND2_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand2_1 schematic**
-.. image:: sc9_sch/NAND2_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand2_1 layout**
-.. image:: sc9_lay/NAND2_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_1 layout
-.. include:: images.rst
+
| NAND2_X1 is a 2-input NAND with 1X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image464|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.rst b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.rst
index cf69174..1ab8f6f 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand2_2 symbol**
-.. image:: sc9_sym/NAND2_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand2_2 schematic**
-.. image:: sc9_sch/NAND2_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand2_2 layout**
-.. image:: sc9_lay/NAND2_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_2 layout
-.. include:: images.rst
+
| NAND2_X2 is a 2-input NAND with 2X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image467|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.rst b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.rst
index 33e6284..2a0ed1d 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand2_4 symbol**
-.. image:: sc9_sym/NAND2_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand2_4 schematic**
-.. image:: sc9_sch/NAND2_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand2_4 layout**
-.. image:: sc9_lay/NAND2_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand2_4 layout
-.. include:: images.rst
+
| NAND2_X4 is a 2-input NAND with 4X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image470|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand2_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.rst b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.rst
index b4102a4..340ca3b 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand3_1 symbol**
-.. image:: sc9_sym/NAND3_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand3_1 schematic**
-.. image:: sc9_sch/NAND3_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand3_1 layout**
-.. image:: sc9_lay/NAND3_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_1 layout
-.. include:: images.rst
+
| NAND3_X1 is a 3-input NAND with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image473|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.rst b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.rst
index 99d432c..34b8ec2 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand3_2 symbol**
-.. image:: sc9_sym/NAND3_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand3_2 schematic**
-.. image:: sc9_sch/NAND3_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand3_2 layout**
-.. image:: sc9_lay/NAND3_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_2 layout
-.. include:: images.rst
+
| NAND3_X2 is a 3-input NAND with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image476|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.rst b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.rst
index 95be649..2362ac9 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand3_4 symbol**
-.. image:: sc9_sym/NAND3_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand3_4 schematic**
-.. image:: sc9_sch/NAND3_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand3_4 layout**
-.. image:: sc9_lay/NAND3_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand3_4 layout
-.. include:: images.rst
+
| NAND3_X4 is a 3-input NAND with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image479|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand3_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.rst b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.rst
index ade6dba..b6a0b8a 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand4_1 symbol**
-.. image:: sc9_sym/NAND4_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand4_1 schematic**
-.. image:: sc9_sch/NAND4_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand4_1 layout**
-.. image:: sc9_lay/NAND4_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_1 layout
-.. include:: images.rst
+
| NAND4_X1 is a 4-input NAND with 1X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image482|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.rst b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.rst
index 73173fd..eadf831 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand4_2 symbol**
-.. image:: sc9_sym/NAND4_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand4_2 schematic**
-.. image:: sc9_sch/NAND4_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand4_2 layout**
-.. image:: sc9_lay/NAND4_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_2 layout
-.. include:: images.rst
+
| NAND4_X2 is a 4-input NAND with 2X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image485|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.rst b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.rst
index 3e1c1ff..c61769b 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nand4_4 symbol**
-.. image:: sc9_sym/NAND4_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__nand4_4 schematic**
-.. image:: sc9_sch/NAND4_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__nand4_4 layout**
-.. image:: sc9_lay/NAND4_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nand4_4 layout
-.. include:: images.rst
+
| NAND4_X4 is a 4-input NAND with 4X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image488|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nand4_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.rst b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.rst
index 9eebca3..b3842b1 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor2_1 symbol**
-.. image:: sc9_sym/NOR2_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor2_1 schematic**
-.. image:: sc9_sch/NOR2_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor2_1 layout**
-.. image:: sc9_lay/NOR2_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_1 layout
-.. include:: images.rst
+
| NOR2_X1 is a 2-input NOR with 1X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image491|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.rst b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.rst
index db84c7f..a0d9b1e 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor2_2 symbol**
-.. image:: sc9_sym/NOR2_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor2_2 schematic**
-.. image:: sc9_sch/NOR2_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor2_2 layout**
-.. image:: sc9_lay/NOR2_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_2 layout
-.. include:: images.rst
+
| NOR2_X2 is a 2-input NOR with 2X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image494|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.rst b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.rst
index 9349f11..af65d81 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor2_4 symbol**
-.. image:: sc9_sym/NOR2_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor2_4 schematic**
-.. image:: sc9_sch/NOR2_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor2_4 layout**
-.. image:: sc9_lay/NOR2_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor2_4 layout
-.. include:: images.rst
+
| NOR2_X4 is a 2-input NOR with 4X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image497|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor2_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.rst b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.rst
index f9c5c25..b9abc43 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor3_1 symbol**
-.. image:: sc9_sym/NOR3_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor3_1 schematic**
-.. image:: sc9_sch/NOR3_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor3_1 layout**
-.. image:: sc9_lay/NOR3_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_1 layout
-.. include:: images.rst
+
| NOR3_X1 is a 3-input NOR with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image500|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.rst b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.rst
index 31070e5..fe9fdb3 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor3_2 symbol**
-.. image:: sc9_sym/NOR3_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor3_2 schematic**
-.. image:: sc9_sch/NOR3_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor3_2 layout**
-.. image:: sc9_lay/NOR3_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_2 layout
-.. include:: images.rst
+
| NOR3_X2 is a 3-input NOR with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image503|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.rst b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.rst
index aafea3f..f8db624 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor3_4 symbol**
-.. image:: sc9_sym/NOR3_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor3_4 schematic**
-.. image:: sc9_sch/NOR3_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor3_4 layout**
-.. image:: sc9_lay/NOR3_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor3_4 layout
-.. include:: images.rst
+
| NOR3_X4 is a 3-input NOR with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image506|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor3_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.rst b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.rst
index b33362b..17c0f87 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor4_1 symbol**
-.. image:: sc9_sym/NOR4_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor4_1 schematic**
-.. image:: sc9_sch/NOR4_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor4_1 layout**
-.. image:: sc9_lay/NOR4_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_1 layout
-.. include:: images.rst
+
| NOR4_X1 is a 4-input NOR with 1X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image509|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.rst b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.rst
index a70ced8..ad103ff 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor4_2 symbol**
-.. image:: sc9_sym/NOR4_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor4_2 schematic**
-.. image:: sc9_sch/NOR4_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor4_2 layout**
-.. image:: sc9_lay/NOR4_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_2 layout
-.. include:: images.rst
+
| NOR4_X2 is a 4-input NOR with 2X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image512|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.rst b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.rst
index 91a9a74..ce89f3b 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__nor4_4 symbol**
-.. image:: sc9_sym/NOR4_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__nor4_4 schematic**
-.. image:: sc9_sch/NOR4_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__nor4_4 layout**
-.. image:: sc9_lay/NOR4_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__nor4_4 layout
-.. include:: images.rst
+
| NOR4_X4 is a 4-input NOR with 4X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image515|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__nor4_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.rst b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.rst
index 8567fd6..23fecd9 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai21_1 symbol**
-.. image:: sc9_sym/OAI21_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai21_1 schematic**
-.. image:: sc9_sch/OAI21_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai21_1 layout**
-.. image:: sc9_lay/OAI21_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_1 layout
-.. include:: images.rst
+
| OAI21_X1 is a 2-input OR into 2-input NAND with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image527|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.rst b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.rst
index 325fb00..b93ed8c 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai21_2 symbol**
-.. image:: sc9_sym/OAI21_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai21_2 schematic**
-.. image:: sc9_sch/OAI21_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai21_2 layout**
-.. image:: sc9_lay/OAI21_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_2 layout
-.. include:: images.rst
+
| OAI21_X2 is a 2-input OR into 2-input NAND with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image530|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.rst b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.rst
index 6d20b4f..fc2b64a 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai21_4 symbol**
-.. image:: sc9_sym/OAI21_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai21_4 schematic**
-.. image:: sc9_sch/OAI21_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai21_4 layout**
-.. image:: sc9_lay/OAI21_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai21_4 layout
-.. include:: images.rst
+
| OAI21_X4 is a 2-input OR into 2-input NAND with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image533|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai21_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.rst b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.rst
index dadb6d8..8b591e4 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai211_1 symbol**
-.. image:: sc9_sym/OAI211_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai211_1 schematic**
-.. image:: sc9_sch/OAI211_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai211_1 layout**
-.. image:: sc9_lay/OAI211_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_1 layout
-.. include:: images.rst
+
| OAI211_X1 is a 2-input OR into 3-input NAND with 1X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image518|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.rst b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.rst
index 39cbee4..c44d101 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai211_2 symbol**
-.. image:: sc9_sym/OAI211_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai211_2 schematic**
-.. image:: sc9_sch/OAI211_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai211_2 layout**
-.. image:: sc9_lay/OAI211_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_2 layout
-.. include:: images.rst
+
| OAI211_X2 is a 2-input OR into 3-input NAND with 2X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image521|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.rst b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.rst
index 378fa10..4036a3f 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai211_4 symbol**
-.. image:: sc9_sym/OAI211_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai211_4 schematic**
-.. image:: sc9_sch/OAI211_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai211_4 layout**
-.. image:: sc9_lay/OAI211_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai211_4 layout
-.. include:: images.rst
+
| OAI211_X4 is a 2-input OR into 3-input NAND with 4X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image524|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai211_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.rst b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.rst
index 74ae63f..f1539d7 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai22_1 symbol**
-.. image:: sc9_sym/OAI22_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai22_1 schematic**
-.. image:: sc9_sch/OAI22_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai22_1 layout**
-.. image:: sc9_lay/OAI22_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_1 layout
-.. include:: images.rst
+
| OAI22_X1 is a two 2-input OR into 2-input NAND with 1X drive strength
|
@@ -61,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image554|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.rst b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.rst
index 9ffdd6f..f0a3f91 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai22_2 symbol**
-.. image:: sc9_sym/OAI22_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai22_2 schematic**
-.. image:: sc9_sch/OAI22_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai22_2 layout**
-.. image:: sc9_lay/OAI22_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_2 layout
-.. include:: images.rst
+
| OAI22_X2 is a two 2-input OR into 2-input NAND with 2X drive strength
|
@@ -61,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image557|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.rst b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.rst
index 60248ef..274008b 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai22_4 symbol**
-.. image:: sc9_sym/OAI22_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai22_4 schematic**
-.. image:: sc9_sch/OAI22_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai22_4 layout**
-.. image:: sc9_lay/OAI22_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai22_4 layout
-.. include:: images.rst
+
| OAI22_X4 is a two 2-input OR into 2-input NAND with 4X drive strength
|
@@ -61,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image560|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai22_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.rst b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.rst
index 2ab374e..7420dbc 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai221_1 symbol**
-.. image:: sc9_sym/OAI221_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai221_1 schematic**
-.. image:: sc9_sch/OAI221_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai221_1 layout**
-.. image:: sc9_lay/OAI221_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_1 layout
-.. include:: images.rst
+
| OAI221_X1 is a two 2-input OR into 3-input NAND with 1X drive strength
|
@@ -62,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image536|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.rst b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.rst
index e658d56..e95aa6f 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai221_2 symbol**
-.. image:: sc9_sym/OAI221_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai221_2 schematic**
-.. image:: sc9_sch/OAI221_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai221_2 layout**
-.. image:: sc9_lay/OAI221_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_2 layout
-.. include:: images.rst
+
| OAI221_X2 is a two 2-input OR into 3-input NAND with 2X drive strength
|
@@ -62,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image539|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.rst b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.rst
index 131fd97..84a7381 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai221_4 symbol**
-.. image:: sc9_sym/OAI221_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai221_4 schematic**
-.. image:: sc9_sch/OAI221_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai221_4 layout**
-.. image:: sc9_lay/OAI221_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai221_4 layout
-.. include:: images.rst
+
| OAI221_X4 is a two 2-input OR into 3-input NAND with 4X drive strength
|
@@ -62,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image542|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai221_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.rst b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.rst
index e2f06bd..fad296a 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai222_1 symbol**
-.. image:: sc9_sym/OAI222_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai222_1 schematic**
-.. image:: sc9_sch/OAI222_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai222_1 layout**
-.. image:: sc9_lay/OAI222_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_1 layout
-.. include:: images.rst
+
| OAI222_X1 is a three 2-input OR into 3-input NAND with 1X drive strength
|
@@ -66,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image545|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.rst b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.rst
index 48eb21a..632a607 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai222_2 symbol**
-.. image:: sc9_sym/OAI222_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai222_2 schematic**
-.. image:: sc9_sch/OAI222_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai222_2 layout**
-.. image:: sc9_lay/OAI222_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_2 layout
-.. include:: images.rst
+
| OAI222_X2 is a three 2-input OR into 3-input NAND with 2X drive strength
|
@@ -66,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image548|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.rst b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.rst
index 079042a..af9fe19 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai222_4 symbol**
-.. image:: sc9_sym/OAI222_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai222_4 schematic**
-.. image:: sc9_sch/OAI222_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai222_4 layout**
-.. image:: sc9_lay/OAI222_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai222_4 layout
-.. include:: images.rst
+
| OAI222_X4 is a three 2-input OR into 3-input NAND with 4X drive strength
|
@@ -66,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image551|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai222_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.rst b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.rst
index 0cf7784..d3f631f 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai31_1 symbol**
-.. image:: sc9_sym/OAI31_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai31_1 schematic**
-.. image:: sc9_sch/OAI31_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai31_1 layout**
-.. image:: sc9_lay/OAI31_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_1 layout
-.. include:: images.rst
+
| OAI31_X1 is a 3-input OR into 2-input NAND with 1X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image563|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.rst b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.rst
index b05d139..c248ba7 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai31_2 symbol**
-.. image:: sc9_sym/OAI31_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai31_2 schematic**
-.. image:: sc9_sch/OAI31_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai31_2 layout**
-.. image:: sc9_lay/OAI31_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_2 layout
-.. include:: images.rst
+
| OAI31_X2 is a 3-input OR into 2-input NAND with 2X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image566|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.rst b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.rst
index 3bfb842..a9763ef 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai31_4 symbol**
-.. image:: sc9_sym/OAI31_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai31_4 schematic**
-.. image:: sc9_sch/OAI31_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai31_4 layout**
-.. image:: sc9_lay/OAI31_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai31_4 layout
-.. include:: images.rst
+
| OAI31_X4 is a 3-input OR into 2-input NAND with 4X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image569|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai31_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.rst b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.rst
index 4ced666..25e069e 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai32_1 symbol**
-.. image:: sc9_sym/OAI32_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai32_1 schematic**
-.. image:: sc9_sch/OAI32_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai32_1 layout**
-.. image:: sc9_lay/OAI32_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_1 layout
-.. include:: images.rst
+
| OAI32_X1 is a two 3-input OR, 2-input OR into 2-input NAND with 1X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image572|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.rst b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.rst
index 96ab4a7..2942d38 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai32_2 symbol**
-.. image:: sc9_sym/OAI32_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai32_2 schematic**
-.. image:: sc9_sch/OAI32_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai32_2 layout**
-.. image:: sc9_lay/OAI32_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_2 layout
-.. include:: images.rst
+
| OAI32_X2 is a two 3-input OR, 2-input OR into 2-input NAND with 2X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image575|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.rst b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.rst
index 80f3265..151de58 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai32_4 symbol**
-.. image:: sc9_sym/OAI32_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai32_4 schematic**
-.. image:: sc9_sch/OAI32_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai32_4 layout**
-.. image:: sc9_lay/OAI32_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai32_4 layout
-.. include:: images.rst
+
| OAI32_X4 is a two 3-input OR, 2-input OR into 2-input NAND with 4X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image578|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai32_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.rst b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.rst
index 3ad7933..e04c0d5 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai33_1 symbol**
-.. image:: sc9_sym/OAI33_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai33_1 schematic**
-.. image:: sc9_sch/OAI33_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai33_1 layout**
-.. image:: sc9_lay/OAI33_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_1 layout
-.. include:: images.rst
+
| OAI33_X1 is a three 2-input OR into 2-input NAND with 1X drive strength
|
@@ -66,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image581|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.rst b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.rst
index 3e02c11..8870c1e 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai33_2 symbol**
-.. image:: sc9_sym/OAI33_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai33_2 schematic**
-.. image:: sc9_sch/OAI33_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai33_2 layout**
-.. image:: sc9_lay/OAI33_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_2 layout
-.. include:: images.rst
+
| OAI33_X2 is a three 2-input OR into 2-input NAND with 2X drive strength
|
@@ -66,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image584|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.rst b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.rst
index 94ba2d1..8a92628 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__oai33_4 symbol**
-.. image:: sc9_sym/OAI33_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__oai33_4 schematic**
-.. image:: sc9_sch/OAI33_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__oai33_4 layout**
-.. image:: sc9_lay/OAI33_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__oai33_4 layout
-.. include:: images.rst
+
| OAI33_X4 is a three 2-input OR into 2-input NAND with 4X drive strength
|
@@ -66,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image587|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__oai33_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.rst b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.rst
index 0fe1e48..c1a0d6a 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or2_1 symbol**
-.. image:: sc9_sym/OR2_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__or2_1 schematic**
-.. image:: sc9_sch/OR2_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__or2_1 layout**
-.. image:: sc9_lay/OR2_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_1 layout
-.. include:: images.rst
+
| OR2_X1 is a 2-input OR with 1X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image590|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.rst b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.rst
index e85bdb1..32a6b19 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or2_2 symbol**
-.. image:: sc9_sym/OR2_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__or2_2 schematic**
-.. image:: sc9_sch/OR2_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__or2_2 layout**
-.. image:: sc9_lay/OR2_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_2 layout
-.. include:: images.rst
+
| OR2_X2 is a 2-input OR with 2X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image593|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_4.rst b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_4.rst
index 3416101..6a3dcab 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_4.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or2_4 symbol**
-.. image:: sc9_sym/OR2_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__or2_4 schematic**
-.. image:: sc9_sch/OR2_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__or2_4 layout**
-.. image:: sc9_lay/OR2_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or2_4 layout
-.. include:: images.rst
+
| OR2_X4 is a 2-input OR with 4X drive strength
|
@@ -58,7 +49,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image596|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or2_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.rst b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.rst
index cfd5d8a..e111f3f 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or3_1 symbol**
-.. image:: sc9_sym/OR3_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__or3_1 schematic**
-.. image:: sc9_sch/OR3_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__or3_1 layout**
-.. image:: sc9_lay/OR3_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_1 layout
-.. include:: images.rst
+
| OR3_X1 is a 3-input OR with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image599|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.rst b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.rst
index 8a19d64..660c05e 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or3_2 symbol**
-.. image:: sc9_sym/OR3_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__or3_2 schematic**
-.. image:: sc9_sch/OR3_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__or3_2 layout**
-.. image:: sc9_lay/OR3_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_2 layout
-.. include:: images.rst
+
| OR3_X2 is a 3-input OR with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image602|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_4.rst b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_4.rst
index 63db406..8fef925 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_4.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or3_4 symbol**
-.. image:: sc9_sym/OR3_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__or3_4 schematic**
-.. image:: sc9_sch/OR3_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__or3_4 layout**
-.. image:: sc9_lay/OR3_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or3_4 layout
-.. include:: images.rst
+
| OR3_X4 is a 3-input OR with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image605|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or3_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.rst b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.rst
index 5d18f17..5149cfe 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or4_1 symbol**
-.. image:: sc9_sym/OR4_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__or4_1 schematic**
-.. image:: sc9_sch/OR4_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__or4_1 layout**
-.. image:: sc9_lay/OR4_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_1 layout
-.. include:: images.rst
+
| OR4_X1 is a 4-input OR with 1X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image608|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.rst b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.rst
index 57a9337..9792b2b 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or4_2 symbol**
-.. image:: sc9_sym/OR4_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__or4_2 schematic**
-.. image:: sc9_sch/OR4_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__or4_2 layout**
-.. image:: sc9_lay/OR4_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_2 layout
-.. include:: images.rst
+
| OR4_X2 is a 4-input OR with 2X drive strength
|
@@ -60,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image611|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.rst b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.rst
index 70c00d2..5b6c6cb 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.rst
@@ -4,27 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__or4_4 symbol**
-.. image:: sc9_sym/OR4_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__or4_4 schematic**
-.. image:: sc9_sch/OR4_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__or4_4 layout**
-.. image:: sc9_lay/OR4_X4_lay.png
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__or4_4 layout
-.. include:: images.rst
+
| OR4_X4 is a 4-input OR with 4X drive strength
|
@@ -58,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image614|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__or4_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.rst b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.rst
index d5cb0a9..94e4d33 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffq_1 symbol**
-.. image:: sc9_sym/SDFFQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffq_1 schematic**
-.. image:: sc9_sch/SDFFQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffq_1 layout**
-.. image:: sc9_lay/SDFFQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_1 layout
-.. include:: images.rst
+
| SDFFQ_X1 is a positive edge triggered scan D-type flip flop with 1X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image617|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.rst b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.rst
index 12cc0a8..ebc1d51 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffq_2 symbol**
-.. image:: sc9_sym/SDFFQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffq_2 schematic**
-.. image:: sc9_sch/SDFFQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffq_2 layout**
-.. image:: sc9_lay/SDFFQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_2 layout
-.. include:: images.rst
+
| SDFFQ_X2 is a positive edge triggered scan D-type flip flop with 2X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image620|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.rst b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.rst
index 497c075..a9f642a 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffq_4 symbol**
-.. image:: sc9_sym/SDFFQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffq_4 schematic**
-.. image:: sc9_sch/SDFFQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffq_4 layout**
-.. image:: sc9_lay/SDFFQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffq_4 layout
-.. include:: images.rst
+
| SDFFQ_X4 is a positive edge triggered scan D-type flip flop with 4X drive strength
|
@@ -52,7 +43,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image623|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.rst
index 7de0e63..252ae16 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1 symbol**
-.. image:: sc9_sym/SDFFRNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1 schematic**
-.. image:: sc9_sch/SDFFRNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1 layout**
-.. image:: sc9_lay/SDFFRNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1 layout
-.. include:: images.rst
+
| SDFFRNQ_X1 is a positive edge triggered scan D-type flip flop with active low reset and 1X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image626|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.rst
index 9d01974..d4ab7db 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2 symbol**
-.. image:: sc9_sym/SDFFRNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2 schematic**
-.. image:: sc9_sch/SDFFRNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2 layout**
-.. image:: sc9_lay/SDFFRNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2 layout
-.. include:: images.rst
+
| SDFFRNQ_X2 is a positive edge triggered scan D-type flip flop with active low reset and 2X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image629|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.rst
index 1a16c3e..3470e58 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4 symbol**
-.. image:: sc9_sym/SDFFRNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4 schematic**
-.. image:: sc9_sch/SDFFRNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4 layout**
-.. image:: sc9_lay/SDFFRNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4 layout
-.. include:: images.rst
+
| SDFFRNQ_X4 is a positive edge triggered scan D-type flip flop with active low reset and 4X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image632|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.rst
index ec30b0d..ded8867 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1 symbol**
-.. image:: sc9_sym/SDFFRSNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1 schematic**
-.. image:: sc9_sch/SDFFRSNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1 layout**
-.. image:: sc9_lay/SDFFRSNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1 layout
-.. include:: images.rst
+
| SDFFRSNQ_X1 is a positive edge triggered scan D-type flip flop with active low reset and 1X drive strength
|
@@ -55,7 +46,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image635|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.rst
index 4b0fcb0..bc385b4 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2 symbol**
-.. image:: sc9_sym/SDFFRSNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2 schematic**
-.. image:: sc9_sch/SDFFRSNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2 layout**
-.. image:: sc9_lay/SDFFRSNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2 layout
-.. include:: images.rst
+
| SDFFRSNQ_X2 is a positive edge triggered scan D-type flip flop with active low reset and 2X drive strength
|
@@ -55,7 +46,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image638|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.rst
index 218e80a..b11a8e2 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4 symbol**
-.. image:: sc9_sym/SDFFRSNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4 schematic**
-.. image:: sc9_sch/SDFFRSNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4 layout**
-.. image:: sc9_lay/SDFFRSNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4 layout
-.. include:: images.rst
+
| SDFFRSNQ_X4 is a positive edge triggered scan D-type flip flop with active low reset and 4X drive strength
|
@@ -55,7 +46,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image641|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.rst
index ea1452a..d92a2a1 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1 symbol**
-.. image:: sc9_sym/SDFFSNQ_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1 schematic**
-.. image:: sc9_sch/SDFFSNQ_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1 layout**
-.. image:: sc9_lay/SDFFSNQ_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1 layout
-.. include:: images.rst
+
| SDFFSNQ_X1 is a positive edge triggered scan D-type flip flop with active low set and 1X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image644|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.rst
index 0dafaa7..a96bdd3 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2 symbol**
-.. image:: sc9_sym/SDFFSNQ_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2 schematic**
-.. image:: sc9_sch/SDFFSNQ_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2 layout**
-.. image:: sc9_lay/SDFFSNQ_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2 layout
-.. include:: images.rst
+
| SDFFSNQ_X2 is a positive edge triggered scan D-type flip flop with active low set and 2X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image647|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.rst
index d750adc..5554ba6 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4 symbol**
-.. image:: sc9_sym/SDFFSNQ_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4 schematic**
-.. image:: sc9_sch/SDFFSNQ_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4 layout**
-.. image:: sc9_lay/SDFFSNQ_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4 layout
-.. include:: images.rst
+
| SDFFSNQ_X4 is a positive edge triggered scan D-type flip flop with active low set and 4X drive strength
|
@@ -53,7 +44,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image650|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.rst b/cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.rst
index 2443cab..bbbebb3 100644
--- a/cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.rst
+++ b/cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__tieh symbol**
-.. image:: sc9_sym/TIEH_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__tieh.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__tieh symbol
**gf180mcu_fd_sc_mcu9t5v0__tieh schematic**
-.. image:: sc9_sch/TIEH_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__tieh.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__tieh schematic
**gf180mcu_fd_sc_mcu9t5v0__tieh layout**
-.. image:: sc9_lay/TIEH_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__tieh.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__tieh layout
-.. include:: images.rst
+
| TIEH is a high Level generator
|
@@ -54,7 +45,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image653|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__tieh.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.rst b/cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.rst
index 2ab3cbb..6eb0400 100644
--- a/cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.rst
+++ b/cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__tiel symbol**
-.. image:: sc9_sym/TIEL_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__tiel.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__tiel symbol
**gf180mcu_fd_sc_mcu9t5v0__tiel schematic**
-.. image:: sc9_sch/TIEL_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__tiel.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__tiel schematic
**gf180mcu_fd_sc_mcu9t5v0__tiel layout**
-.. image:: sc9_lay/TIEL_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__tiel.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__tiel layout
-.. include:: images.rst
+
| TIEL is a low Level generator
|
@@ -54,7 +45,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image656|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__tiel.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.rst b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.rst
index da8876c..2511c04 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xnor2_1 symbol**
-.. image:: sc9_sym/XNOR2_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__xnor2_1 schematic**
-.. image:: sc9_sch/XNOR2_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__xnor2_1 layout**
-.. image:: sc9_lay/XNOR2_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_1 layout
-.. include:: images.rst
+
| XNOR2_X1 is a 2-input exclusive NOR with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image659|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.rst b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.rst
index bcc4b7a..25ce541 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xnor2_2 symbol**
-.. image:: sc9_sym/XNOR2_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__xnor2_2 schematic**
-.. image:: sc9_sch/XNOR2_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__xnor2_2 layout**
-.. image:: sc9_lay/XNOR2_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_2 layout
-.. include:: images.rst
+
| XNOR2_X2 is a 2-input exclusive NOR with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image662|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.rst b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.rst
index d6837ed..9c40c9c 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xnor2_4 symbol**
-.. image:: sc9_sym/XNOR2_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__xnor2_4 schematic**
-.. image:: sc9_sch/XNOR2_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__xnor2_4 layout**
-.. image:: sc9_lay/XNOR2_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor2_4 layout
-.. include:: images.rst
+
| XNOR2_X4 is a 2-input exclusive NOR with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image665|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor2_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.rst b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.rst
index 10cee3b..2e7cb98 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xnor3_1 symbol**
-.. image:: sc9_sym/XNOR3_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__xnor3_1 schematic**
-.. image:: sc9_sch/XNOR3_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__xnor3_1 layout**
-.. image:: sc9_lay/XNOR3_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_1 layout
-.. include:: images.rst
+
| XNOR3_X1 is a 3-input exclusive NOR with 1X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image668|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.rst b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.rst
index e68c8eb..221737e 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xnor3_2 symbol**
-.. image:: sc9_sym/XNOR3_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__xnor3_2 schematic**
-.. image:: sc9_sch/XNOR3_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__xnor3_2 layout**
-.. image:: sc9_lay/XNOR3_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_2 layout
-.. include:: images.rst
+
| XNOR3_X2 is a 3-input exclusive NOR with 2X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image671|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.rst b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.rst
index 82309d3..50e3fb2 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xnor3_4 symbol**
-.. image:: sc9_sym/XNOR3_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__xnor3_4 schematic**
-.. image:: sc9_sch/XNOR3_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__xnor3_4 layout**
-.. image:: sc9_lay/XNOR3_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xnor3_4 layout
-.. include:: images.rst
+
| XNOR3_X4 is a 3-input exclusive NOR with 4X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image674|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xnor3_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.rst b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.rst
index 590b65d..d57880a 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xor2_1 symbol**
-.. image:: sc9_sym/XOR2_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__xor2_1 schematic**
-.. image:: sc9_sch/XOR2_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__xor2_1 layout**
-.. image:: sc9_lay/XOR2_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_1 layout
-.. include:: images.rst
+
| XOR2_X1 is a 2-input exclusive OR with 1X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image677|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.rst b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.rst
index 96311fc..5859815 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xor2_2 symbol**
-.. image:: sc9_sym/XOR2_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__xor2_2 schematic**
-.. image:: sc9_sch/XOR2_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__xor2_2 layout**
-.. image:: sc9_lay/XOR2_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_2 layout
-.. include:: images.rst
+
| XOR2_X2 is a 2-input exclusive OR with 2X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image680|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.rst b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.rst
index a4eee6f..f2c922a 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xor2_4 symbol**
-.. image:: sc9_sym/XOR2_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__xor2_4 schematic**
-.. image:: sc9_sch/XOR2_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__xor2_4 layout**
-.. image:: sc9_lay/XOR2_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor2_4 layout
-.. include:: images.rst
+
| XOR2_X4 is a 2-input exclusive OR with 4X drive strength
|
@@ -59,7 +50,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image683|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor2_4.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.rst b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.rst
index ad3b4e2..701cbb9 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xor3_1 symbol**
-.. image:: sc9_sym/XOR3_X1_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_1.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_1 symbol
**gf180mcu_fd_sc_mcu9t5v0__xor3_1 schematic**
-.. image:: sc9_sch/XOR3_X1_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_1.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_1 schematic
**gf180mcu_fd_sc_mcu9t5v0__xor3_1 layout**
-.. image:: sc9_lay/XOR3_X1_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_1.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_1 layout
-.. include:: images.rst
+
| XOR3_X1 is a 3-input exclusive OR with 1X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image686|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_1.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.rst b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.rst
index e3c1cec..cdb7b4f 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xor3_2 symbol**
-.. image:: sc9_sym/XOR3_X2_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_2.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_2 symbol
**gf180mcu_fd_sc_mcu9t5v0__xor3_2 schematic**
-.. image:: sc9_sch/XOR3_X2_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_2.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_2 schematic
**gf180mcu_fd_sc_mcu9t5v0__xor3_2 layout**
-.. image:: sc9_lay/XOR3_X2_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_2.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_2 layout
-.. include:: images.rst
+
| XOR3_X2 is a 3-input exclusive OR with 2X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image689|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_2.png
+
| PIN CAPACITANCE (pf)
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.rst b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.rst
index 915de78..b1460c5 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.rst
@@ -4,29 +4,20 @@
**gf180mcu_fd_sc_mcu9t5v0__xor3_4 symbol**
-.. image:: sc9_sym/XOR3_X4_sym.png
- :height: 200px
- :width: 400 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_4.symbol.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_4 symbol
**gf180mcu_fd_sc_mcu9t5v0__xor3_4 schematic**
-.. image:: sc9_sch/XOR3_X4_sch.png
- :height: 250px
- :width: 450 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_4.schematic.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_4 schematic
**gf180mcu_fd_sc_mcu9t5v0__xor3_4 layout**
-.. image:: sc9_lay/XOR3_X4_lay.png
- :height: 300px
- :width: 500 px
- :align: center
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_4.layout.png
:alt: gf180mcu_fd_sc_mcu9t5v0__xor3_4 layout
-.. include:: images.rst
+
| XOR3_X4 is a 3-input exclusive OR with 4X drive strength
|
@@ -63,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image692|
+
+.. image:: gf180mcu_fd_sc_mcu9t5v0__xor3_4.png
+
| PIN CAPACITANCE (pf)
