blob: 3c22cc998bb22e56b1ccf61b65235d61b43c39c7 [file] [log] [blame]
{
"description": "16 buffer delay cell",
"file_prefix": "gf180mcu_fd_sc_mcu9t5v0__dlyd",
"library": "gf180mcu_fd_sc_mcu9t5v0",
"name": "dlyd",
"parameters": [],
"ports": [
[
"signal",
"I",
"input",
""
],
[
"signal",
"Z",
"output",
""
],
[
"power",
"VDD",
"input",
"supply1"
],
[
"power",
"VSS",
"input",
"supply0"
]
],
"type": "cell",
"verilog_name": "gf180mcu_fd_sc_mcu9t5v0__dlyd"
}