blob: 1cdcda987b5613e9ec3548426bc4079442400244 [file] [log] [blame]
{
"description": "positive edge triggered D-type flip flop",
"file_prefix": "gf180mcu_fd_sc_mcu9t5v0__dffq",
"library": "gf180mcu_fd_sc_mcu9t5v0",
"name": "dffq",
"parameters": [],
"ports": [
[
"signal",
"CLK",
"input",
""
],
[
"signal",
"D",
"input",
""
],
[
"signal",
"Q",
"output",
""
],
[
"power",
"VDD",
"input",
"supply1"
],
[
"power",
"VSS",
"input",
"supply0"
]
],
"type": "cell",
"verilog_name": "gf180mcu_fd_sc_mcu9t5v0__dffq"
}