| { | |
| "cell gf180mcu_fd_sc_mcu7t5v0__latrnq_2": { | |
| "area": "52.684800", | |
| "latch IQ2,IQN2": { | |
| "enable": "E", | |
| "data_in": "D", | |
| "clear": "(!RN)" | |
| }, | |
| "leakage_power ": [ | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "!D&!E&!RN", | |
| "value": "0.00027221" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "!D&!E&RN", | |
| "value": "0.000298595" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "!D&E&!RN", | |
| "value": "0.000272785" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "!D&E&RN", | |
| "value": "0.00027354" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "D&!E&!RN", | |
| "value": "0.00027238" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "D&!E&RN", | |
| "value": "0.000336065" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "D&E&!RN", | |
| "value": "0.000313295" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "D&E&RN", | |
| "value": "0.00029363" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "value": "0.000336065" | |
| } | |
| ], | |
| "pg_pin VDD": { | |
| "voltage_name": "VDD", | |
| "pg_type": "primary_power" | |
| }, | |
| "pg_pin VSS": { | |
| "voltage_name": "VSS", | |
| "pg_type": "primary_ground" | |
| }, | |
| "pin D": { | |
| "capacitance": "0.003078", | |
| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "4", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
| "when": "!E&!RN", | |
| "fall_power pwr_tin_10": { | |
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| 0.02, | |
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| 0.1439, | |
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| 0.6149, | |
| 1.017, | |
| 1.547, | |
| 2.214, | |
| 3.029, | |
| 4 | |
| ], | |
| "values": [ | |
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| 0.03193, | |
| 0.03208 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
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| 4 | |
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| -0.01999 | |
| ] | |
| } | |
| }, | |
| { | |
| "when": "!E&RN", | |
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| 2.214, | |
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| 4 | |
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| "values": [ | |
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| 0.02173 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
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| 3.029, | |
| 4 | |
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| -0.01999 | |
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| } | |
| }, | |
| { | |
| "when": "E&!RN", | |
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| 1.017, | |
| 1.547, | |
| 2.214, | |
| 3.029, | |
| 4 | |
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| "values": [ | |
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| 0.0222, | |
| 0.02217, | |
| 0.02217, | |
| 0.02217 | |
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| "rise_power pwr_tin_10": { | |
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| 4 | |
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| "values": [ | |
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| } | |
| } | |
| ], | |
| "timing ": [ | |
| { | |
| "related_pin": "E", | |
| "sdf_cond": "ENABLE_RN === 1'b1", | |
| "timing_type": "hold_falling", | |
| "when": "RN", | |
| "fall_constraint cnst_ctin_rtin_10x10": { | |
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| 2.214, | |
| 3.029, | |
| 4 | |
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| 3.029, | |
| 4 | |
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| [ | |
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| -0.797, | |
| -0.725, | |
| -0.649 | |
| ] | |
| ] | |
| }, | |
| "rise_constraint cnst_ctin_rtin_10x10": { | |
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| 0.02, | |
| 0.04747, | |
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| 0.328, | |
| 0.6149, | |
| 1.017, | |
| 1.547, | |
| 2.214, | |
| 3.029, | |
| 4 | |
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| 3.029, | |
| 4 | |
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| [ | |
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| [ | |
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| -0.811, | |
| -0.901 | |
| ] | |
| ] | |
| } | |
| }, | |
| { | |
| "related_pin": "E", | |
| "sdf_cond": "ENABLE_RN === 1'b1", | |
| "timing_type": "setup_falling", | |
| "when": "RN", | |
| "fall_constraint cnst_ctin_rtin_10x10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.04747, | |
| 0.1439, | |
| 0.328, | |
| 0.6149, | |
| 1.017, | |
| 1.547, | |
| 2.214, | |
| 3.029, | |
| 4 | |
| ], | |
| "index_2": [ | |
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| 0.328, | |
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| 1.017, | |
| 1.547, | |
| 2.214, | |
| 3.029, | |
| 4 | |
| ], | |
| "values": [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| 0.834, | |
| 0.759, | |
| 0.687 | |
| ] | |
| ] | |
| }, | |
| "rise_constraint cnst_ctin_rtin_10x10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.04747, | |
| 0.1439, | |
| 0.328, | |
| 0.6149, | |
| 1.017, | |
| 1.547, | |
| 2.214, | |
| 3.029, | |
| 4 | |
| ], | |
| "index_2": [ | |
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| 0.04747, | |
| 0.1439, | |
| 0.328, | |
| 0.6149, | |
| 1.017, | |
| 1.547, | |
| 2.214, | |
| 3.029, | |
| 4 | |
| ], | |
| "values": [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| ] | |
| } | |
| } | |
| ] | |
| }, | |
| "pin E": { | |
| "capacitance": "0.007361", | |
| "clock": "true", | |
| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "4", | |
| "min_pulse_width_high": "0.495", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
| "when": "!D&!RN", | |
| "fall_power pwr_tin_10": { | |
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