| { | |
| "cell gf180mcu_fd_sc_mcu7t5v0__latrsnq_1": { | |
| "area": "52.684800", | |
| "latch IQ2,IQN2": { | |
| "enable": "E", | |
| "data_in": "D", | |
| "clear": "(!RN)", | |
| "preset": "(!SETN)", | |
| "clear_preset_var1": "H", | |
| "clear_preset_var2": "L" | |
| }, | |
| "leakage_power ": [ | |
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| { | |
| "related_pg_pin": "VDD", | |
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| "value": "2.616786e-05" | |
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| { | |
| "related_pg_pin": "VDD", | |
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| "value": "3.662658e-05" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
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| { | |
| "related_pg_pin": "VDD", | |
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| { | |
| "related_pg_pin": "VDD", | |
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| { | |
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| { | |
| "related_pg_pin": "VDD", | |
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| { | |
| "related_pg_pin": "VDD", | |
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| { | |
| "related_pg_pin": "VDD", | |
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| { | |
| "related_pg_pin": "VDD", | |
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| "value": "4.517856e-05" | |
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| { | |
| "related_pg_pin": "VDD", | |
| "when": "D&E&!RN&!SETN", | |
| "value": "2.698272e-05" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "D&E&!RN&SETN", | |
| "value": "2.981286e-05" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "D&E&RN&!SETN", | |
| "value": "2.627154e-05" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "D&E&RN&SETN", | |
| "value": "2.912436e-05" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "value": "4.517856e-05" | |
| } | |
| ], | |
| "pg_pin VDD": { | |
| "voltage_name": "VDD", | |
| "pg_type": "primary_power" | |
| }, | |
| "pg_pin VSS": { | |
| "voltage_name": "VSS", | |
| "pg_type": "primary_ground" | |
| }, | |
| "pin D": { | |
| "capacitance": "0.002634", | |
| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "21", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
| "when": "!E&!RN&!SETN", | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| "rise_power pwr_tin_10": { | |
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| } | |
| ], | |
| "timing ": [ | |
| { | |
| "related_pin": "E", | |
| "sdf_cond": "ENABLE_RN_AND_SETN === 1'b1", | |
| "timing_type": "hold_falling", | |
| "when": "RN&SETN", | |
| "fall_constraint cnst_ctin_rtin_10x10": { | |
| "index_1": [ | |
| 0.02, | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| ] | |
| }, | |
| "rise_constraint cnst_ctin_rtin_10x10": { | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| ] | |
| } | |
| }, | |
| { | |
| "related_pin": "E", | |
| "sdf_cond": "ENABLE_RN_AND_SETN === 1'b1", | |
| "timing_type": "setup_falling", | |
| "when": "RN&SETN", | |
| "fall_constraint cnst_ctin_rtin_10x10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.1648, | |
| 0.6731, | |
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| } | |
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| "timing ": [ | |
| { | |
| "related_pin": "E", | |
| "sdf_cond": "ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1", | |
| "timing_type": "min_pulse_width", | |
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| "rise_constraint scalar": { | |
| "values": [ | |
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| { | |
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| } | |
| ] | |
| }, | |
| "pin Q": { | |
| "direction": "output", | |
| "function": "IQ2", | |
| "max_capacitance": "0.1649", | |
| "max_transition": "21", | |
| "min_capacitance": "0.001", | |
| "output_voltage": "default", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
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| "related_pin": "D", | |
| "when": "E&RN&SETN", | |
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