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| 0.05959 | |
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| }, | |
| "rise_power pwr_tin_10": { | |
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| 0.4054, | |
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| 1.268, | |
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| }, | |
| { | |
| "when": "A1&B&C", | |
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| }, | |
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| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "5", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
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| { | |
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| "rise_power pwr_tin_10": { | |
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| { | |
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| "rise_power pwr_tin_10": { | |
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| { | |
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| "rise_power pwr_tin_10": { | |
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| }, | |
| { | |
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| "rise_power pwr_tin_10": { | |
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| 5 | |
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| } | |
| } | |
| ] | |
| }, | |
| "pin C": { | |
| "capacitance": "0.007526", | |
| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "5", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
| "when": "!A1&!A2&B", | |
| "fall_power pwr_tin_10": { | |
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| 0.02, | |
| 0.05437, | |
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| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
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| 0.05813, | |
| 0.05813, | |
| 0.05805 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
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| 5 | |
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| } | |
| }, | |
| { | |
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| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
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| 0.05813, | |
| 0.05811, | |
| 0.05806 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
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| 1.268, | |
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| 2.766, | |
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| 5 | |
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| "values": [ | |
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| } | |
| }, | |
| { | |
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| "fall_power pwr_tin_10": { | |
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| 0.02, | |
| 0.05437, | |
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| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
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| 5 | |
| ], | |
| "values": [ | |
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| 0.05813, | |
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| 0.05814 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
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| 0.02, | |
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| 0.175, | |
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| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
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| } | |
| }, | |
| { | |
| "when": "A1&A2&!B", | |
| "fall_power pwr_tin_10": { | |
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| 0.02, | |
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| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
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| 0.0578, | |
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| 0.05784 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
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| 1.268, | |
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| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
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| -0.056 | |
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| } | |
| }, | |
| { | |
| "when": "A1&A2&B", | |
| "fall_power pwr_tin_10": { | |
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| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
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| 0.058, | |
| 0.058, | |
| 0.05802, | |
| 0.0581, | |
| 0.05808 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
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| 0.02, | |
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| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
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| ] | |
| } | |
| } | |
| ] | |
| }, | |
| "pin ZN": { | |
| "direction": "output", | |
| "function": "(((!A1)&(!B)&(!C))|((!A2)&(!B)&(!C)))", | |
| "max_capacitance": "0.1691", | |
| "max_transition": "5", | |
| "min_capacitance": "0.001", | |
| "output_voltage": "default", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
| "related_pin": "A1", | |
| "when": "A2&!B&!C", | |
| "fall_power pwr_tin_oload_10x10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.05437, | |
| 0.175, | |
| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "index_2": [ | |
| 0.001, | |
| 0.00216, | |
| 0.006232, | |
| 0.01401, | |
| 0.02612, | |
| 0.04312, | |
| 0.06549, | |
| 0.09367, | |
| 0.1281, | |
| 0.1691 | |
| ], | |
| "values": [ | |
| [ | |
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| 0.0065, | |
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| 0.008007, | |
| 0.008079, | |
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| 0.008221 | |
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| [ | |
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| 0.009802, | |
| 0.01001, | |
| 0.01025, | |
| 0.01038 | |
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| [ | |
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| [ | |
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| [ | |
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| 0.02902, | |
| 0.02715, | |
| 0.02553, | |
| 0.02421 | |
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| [ | |
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| [ | |
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| [ | |
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| ], | |
| [ | |
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| 0.1731, | |
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| [ | |
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| 0.3002, | |
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| 0.2495, | |
| 0.227, | |
| 0.2065 | |
| ] | |
| ] | |
| }, | |
| "rise_power pwr_tin_oload_10x10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.05437, | |
| 0.175, | |
| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
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