{ | |
"description": "4 buffer delay cell", | |
"file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyb", | |
"library": "gf180mcu_fd_sc_mcu7t5v0", | |
"name": "dlyb", | |
"parameters": [], | |
"ports": [ | |
[ | |
"signal", | |
"I", | |
"input", | |
"" | |
], | |
[ | |
"signal", | |
"Z", | |
"output", | |
"" | |
], | |
[ | |
"power", | |
"VDD", | |
"input", | |
"supply1" | |
], | |
[ | |
"power", | |
"VSS", | |
"input", | |
"supply0" | |
] | |
], | |
"type": "cell", | |
"verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyb" | |
} |