| # Copyright 2022 GlobalFoundries PDK Authors |
| # |
| # Licensed under the Apache License, Version 2.0 (the "License"); |
| # you may not use this file except in compliance with the License. |
| # You may obtain a copy of the License at |
| # |
| # https://www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, software |
| # distributed under the License is distributed on an "AS IS" BASIS, |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # See the License for the specific language governing permissions and |
| # limitations under the License. |
| |
| #============================================================================================================================================================= |
| #----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (OTP_MK) ------------------------------------------------------------ |
| #============================================================================================================================================================= |
| |
| require 'time' |
| require "logger" |
| |
| exec_start_time = Time.now |
| |
| logger = Logger.new(STDOUT) |
| |
| logger.formatter = proc do |severity, datetime, progname, msg| |
| "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} |
| " |
| end |
| |
| #================================================ |
| #----------------- FILE SETUP ------------------- |
| #================================================ |
| |
| # optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb |
| |
| logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) |
| |
| if $input |
| if $topcell |
| source($input, $topcell) |
| else |
| source($input) |
| end |
| end |
| |
| logger.info("Loading database to memory is complete.") |
| |
| if $report |
| logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) |
| report("DRC Run Report at", $report) |
| else |
| logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) |
| report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) |
| end |
| |
| if $thr |
| logger.info("Number of threads to use %s" % [$thr]) |
| threads($thr) |
| else |
| logger.info("Number of threads to use 16") |
| threads(16) |
| end |
| |
| # === TILING MODE === |
| if $run_mode == "tiling" |
| # use a tile size of 1mm - not used in deep mode- |
| # tiles(500.um) |
| # use a tile border of 10 micron: |
| # tile_borders(10.um) |
| tiles(1000) |
| logger.info("Tiling mode is enabled.") |
| |
| elsif $run_mode == "deep" |
| #=== HIER MODE === |
| deep |
| logger.info("deep mode is enabled.") |
| |
| elsif $run_mode == "flat" |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| else |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| end # run_mode |
| |
| #================================================ |
| #------------- LAYERS DEFINITIONS --------------- |
| #================================================ |
| |
| v5_xtor = polygons(112, 1 ) |
| dualgate = polygons(55 , 0 ) |
| poly2 = polygons(30 , 0 ) |
| nplus = polygons(32 , 0 ) |
| pplus = polygons(31 , 0 ) |
| comp = polygons(22 , 0 ) |
| sab = polygons(49 , 0 ) |
| contact = polygons(33 , 0 ) |
| otp_mk = polygons(173, 5 ) |
| |
| logger.info("Starting deriving base layers.") |
| #================================================ |
| #------------- LAYERS DERIVATIONS --------------- |
| #================================================ |
| |
| ncomp = comp & nplus |
| pcomp = comp & pplus |
| tgate = poly2 & comp |
| ngate = nplus & tgate |
| pgate = pplus & tgate |
| |
| #================================================ |
| #------------------ SWITCHES -------------------- |
| #================================================ |
| logger.info("Evaluate switches.") |
| |
| # FEOL |
| if $feol == "false" |
| FEOL = $feol |
| logger.info("FEOL is disabled.") |
| else |
| FEOL = "true" |
| logger.info("FEOL is enabled.") |
| end # FEOL |
| |
| # BEOL |
| if $beol == "false" |
| BEOL = $beol |
| logger.info("BEOL is disabled.") |
| else |
| BEOL = "true" |
| logger.info("BEOL is enabled.") |
| end # BEOL |
| |
| # connectivity rules |
| if $conn_drc == "true" |
| CONNECTIVITY_RULES = $conn_drc |
| logger.info("connectivity rules are enabled.") |
| else |
| CONNECTIVITY_RULES = false |
| logger.info("connectivity rules are disabled.") |
| end # connectivity rules |
| |
| # METAL_TOP |
| if $metal_top |
| METAL_TOP = $metal_top |
| else |
| METAL_TOP = "9K" |
| end # METAL_TOP |
| |
| logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) |
| |
| # METAL_LEVEL |
| if $metal_level |
| METAL_LEVEL = $metal_level |
| else |
| METAL_LEVEL = "6LM" |
| end # METAL_LEVEL |
| |
| logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) |
| |
| # WEDGE |
| if $wedge == "false" |
| WEDGE = $wedge |
| else |
| WEDGE = "true" |
| end # WEDGE |
| |
| logger.info("Wedge enabled %s" % [WEDGE]) |
| |
| # BALL |
| if $ball == "false" |
| BALL = $ball |
| else |
| BALL = "true" |
| end # BALL |
| |
| logger.info("Ball enabled %s" % [BALL]) |
| |
| # GOLD |
| if $gold == "false" |
| GOLD = $gold |
| else |
| GOLD = "true" |
| end # GOLD |
| |
| logger.info("Gold enabled %s" % [GOLD]) |
| |
| if $mim_option |
| MIM_OPTION = $mim_option |
| else |
| MIM_OPTION = "Nan" |
| end |
| |
| logger.info("MIM Option selected %s" % [MIM_OPTION]) |
| |
| # OFFGRID |
| if $offgrid == "false" |
| OFFGRID = false |
| else |
| OFFGRID = true |
| end # OFFGRID |
| |
| logger.info("Offgrid enabled %s" % [OFFGRID]) |
| |
| #================================================ |
| #---------------------OTP_MK--------------------- |
| #================================================ |
| |
| # Rule O.DF.3a: Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. is 0.24µm |
| logger.info("Executing rule O.DF.3a") |
| odf3a_l1 = comp.and(otp_mk).space(0.24.um, euclidian).polygons(0.001) |
| odf3a_l1.output("O.DF.3a", "O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm") |
| odf3a_l1.forget |
| |
| # Rule O.DF.6: Min. COMP extend beyond poly2 (it also means source/drain overhang). is 0.22µm |
| logger.info("Executing rule O.DF.6") |
| odf6_l1 = comp.and(otp_mk).enclosing(poly2.and(otp_mk), 0.22.um, euclidian).polygons(0.001) |
| odf6_l1.output("O.DF.6", "O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm") |
| odf6_l1.forget |
| |
| # Rule O.DF.9: Min. COMP area (um2). is 0.1444µm² |
| logger.info("Executing rule O.DF.9") |
| odf9_l1 = comp.and(otp_mk).with_area(nil, 0.1444.um) |
| odf9_l1.output("O.DF.9", "O.DF.9 : Min. COMP area (um2). : 0.1444µm²") |
| odf9_l1.forget |
| # Rule O.PL.2: Min. poly2 width. is 0.22µm |
| logger.info("Executing rule O.PL.2") |
| opl2_l1 = poly2.edges.and(tgate.edges).and(otp_mk).width(0.22.um, euclidian).polygons(0.001) |
| opl2_l1.output("O.PL.2", "O.PL.2 : Min. poly2 width. : 0.22µm") |
| opl2_l1.forget |
| |
| # Rule O.PL.3a: Min. poly2 Space on COMP. is 0.18µm |
| logger.info("Executing rule O.PL.3a") |
| opl3a_l1 = (tgate).or(poly2.not(comp)).and(otp_mk).space(0.18.um, euclidian).polygons(0.001) |
| opl3a_l1.output("O.PL.3a", "O.PL.3a : Min. poly2 Space on COMP. : 0.18µm") |
| opl3a_l1.forget |
| |
| # Rule O.PL.4: Min. extension beyond COMP to form Poly2 end cap. is 0.14µm |
| logger.info("Executing rule O.PL.4") |
| opl4_l1 = poly2.and(otp_mk).enclosing(comp.and(otp_mk), 0.14.um, euclidian).polygons(0.001) |
| opl4_l1.output("O.PL.4", "O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm") |
| opl4_l1.forget |
| |
| # rule O.PL.5a is not a DRC check |
| |
| # rule O.PL.5b is not a DRC check |
| |
| # Rule O.SB.2: Min. salicide Block Space. is 0.28µm |
| logger.info("Executing rule O.SB.2") |
| osb2_l1 = sab.and(otp_mk).space(0.28.um, euclidian).polygons(0.001) |
| osb2_l1.output("O.SB.2", "O.SB.2 : Min. salicide Block Space. : 0.28µm") |
| osb2_l1.forget |
| |
| # Rule O.SB.3: Min. space from salicide block to unrelated COMP. is 0.09µm |
| logger.info("Executing rule O.SB.3") |
| osb3_l1 = sab.outside(comp).and(otp_mk).separation(comp.outside(sab), 0.09.um, euclidian).polygons(0.001) |
| osb3_l1.output("O.SB.3", "O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm") |
| osb3_l1.forget |
| |
| # Rule O.SB.4: Min. space from salicide block to contact. |
| logger.info("Executing rule O.SB.4") |
| osb4_l1 = sab.and(otp_mk).separation(contact, 0.03.um, euclidian).polygons(0.001).or(sab.and(otp_mk).and(contact)) |
| osb4_l1.output("O.SB.4", "O.SB.4 : Min. space from salicide block to contact.") |
| osb4_l1.forget |
| |
| # rule O.SB.5a is not a DRC check |
| |
| # Rule O.SB.5b_3.3V: Min. space from salicide block to unrelated Poly2 on COMP. is 0.1µm |
| logger.info("Executing rule O.SB.5b_3.3V") |
| osb5b_l1 = sab.outside(tgate).and(otp_mk).separation(tgate.outside(sab), 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| osb5b_l1.output("O.SB.5b_3.3V", "O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm") |
| osb5b_l1.forget |
| |
| # rule O.SB.5b_5V is not a DRC check |
| |
| # Rule O.SB.9: Min. salicide block extension beyond unsalicided Poly2. is 0.1µm |
| logger.info("Executing rule O.SB.9") |
| osb9_l1 = sab.and(otp_mk).enclosing(poly2.and(sab), 0.1.um, euclidian).polygons |
| osb9_l1.output("O.SB.9", "O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm") |
| osb9_l1.forget |
| |
| # Rule O.SB.11: Min. salicide block overlap with COMP. is 0.04µm |
| logger.info("Executing rule O.SB.11") |
| osb11_l1 = sab.and(otp_mk).overlap(comp, 0.04.um, euclidian).polygons |
| osb11_l1.output("O.SB.11", "O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm") |
| osb11_l1.forget |
| |
| # rule O.SB.12 is not a DRC check |
| |
| # Rule O.SB.13_3.3V: Min. area of silicide block (um2). is 1.488µm² |
| logger.info("Executing rule O.SB.13_3.3V") |
| osb13_l1 = sab.and(otp_mk).with_area(nil, 1.488.um).not_interacting(v5_xtor).not_interacting(dualgate) |
| osb13_l1.output("O.SB.13_3.3V", "O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²") |
| osb13_l1.forget |
| # Rule O.SB.13_5V: Min. area of silicide block (um2). is 2µm² |
| logger.info("Executing rule O.SB.13_5V") |
| osb13_l1 = sab.and(otp_mk).and(v5_xtor).with_area(nil, 2.um) |
| osb13_l1.output("O.SB.13_5V", "O.SB.13_5V : Min. area of silicide block (um2). : 2µm²") |
| osb13_l1.forget |
| # rule O.SB.15b is not a DRC check |
| |
| # Rule O.CO.7: Min. space from COMP contact to Poly2 on COMP. is 0.13µm |
| logger.info("Executing rule O.CO.7") |
| oco7_l1 = contact.not_outside(comp).and(otp_mk).separation(tgate.and(otp_mk), 0.13.um, euclidian).polygons(0.001) |
| oco7_l1.output("O.CO.7", "O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm") |
| oco7_l1.forget |
| |
| # Rule O.PL.ORT: Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. is 0µm |
| logger.info("Executing rule O.PL.ORT") |
| oplort_l1 = comp.not(poly2).edges.and(tgate.edges).and(otp_mk).without_angle(0.um).extended(0, 0, 0.001, 0.001) |
| oplort_l1.output("O.PL.ORT", "O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm") |
| oplort_l1.forget |
| |
| |
| exec_end_time = Time.now |
| run_time = exec_end_time - exec_start_time |
| logger.info("DRC Run time %f seconds" % [run_time]) |
| |