| # Copyright 2022 GlobalFoundries PDK Authors |
| # |
| # Licensed under the Apache License, Version 2.0 (the "License"); |
| # you may not use this file except in compliance with the License. |
| # You may obtain a copy of the License at |
| # |
| # https://www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, software |
| # distributed under the License is distributed on an "AS IS" BASIS, |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # See the License for the specific language governing permissions and |
| # limitations under the License. |
| |
| #============================================================================================================================================================= |
| #------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (POLY2) ------------------------------------------------------------ |
| #============================================================================================================================================================= |
| |
| require 'time' |
| require "logger" |
| |
| exec_start_time = Time.now |
| |
| logger = Logger.new(STDOUT) |
| |
| logger.formatter = proc do |severity, datetime, progname, msg| |
| "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} |
| " |
| end |
| |
| #================================================ |
| #----------------- FILE SETUP ------------------- |
| #================================================ |
| |
| # optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb |
| |
| logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) |
| |
| if $input |
| if $topcell |
| source($input, $topcell) |
| else |
| source($input) |
| end |
| end |
| |
| logger.info("Loading database to memory is complete.") |
| |
| if $report |
| logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) |
| report("DRC Run Report at", $report) |
| else |
| logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) |
| report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) |
| end |
| |
| if $thr |
| logger.info("Number of threads to use %s" % [$thr]) |
| threads($thr) |
| else |
| logger.info("Number of threads to use 16") |
| threads(16) |
| end |
| |
| # === TILING MODE === |
| if $run_mode == "tiling" |
| # use a tile size of 1mm - not used in deep mode- |
| # tiles(500.um) |
| # use a tile border of 10 micron: |
| # tile_borders(10.um) |
| tiles(1000) |
| logger.info("Tiling mode is enabled.") |
| |
| elsif $run_mode == "deep" |
| #=== HIER MODE === |
| deep |
| logger.info("deep mode is enabled.") |
| |
| elsif $run_mode == "flat" |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| else |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| end # run_mode |
| |
| #================================================ |
| #------------- LAYERS DEFINITIONS --------------- |
| #================================================ |
| |
| v5_xtor = polygons(112, 1 ) |
| dualgate = polygons(55 , 0 ) |
| poly2 = polygons(30 , 0 ) |
| nplus = polygons(32 , 0 ) |
| pplus = polygons(31 , 0 ) |
| comp = polygons(22 , 0 ) |
| mvsd = polygons(210, 0 ) |
| mvpsd = polygons(11 , 39) |
| res_mk = polygons(110, 5 ) |
| otp_mk = polygons(173, 5 ) |
| sramcore = polygons(108, 5 ) |
| plfuse = polygons(125, 5 ) |
| ymtp_mk = polygons(86 , 17) |
| |
| logger.info("Starting deriving base layers.") |
| #================================================ |
| #------------- LAYERS DERIVATIONS --------------- |
| #================================================ |
| |
| ncomp = comp & nplus |
| pcomp = comp & pplus |
| tgate = poly2 & comp |
| ngate = nplus & tgate |
| pgate = pplus & tgate |
| |
| #================================================ |
| #------------------ SWITCHES -------------------- |
| #================================================ |
| logger.info("Evaluate switches.") |
| |
| # FEOL |
| if $feol == "false" |
| FEOL = $feol |
| logger.info("FEOL is disabled.") |
| else |
| FEOL = "true" |
| logger.info("FEOL is enabled.") |
| end # FEOL |
| |
| # BEOL |
| if $beol == "false" |
| BEOL = $beol |
| logger.info("BEOL is disabled.") |
| else |
| BEOL = "true" |
| logger.info("BEOL is enabled.") |
| end # BEOL |
| |
| # connectivity rules |
| if $conn_drc == "true" |
| CONNECTIVITY_RULES = $conn_drc |
| logger.info("connectivity rules are enabled.") |
| else |
| CONNECTIVITY_RULES = false |
| logger.info("connectivity rules are disabled.") |
| end # connectivity rules |
| |
| # METAL_TOP |
| if $metal_top |
| METAL_TOP = $metal_top |
| else |
| METAL_TOP = "9K" |
| end # METAL_TOP |
| |
| logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) |
| |
| # METAL_LEVEL |
| if $metal_level |
| METAL_LEVEL = $metal_level |
| else |
| METAL_LEVEL = "6LM" |
| end # METAL_LEVEL |
| |
| logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) |
| |
| # WEDGE |
| if $wedge == "false" |
| WEDGE = $wedge |
| else |
| WEDGE = "true" |
| end # WEDGE |
| |
| logger.info("Wedge enabled %s" % [WEDGE]) |
| |
| # BALL |
| if $ball == "false" |
| BALL = $ball |
| else |
| BALL = "true" |
| end # BALL |
| |
| logger.info("Ball enabled %s" % [BALL]) |
| |
| # GOLD |
| if $gold == "false" |
| GOLD = $gold |
| else |
| GOLD = "true" |
| end # GOLD |
| |
| logger.info("Gold enabled %s" % [GOLD]) |
| |
| if $mim_option |
| MIM_OPTION = $mim_option |
| else |
| MIM_OPTION = "Nan" |
| end |
| |
| logger.info("MIM Option selected %s" % [MIM_OPTION]) |
| |
| # OFFGRID |
| if $offgrid == "false" |
| OFFGRID = false |
| else |
| OFFGRID = true |
| end # OFFGRID |
| |
| logger.info("Offgrid enabled %s" % [OFFGRID]) |
| |
| #================================================ |
| #---------------------POLY2---------------------- |
| #================================================ |
| |
| |
| if FEOL |
| logger.info("FEOL section") |
| |
| # Rule PL.1_3.3V: Interconnect Width (outside PLFUSE). is 0.18µm |
| logger.info("Executing rule PL.1_3.3V") |
| pl1_l1 = poly2.outside(plfuse).not(ymtp_mk).width(0.18.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| pl1_l1.output("PL.1_3.3V", "PL.1_3.3V : Interconnect Width (outside PLFUSE). : 0.18µm") |
| pl1_l1.forget |
| |
| # Rule PL.1_5V: Interconnect Width (outside PLFUSE). is 0.2µm |
| logger.info("Executing rule PL.1_5V") |
| pl1_l1 = poly2.outside(plfuse).not(ymtp_mk).width(0.2.um, euclidian).polygons(0.001).overlapping(dualgate) |
| pl1_l1.output("PL.1_5V", "PL.1_5V : Interconnect Width (outside PLFUSE). : 0.2µm") |
| pl1_l1.forget |
| |
| # Rule PL.1a_3.3V: Interconnect Width (inside PLFUSE). is 0.18µm |
| logger.info("Executing rule PL.1a_3.3V") |
| pl1a_l1 = poly2.inside(plfuse).width(0.18.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| pl1a_l1.output("PL.1a_3.3V", "PL.1a_3.3V : Interconnect Width (inside PLFUSE). : 0.18µm") |
| pl1a_l1.forget |
| |
| # Rule PL.1a_5V: Interconnect Width (inside PLFUSE). is 0.18µm |
| logger.info("Executing rule PL.1a_5V") |
| pl1a_l1 = poly2.inside(plfuse).width(0.18.um, euclidian).polygons(0.001).overlapping(dualgate) |
| pl1a_l1.output("PL.1a_5V", "PL.1a_5V : Interconnect Width (inside PLFUSE). : 0.18µm") |
| pl1a_l1.forget |
| |
| # Rule PL.2_3.3V: Gate Width (Channel Length). is 0.28µm |
| logger.info("Executing rule PL.2_3.3V") |
| pl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).not(ymtp_mk).width(0.28.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| pl2_l1.output("PL.2_3.3V", "PL.2_3.3V : Gate Width (Channel Length). : 0.28µm") |
| pl2_l1.forget |
| |
| pl_2_5v_n = comp.not(poly2).edges.and(ngate.edges).and(v5_xtor).and(dualgate).space(0.6.um, euclidian).polygons |
| pl_2_5v_p = comp.not(poly2).edges.and(pgate.edges).and(v5_xtor).and(dualgate).space(0.5.um, euclidian).polygons |
| pl_2_6v_n = comp.not(poly2).edges.and(ngate.edges).not(v5_xtor).and(dualgate).space(0.7.um, euclidian).polygons |
| pl_2_6v_p = comp.not(poly2).edges.and(pgate.edges).not(v5_xtor).and(dualgate).space(0.55.um, euclidian).polygons |
| # Rule PL.2_5V: Gate Width (Channel Length). |
| logger.info("Executing rule PL.2_5V") |
| pl2_l1 = pl_2_5v_n.or(pl_2_5v_p).or(pl_2_6v_n.or(pl_2_6v_p)) |
| pl2_l1.output("PL.2_5V", "PL.2_5V : Gate Width (Channel Length).") |
| pl2_l1.forget |
| |
| pl_2_5v_n.forget |
| pl_2_5v_p.forget |
| pl_2_6v_n.forget |
| pl_2_6v_p.forget |
| # Rule PL.3a_3.3V: Space on COMP/Field. is 0.24µm |
| logger.info("Executing rule PL.3a_3.3V") |
| pl3a_l1 = (tgate).or(poly2.not(comp)).not(otp_mk).space(0.24.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| pl3a_l1.output("PL.3a_3.3V", "PL.3a_3.3V : Space on COMP/Field. : 0.24µm") |
| pl3a_l1.forget |
| |
| # Rule PL.3a_5V: Space on COMP/Field. is 0.24µm |
| logger.info("Executing rule PL.3a_5V") |
| pl3a_l1 = (tgate).or(poly2.not(comp)).not(otp_mk).space(0.24.um, euclidian).polygons(0.001).overlapping(dualgate) |
| pl3a_l1.output("PL.3a_5V", "PL.3a_5V : Space on COMP/Field. : 0.24µm") |
| pl3a_l1.forget |
| |
| # rule PL.3b_3.3V is not a DRC check |
| |
| # rule PL.3b_5V is not a DRC check |
| |
| poly_pl = poly2.not(otp_mk).not(ymtp_mk).not(mvsd).not(mvpsd) |
| comp_pl = comp.not(otp_mk).not(ymtp_mk).not(mvsd).not(mvpsd) |
| # Rule PL.4_3.3V: Extension beyond COMP to form Poly2 end cap. is 0.22µm |
| logger.info("Executing rule PL.4_3.3V") |
| pl4_l1 = poly_pl.enclosing(comp.not(otp_mk).not(ymtp_mk), 0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| pl4_l1.output("PL.4_3.3V", "PL.4_3.3V : Extension beyond COMP to form Poly2 end cap. : 0.22µm") |
| pl4_l1.forget |
| |
| # Rule PL.4_5V: Extension beyond COMP to form Poly2 end cap. is 0.22µm |
| logger.info("Executing rule PL.4_5V") |
| pl4_l1 = poly_pl.enclosing(comp.not(otp_mk).not(ymtp_mk), 0.22.um, euclidian).polygons(0.001).overlapping(dualgate) |
| pl4_l1.output("PL.4_5V", "PL.4_5V : Extension beyond COMP to form Poly2 end cap. : 0.22µm") |
| pl4_l1.forget |
| |
| # Rule PL.5a_3.3V: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.1µm |
| logger.info("Executing rule PL.5a_3.3V") |
| pl5a_l1 = poly_pl.separation(comp_pl, 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| pl5a_l1.output("PL.5a_3.3V", "PL.5a_3.3V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.1µm") |
| pl5a_l1.forget |
| |
| # Rule PL.5a_5V: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.3µm |
| logger.info("Executing rule PL.5a_5V") |
| pl5a_l1 = poly_pl.outside(sramcore).separation(comp_pl, 0.3.um, euclidian).polygons(0.001).overlapping(dualgate) |
| pl5a_l1.output("PL.5a_5V", "PL.5a_5V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.3µm") |
| pl5a_l1.forget |
| |
| # Rule PL.5b_3.3V: Space from field Poly2 to related COMP. is 0.1µm |
| logger.info("Executing rule PL.5b_3.3V") |
| pl5b_l1 = poly_pl.separation(comp_pl, 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| pl5b_l1.output("PL.5b_3.3V", "PL.5b_3.3V : Space from field Poly2 to related COMP. : 0.1µm") |
| pl5b_l1.forget |
| |
| # Rule PL.5b_5V: Space from field Poly2 to related COMP. is 0.3µm |
| logger.info("Executing rule PL.5b_5V") |
| pl5b_l1 = poly_pl.outside(sramcore).separation(comp_pl, 0.3.um, euclidian).polygons(0.001).overlapping(dualgate) |
| pl5b_l1.output("PL.5b_5V", "PL.5b_5V : Space from field Poly2 to related COMP. : 0.3µm") |
| pl5b_l1.forget |
| |
| poly_pl.forget |
| comp_pl.forget |
| poly_90deg = poly2.corners(90.0).sized(0.1).or(poly2.corners(-90.0).sized(0.1)).not(ymtp_mk) |
| # Rule PL.6: 90 degree bends on the COMP are not allowed. |
| logger.info("Executing rule PL.6") |
| pl6_l1 = poly2.corners(90.0).sized(0.1).or(poly2.corners(-90.0).sized(0.1)).not(ymtp_mk).inside(comp.not(ymtp_mk)) |
| pl6_l1.output("PL.6", "PL.6 : 90 degree bends on the COMP are not allowed.") |
| pl6_l1.forget |
| |
| poly_90deg.forget |
| poly_45deg = poly2.edges.with_angle(-45).or(poly2.edges.with_angle(45)) |
| # Rule PL.7_3.3V: 45 degree bent gate width is 0.3µm |
| logger.info("Executing rule PL.7_3.3V") |
| pl7_l1 = poly_45deg.width(0.3.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| pl7_l1.output("PL.7_3.3V", "PL.7_3.3V : 45 degree bent gate width : 0.3µm") |
| pl7_l1.forget |
| |
| # Rule PL.7_5V: 45 degree bent gate width is 0.7µm |
| logger.info("Executing rule PL.7_5V") |
| pl7_l1 = poly_45deg.width(0.7.um, euclidian).polygons(0.001).overlapping(dualgate) |
| pl7_l1.output("PL.7_5V", "PL.7_5V : 45 degree bent gate width : 0.7µm") |
| pl7_l1.forget |
| |
| poly_45deg.forget |
| # Rule PL.9: Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only. |
| logger.info("Executing rule PL.9") |
| pl9_l1 = poly2.interacting(poly2.not(v5_xtor).not(dualgate)).interacting(poly2.and(dualgate)) |
| pl9_l1.output("PL.9", "PL.9 : Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only.") |
| pl9_l1.forget |
| |
| # rule PL.10 is not a DRC check |
| |
| # Rule PL.11: V5_Xtor must enclose 5V device. |
| logger.info("Executing rule PL.11") |
| pl11_l1 = v5_xtor.not_interacting(dualgate.or(otp_mk)) |
| pl11_l1.output("PL.11", "PL.11 : V5_Xtor must enclose 5V device.") |
| pl11_l1.forget |
| |
| # rule PL.12_3.3V is not a DRC check |
| |
| # Rule PL.12: V5_Xtor enclose 5V Comp. |
| logger.info("Executing rule PL.12") |
| pl12_l1 = comp.interacting(v5_xtor).not(v5_xtor) |
| pl12_l1.output("PL.12", "PL.12 : V5_Xtor enclose 5V Comp.") |
| pl12_l1.forget |
| |
| |
| end #FEOL |
| |
| |
| exec_end_time = Time.now |
| run_time = exec_end_time - exec_start_time |
| logger.info("DRC Run time %f seconds" % [run_time]) |
| |
