| # Copyright 2022 GlobalFoundries PDK Authors |
| # |
| # Licensed under the Apache License, Version 2.0 (the "License"); |
| # you may not use this file except in compliance with the License. |
| # You may obtain a copy of the License at |
| # |
| # https://www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, software |
| # distributed under the License is distributed on an "AS IS" BASIS, |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # See the License for the specific language governing permissions and |
| # limitations under the License. |
| |
| #============================================================================================================================================================= |
| #------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (NATIVE VT NMOS) -------------------------------------------------------- |
| #============================================================================================================================================================= |
| |
| require 'time' |
| require "logger" |
| |
| exec_start_time = Time.now |
| |
| logger = Logger.new(STDOUT) |
| |
| logger.formatter = proc do |severity, datetime, progname, msg| |
| "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} |
| " |
| end |
| |
| #================================================ |
| #----------------- FILE SETUP ------------------- |
| #================================================ |
| |
| # optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb |
| |
| logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) |
| |
| if $input |
| if $topcell |
| source($input, $topcell) |
| else |
| source($input) |
| end |
| end |
| |
| logger.info("Loading database to memory is complete.") |
| |
| if $report |
| logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) |
| report("DRC Run Report at", $report) |
| else |
| logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) |
| report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) |
| end |
| |
| if $thr |
| logger.info("Number of threads to use %s" % [$thr]) |
| threads($thr) |
| else |
| logger.info("Number of threads to use 16") |
| threads(16) |
| end |
| |
| # === TILING MODE === |
| if $run_mode == "tiling" |
| # use a tile size of 1mm - not used in deep mode- |
| # tiles(500.um) |
| # use a tile border of 10 micron: |
| # tile_borders(10.um) |
| tiles(1000) |
| logger.info("Tiling mode is enabled.") |
| |
| elsif $run_mode == "deep" |
| #=== HIER MODE === |
| deep |
| logger.info("deep mode is enabled.") |
| |
| elsif $run_mode == "flat" |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| else |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| end # run_mode |
| |
| #================================================ |
| #------------- LAYERS DEFINITIONS --------------- |
| #================================================ |
| |
| v5_xtor = polygons(112, 1 ) |
| dualgate = polygons(55 , 0 ) |
| poly2 = polygons(30 , 0 ) |
| nplus = polygons(32 , 0 ) |
| pplus = polygons(31 , 0 ) |
| comp = polygons(22 , 0 ) |
| nwell = polygons(21 , 0 ) |
| nat = polygons(5 , 0 ) |
| |
| logger.info("Starting deriving base layers.") |
| #================================================ |
| #------------- LAYERS DERIVATIONS --------------- |
| #================================================ |
| |
| ncomp = comp & nplus |
| pcomp = comp & pplus |
| tgate = poly2 & comp |
| ngate = nplus & tgate |
| pgate = pplus & tgate |
| |
| #================================================ |
| #------------------ SWITCHES -------------------- |
| #================================================ |
| logger.info("Evaluate switches.") |
| |
| # FEOL |
| if $feol == "false" |
| FEOL = $feol |
| logger.info("FEOL is disabled.") |
| else |
| FEOL = "true" |
| logger.info("FEOL is enabled.") |
| end # FEOL |
| |
| # BEOL |
| if $beol == "false" |
| BEOL = $beol |
| logger.info("BEOL is disabled.") |
| else |
| BEOL = "true" |
| logger.info("BEOL is enabled.") |
| end # BEOL |
| |
| # connectivity rules |
| if $conn_drc == "true" |
| CONNECTIVITY_RULES = $conn_drc |
| logger.info("connectivity rules are enabled.") |
| else |
| CONNECTIVITY_RULES = false |
| logger.info("connectivity rules are disabled.") |
| end # connectivity rules |
| |
| # METAL_TOP |
| if $metal_top |
| METAL_TOP = $metal_top |
| else |
| METAL_TOP = "9K" |
| end # METAL_TOP |
| |
| logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) |
| |
| # METAL_LEVEL |
| if $metal_level |
| METAL_LEVEL = $metal_level |
| else |
| METAL_LEVEL = "6LM" |
| end # METAL_LEVEL |
| |
| logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) |
| |
| # WEDGE |
| if $wedge == "false" |
| WEDGE = $wedge |
| else |
| WEDGE = "true" |
| end # WEDGE |
| |
| logger.info("Wedge enabled %s" % [WEDGE]) |
| |
| # BALL |
| if $ball == "false" |
| BALL = $ball |
| else |
| BALL = "true" |
| end # BALL |
| |
| logger.info("Ball enabled %s" % [BALL]) |
| |
| # GOLD |
| if $gold == "false" |
| GOLD = $gold |
| else |
| GOLD = "true" |
| end # GOLD |
| |
| logger.info("Gold enabled %s" % [GOLD]) |
| |
| if $mim_option |
| MIM_OPTION = $mim_option |
| else |
| MIM_OPTION = "Nan" |
| end |
| |
| logger.info("MIM Option selected %s" % [MIM_OPTION]) |
| |
| # OFFGRID |
| if $offgrid == "false" |
| OFFGRID = false |
| else |
| OFFGRID = true |
| end # OFFGRID |
| |
| logger.info("Offgrid enabled %s" % [OFFGRID]) |
| natcompsd = (nat & comp.interacting(poly2)) - tgate |
| |
| if CONNECTIVITY_RULES |
| logger.info("Construct connectivity for NAT layer.") |
| connect(natcompsd, contact) |
| end #CONNECTIVITY_RULES |
| |
| |
| |
| #================================================ |
| #-----------------NATIVE VT NMOS----------------- |
| #================================================ |
| |
| # Rule NAT.1: Min. NAT Overlap of COMP of Native Vt NMOS. is 2µm |
| logger.info("Executing rule NAT.1") |
| nat1_l1 = nat.enclosing(ncomp.outside(nwell).interacting(nat), 2.um, euclidian).polygons(0.001) |
| nat1_l1.output("NAT.1", "NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm") |
| nat1_l1.forget |
| |
| # Rule NAT.2: Space to unrelated COMP (outside NAT). is 0.3µm |
| logger.info("Executing rule NAT.2") |
| nat2_l1 = nat.separation(comp.outside(nat), 0.3.um, euclidian).polygons(0.001) |
| nat2_l1.output("NAT.2", "NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm") |
| nat2_l1.forget |
| |
| # Rule NAT.3: Space to NWell edge. is 0.5µm |
| logger.info("Executing rule NAT.3") |
| nat3_l1 = nat.separation(nwell, 0.5.um, euclidian).polygons(0.001) |
| nat3_l1.output("NAT.3", "NAT.3 : Space to NWell edge. : 0.5µm") |
| nat3_l1.forget |
| |
| # Rule NAT.4: Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). is 1.8µm |
| logger.info("Executing rule NAT.4") |
| nat4_l1 = poly2.edges.and(ngate.edges).not(nwell).interacting(nat).width(1.8.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) |
| nat4_l1.output("NAT.4", "NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm") |
| nat4_l1.forget |
| |
| # Rule NAT.5: Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). is 1.8µm |
| logger.info("Executing rule NAT.5") |
| nat5_l1 = poly2.edges.and(ngate.edges).not(nwell).interacting(nat).width(1.8.um, euclidian).polygons(0.001).overlapping(dualgate) |
| nat5_l1.output("NAT.5", "NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm") |
| nat5_l1.forget |
| |
| if CONNECTIVITY_RULES |
| logger.info("CONNECTIVITY_RULES section") |
| |
| connected_nat, unconnected_nat = conn_space(natcompsd, 10, 10, transparent) |
| |
| # Rule NAT.6: Two or more COMPs if connected to different potential are not allowed under same NAT layer. |
| logger.info("Executing rule NAT.6") |
| nat6_l1 = comp.and(nat).interacting(unconnected_nat.inside(nat.covering(comp, 2)).not(poly2)) |
| nat6_l1.output("NAT.6", "NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.") |
| nat6_l1.forget |
| |
| end #CONNECTIVITY_RULES |
| |
| natcompsd.forget |
| # Rule NAT.7: Minimum NAT to NAT spacing. is 0.74µm |
| logger.info("Executing rule NAT.7") |
| nat7_l1 = nat.space(0.74.um, euclidian).polygons(0.001) |
| nat7_l1.output("NAT.7", "NAT.7 : Minimum NAT to NAT spacing. : 0.74µm") |
| nat7_l1.forget |
| |
| # Rule NAT.8: Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only. |
| logger.info("Executing rule NAT.8") |
| nat8_l1 = nat.not_outside(dualgate).not(dualgate) |
| nat8_l1.output("NAT.8", "NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.") |
| nat8_l1.forget |
| |
| nat9_1 = poly2.and(nat).not(ncomp).interacting(ngate.and(nat) , 2) |
| nat9_2 = poly2.not(nat).separation(nat, 0.3.um, euclidian).polygons(0.001) |
| # Rule NAT.9: Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer. |
| logger.info("Executing rule NAT.9") |
| nat9_l1 = nat9_1.or(nat9_2) |
| nat9_l1.output("NAT.9", "NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.") |
| nat9_l1.forget |
| |
| nat9_1.forget |
| nat9_2.forget |
| # Rule NAT.10: Nwell, inside NAT layer are not allowed. |
| logger.info("Executing rule NAT.10") |
| nat10_l1 = nwell.inside(nat) |
| nat10_l1.output("NAT.10", "NAT.10 : Nwell, inside NAT layer are not allowed.") |
| nat10_l1.forget |
| |
| # Rule NAT.11: NCOMP not intersecting to Poly2, is not allowed inside NAT layer. |
| logger.info("Executing rule NAT.11") |
| nat11_l1 = ncomp.and(nat).outside(poly2) |
| nat11_l1.output("NAT.11", "NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.") |
| nat11_l1.forget |
| |
| # Rule NAT.12: Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT). |
| logger.info("Executing rule NAT.12") |
| nat12_l1 = poly2.interacting(nat).not_interacting(comp.and(nat)) |
| nat12_l1.output("NAT.12", "NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).") |
| nat12_l1.forget |
| |
| |
| exec_end_time = Time.now |
| run_time = exec_end_time - exec_start_time |
| logger.info("DRC Run time %f seconds" % [run_time]) |
| |