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# Copyright 2022 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#=============================================================================================================================================================
#---------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (DUALGATE) -----------------------------------------------------------
#=============================================================================================================================================================
require 'time'
require "logger"
exec_start_time = Time.now
logger = Logger.new(STDOUT)
logger.formatter = proc do |severity, datetime, progname, msg|
"#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg}
"
end
#================================================
#----------------- FILE SETUP -------------------
#================================================
# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb
logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input])
if $input
if $topcell
source($input, $topcell)
else
source($input)
end
end
logger.info("Loading database to memory is complete.")
if $report
logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report])
report("DRC Run Report at", $report)
else
logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path])
report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb"))
end
if $thr
logger.info("Number of threads to use %s" % [$thr])
threads($thr)
else
logger.info("Number of threads to use 16")
threads(16)
end
# === TILING MODE ===
if $run_mode == "tiling"
# use a tile size of 1mm - not used in deep mode-
# tiles(500.um)
# use a tile border of 10 micron:
# tile_borders(10.um)
tiles(1000)
logger.info("Tiling mode is enabled.")
elsif $run_mode == "deep"
#=== HIER MODE ===
deep
logger.info("deep mode is enabled.")
elsif $run_mode == "flat"
#=== FLAT MODE ===
flat
logger.info("flat mode is enabled.")
else
#=== FLAT MODE ===
flat
logger.info("flat mode is enabled.")
end # run_mode
#================================================
#------------- LAYERS DEFINITIONS ---------------
#================================================
v5_xtor = polygons(112, 1 )
dualgate = polygons(55 , 0 )
poly2 = polygons(30 , 0 )
nplus = polygons(32 , 0 )
pplus = polygons(31 , 0 )
comp = polygons(22 , 0 )
dnwell = polygons(12 , 0 )
nwell = polygons(21 , 0 )
logger.info("Starting deriving base layers.")
#================================================
#------------- LAYERS DERIVATIONS ---------------
#================================================
ncomp = comp & nplus
pcomp = comp & pplus
tgate = poly2 & comp
ngate = nplus & tgate
pgate = pplus & tgate
#================================================
#------------------ SWITCHES --------------------
#================================================
logger.info("Evaluate switches.")
# FEOL
if $feol == "false"
FEOL = $feol
logger.info("FEOL is disabled.")
else
FEOL = "true"
logger.info("FEOL is enabled.")
end # FEOL
# BEOL
if $beol == "false"
BEOL = $beol
logger.info("BEOL is disabled.")
else
BEOL = "true"
logger.info("BEOL is enabled.")
end # BEOL
# connectivity rules
if $conn_drc == "true"
CONNECTIVITY_RULES = $conn_drc
logger.info("connectivity rules are enabled.")
else
CONNECTIVITY_RULES = false
logger.info("connectivity rules are disabled.")
end # connectivity rules
# METAL_TOP
if $metal_top
METAL_TOP = $metal_top
else
METAL_TOP = "9K"
end # METAL_TOP
logger.info("METAL_TOP Selected is %s" % [METAL_TOP])
# METAL_LEVEL
if $metal_level
METAL_LEVEL = $metal_level
else
METAL_LEVEL = "6LM"
end # METAL_LEVEL
logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL])
# WEDGE
if $wedge == "false"
WEDGE = $wedge
else
WEDGE = "true"
end # WEDGE
logger.info("Wedge enabled %s" % [WEDGE])
# BALL
if $ball == "false"
BALL = $ball
else
BALL = "true"
end # BALL
logger.info("Ball enabled %s" % [BALL])
# GOLD
if $gold == "false"
GOLD = $gold
else
GOLD = "true"
end # GOLD
logger.info("Gold enabled %s" % [GOLD])
if $mim_option
MIM_OPTION = $mim_option
else
MIM_OPTION = "Nan"
end
logger.info("MIM Option selected %s" % [MIM_OPTION])
# OFFGRID
if $offgrid == "false"
OFFGRID = false
else
OFFGRID = true
end # OFFGRID
logger.info("Offgrid enabled %s" % [OFFGRID])
#================================================
#--------------------DUALGATE--------------------
#================================================
if FEOL
logger.info("FEOL section")
# Rule DV.1: Min. Dualgate enclose DNWELL. is 0.5µm
logger.info("Executing rule DV.1")
dv1_l1 = dualgate.enclosing(dnwell, 0.5.um, euclidian).polygons(0.001)
dv1_l2 = dnwell.not_outside(dualgate).not(dualgate)
dv1_l = dv1_l1.or(dv1_l2)
dv1_l.output("DV.1", "DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm")
dv1_l1.forget
dv1_l2.forget
dv1_l.forget
# Rule DV.2: Min. Dualgate Space. Merge if Space is less than this design rule. is 0.44µm
logger.info("Executing rule DV.2")
dv2_l1 = dualgate.space(0.44.um, euclidian).polygons(0.001)
dv2_l1.output("DV.2", "DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm")
dv2_l1.forget
# Rule DV.3: Min. Dualgate to COMP space [unrelated]. is 0.24µm
logger.info("Executing rule DV.3")
dv3_l1 = dualgate.separation(comp.outside(dualgate), 0.24.um, euclidian).polygons(0.001)
dv3_l1.output("DV.3", "DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm")
dv3_l1.forget
# rule DV.4 is not a DRC check
# Rule DV.5: Min. Dualgate width. is 0.7µm
logger.info("Executing rule DV.5")
dv5_l1 = dualgate.width(0.7.um, euclidian).polygons(0.001)
dv5_l1.output("DV.5", "DV.5 : Min. Dualgate width. : 0.7µm")
dv5_l1.forget
comp_dv = comp.not(pcomp.outside(nwell))
# Rule DV.6: Min. Dualgate enclose COMP (except substrate tap). is 0.24µm
logger.info("Executing rule DV.6")
dv6_l1 = dualgate.enclosing(comp_dv, 0.24.um, euclidian).polygons(0.001)
dv6_l2 = comp_dv.not_outside(dualgate).not(dualgate)
dv6_l = dv6_l1.or(dv6_l2)
dv6_l.output("DV.6", "DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm")
dv6_l1.forget
dv6_l2.forget
dv6_l.forget
# Rule DV.7: COMP (except substrate tap) can not be partially overlapped by Dualgate.
logger.info("Executing rule DV.7")
dv7_l1 = dualgate.not_outside(comp_dv).not(dualgate.covering(comp_dv))
dv7_l1.output("DV.7", "DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.")
dv7_l1.forget
comp_dv.forget
# Rule DV.8: Min Dualgate enclose Poly2. is 0.4µm
logger.info("Executing rule DV.8")
dv8_l1 = dualgate.enclosing(poly2, 0.4.um, euclidian).polygons(0.001)
dv8_l2 = poly2.not_outside(dualgate).not(dualgate)
dv8_l = dv8_l1.or(dv8_l2)
dv8_l.output("DV.8", "DV.8 : Min Dualgate enclose Poly2. : 0.4µm")
dv8_l1.forget
dv8_l2.forget
dv8_l.forget
# Rule DV.9: 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.
logger.info("Executing rule DV.9")
dv9_l1 = nwell.covering(pgate.and(dualgate)).covering(pgate.not_inside(v5_xtor).not_inside(dualgate))
dv9_l1.output("DV.9", "DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.")
dv9_l1.forget
end #FEOL
exec_end_time = Time.now
run_time = exec_end_time - exec_start_time
logger.info("DRC Run time %f seconds" % [run_time])