blob: 4cb584cf8971e1fb3fed7598387fab26924ac793 [file] [log] [blame]
*Xyce Common Source Circuit
** library calling
* .OPTIONS DEVICE TEMP=-40
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** main netlist
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Vds D_tn 0 dc -3.3
Vgs G_tn 0 dc -3.3
xmn1 D_tn G_tn 0 0 pmos_6p0 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as={{AS}}u ps={{PS}}u
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** Analysis
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.DC Vds 0 -6.6 -0.05 Vgs -1 -6 -1
.STEP TEMP {{temp}} -60 200
.print DC FORMAT=CSV file=pmos_6p0_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
.include "../../../../../design.xyce"
.lib "../../../../../sm141064.xyce" typical
.end