| 7.7 Poly2 |
| ================================= |
| |
| Poly2 defines the Poly2-Gate on CMOS device. The minimum channel length for 1.8V, 5V and 6V CMOS device are |
| 0.18um, 0.5um and 0.6um respectively. A 5V PMOS with smaller channel length (0.40) is also available for applications |
| that can tolerate higher leakage current (< 10nA/um at 25C). |
| |
| Marking layer V5_Xtor is used to define 5V CMOS area. V5_Xtor must enclose 5V devices. Sub-nominal 5V PMOS is |
| identified with two marking layers, 5V_XTOR and MOS_MK_TYPE1. |
| |
| .. csv-table:: POLY2 |
| :file: tables_clear/7.7_POLY2.csv |
| :widths: 100, 200 , 300 |
| |
| Parasitic capacitance needs to be considered when adding dummy poly2. Customer has the option to use |
| GLOBALFOUNDRIESs dummy poly2 generation rule. In this case, customer needs to mark out areas of circuit which |
| are sensitive to parasitic capacitance and do not want dummy poly2 fill generated. Customer need to separate circuit |
| Metal1 and Metal2 from dummy metal in order that dummy poly2 can be generated beneath dummy metal. Refer to 4.1 |
| for layer name |
| |
| .. image:: images/POLY2.png |
| :width: 800 |
| :align: center |
| :alt: POLY2 |
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