BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs

################################################################################################
# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
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# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
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#================================
# ---- Varactor DERIVATIONS ----
#================================

logger.info('Starting VARACTOR DERIVATIONS')

#=========================
# --- VARACTOR EXCLUDE ---
#=========================

var_exclude = lvpwell.join(resistor).join(esd)
                     .join(sab).join(fusetop).join(tanres)
                     .join(dni).join(pwhv).join(fusewindow_d)
                     .join(polyfuse).join(schottky_diode).join(piscap)
                     .join(zener).join(res_mk).join(diode_mk)
                     .join(v5_xtor).join(drc_bjt).join(nat)
                     .join(fhres).join(mos_cap_mk).join(tanres_mk)
                     .join(tanres_l_mk).join(mvsd).join(mvpsd)
                     .join(elmd_mk).join(elmd2_mk).join(lvs_source)
                     .join(mk_35v).join(well_diode_mk).join(esd_hbm_mk)
                     .join(mos_mk_type1).join(swfet_mk).join(mom_mk)
                     .join(mom_m1_mk).join(mom_m2_mk).join(mom_m3_mk)
                     .join(mom_m4_mk).join(mom_m5_mk).join(hvnddd)
                     .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)

pcomp_nw_var = pcomp.and(nwell).and(lvs_rf).not(poly2).not(var_exclude)
ngate_nw_var = nplus.and(tgate).and(nwell).and(lvs_rf).not(var_exclude)

pcomp_nw_var_lv = pcomp_nw_var.not(dualgate2_d)
pcomp_nw_var_mv = pcomp_nw_var.and(dualgate2_d)

ngate_nw_var_lv = ngate_nw_var.not(dualgate2_d)
ngate_nw_var_mv = ngate_nw_var.and(dualgate2_d)

#========================
# --- PN 1P8 VARACTOR ---
#========================

# cap_var_pd2nw_01v8: Model for 1.8V Scalable PN-varactor (outside DNWELL) [pn_varactor_1p8]
cap_var_pd2nw_01v8_terminal_p = pcomp_nw_var_lv.not(dnwell)

# cap_var_pd2nw_01v8_dn: Model for 1.8V Scalable PN-varactor (inside DNWELL) [pn_varactor_1p8_dw]
cap_var_pd2nw_01v8_dn_terminal_p = pcomp_nw_var_lv.and(dnwell)

#========================
# --- PN 6P0 VARACTOR ---
#========================

# cap_var_pd2nw_06v0: Model for 6V Scalable PN-varactor (outside DNWELL) [pn_varactor_6p0]
cap_var_pd2nw_06v0_terminal_p = pcomp_nw_var_mv.not(dnwell)

# cap_var_pd2nw_06v0_dn: Model for 6V Scalable PN-varactor (inside DNWELL) [pn_varactor_6p0_dw]
cap_var_pd2nw_06v0_dn_terminal_p = pcomp_nw_var_mv.and(dnwell)

#=========================
# --- MOS 1P8 VARACTOR ---
#=========================

# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
cap_var_fet_01v8_gate = ngate_nw_var_lv.not(dnwell)

# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
cap_var_fet_01v8_dn_gate = ngate_nw_var_lv.and(dnwell)

#=========================
# --- MOS 6P0 VARACTOR ---
#=========================

# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
cap_var_fet_06v0_gate = ngate_nw_var_mv.not(dnwell)

# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
cap_var_fet_06v0_dn_gate = ngate_nw_var_mv.and(dnwell)