docs/ULL/physical_verification/design_manual/drm_07_3.rst

7.3 LV/MV PWELL (LVPWELL)
=================================

This drawn layer is defined for LV & MV NMOS body . If this layer is used without DNWELL (outside DNWELL), the
body of all those transistors will by default be connected to P-substrate potential.

**(A)LVPWELL inside DNWELL**

 .. csv-table:: LVPWELLA
    :file: tables_clear/7.3_A_LVPWELL.csv
    :widths: 100, 700 , 200,200

* This note is a layout guide for customer and this rule can be detected by ERC, not by DRC

.. image:: images/LVPWELLA.png
    :width: 800
    :align: center
    :alt: LVPWELLA


**(B)LVPWELL outside DNWELL**

This part is to define LV & MV NMOS transistor outside DNWELL. If LV_PWELL is designed as a resistor,
then it is not allowed to be placed outside DNWELL. Also it is to be noted that all LVPWELL outside
DNWELL will be by default at P-substrate potential

 .. csv-table:: LVPWELLB
    :file: tables_clear/7.3_B_LVPWELL.csv
    :widths: 100, 200 , 300

.. image:: images/LVPWELLB.png
    :width: 800
    :align: center
    :alt: LVPWELLB