| 7.2 DNWELL |
| ================================= |
| |
| This layer is defined to put 1.8/6V CMOS devices inside deep Nwell, for better isolation from substrate noise. For |
| 1.8V/6V/30V LDMOS process it is also used as the body of LDPMOS. Designer should make sure Nwell-taps for MV |
| area can only be connected to MV VDD & that for LV can only be connected to LV VDD. |
| |
| |
| .. csv-table:: DNWELL |
| :file: tables_clear/7.2_DNWELL.csv |
| :widths: 100, 200 , 300 |
| |
| Note: 1.8V, 3.3V & 5/6.0V transistors are not allowed in the same DNWELL (Refer to 7.6 DV2 rule). It |
| is a layout Guide for Customer. |
| |
| Note: As the whole LV & MV structures lies in deep Nwell (N-type Sub), Nwell-taps for MV area can |
| only be connected to MV VDD & that for LV can only be connected to LV VDD. (It is a layout Guide for |
| Customer) |
| |
| .. image:: images/DNWELL.png |
| :width: 800 |
| :align: center |
| :alt: DNWELL |
