docs/ULL/physical_verification/design_manual/drm_02.rst

2.0 Scope
=========

2.1 This document covers rules from Deep Nwell layer to passivation layer and scribe line layout.
    Device parameters, device models and process flow are available in separate documents.

2.2 This document also provides information on drawn layer definition, generated layer rules and mask
    layer numbers.

2.3 The dimensions stated in this document refer to the minimum allowed geometry or the window of
    allowed geometry. Deviations from these rules have to be approved by Globalfoundries.

2.4 Refer to YI-000-XX010 for the terminology used in Globalfoundries design rule specifications

2.5 Two terms used in this document have the following specific meanings:

2.5.1 Design Rules (“Rules” or “Layout Rules”) specify layout dimensions that meet the Process and
      Electrical Parameter Specifications. Rules are implemented in the Design Rule Check (DRC)
      runsets. Prior to design data submission using the Globalfoundries Foundry Service Request
      Specification (CX-008) procedure, the design must pass all DRC tests. Rule violations must be
      waived through the Design Rule (DR) Waiver Request Procedure (YI-000) before design is
      accepted for tapeout.

2.5.2 Design Guidelines (“Guidelines” or “Layout Guidelines”) are provided on an “as is” basis,
      without warranty of any kind, express or implied, to assist the reader in designing circuits for
      improved manufacturability and reliability. Guidelines are neither implemented in DRC runsets
      nor reviewed in the Design Rule Waiver Request Procedure (YI-000).

2.6 Refer to the reference documents for information on mask sizing and alignment sequence
    (BiasTable), Optical Proximity Correction (OPC), Proprietary SRAM cells, and dummy COMP
    generation.

2.7 Use the table below for Process Identification on 0.9um, 2um & 3um Metal Top options:
 .. csv-table:: Process Identification
    :file: tables_clear/2.7_Process_Identification.csv
    :widths: 100, 200