docs/IC/physical_verification/design_manual/drm_04_2.rst

4.2. Generated Layer and Generation rules
=========================================

The following layers are generated from drawn layers through data manipulation and do not have to be
drawn by the designer.

 .. csv-table:: Generated layers
    :file: tables_clear/4.2_GENERATED_LAYER.csv
    :widths: 200, 800


.. note::

    1. Refer to spec YI-093-GR008 for details on the dummy active, poly and metal generation rule.

    2. Data polarity is reversed (see table 4.3). Union of Nwell with “NativeVt” is used only when Native-Vt NMOS is required. Otherwise, use NWELL.

    3. The layers will be generated for all tape outs unless there are strong reasons for not using GLOBALFOUNDRIES generation algorithms. If use of designer-supplied DTN, DTP, DHVN layers are necessary, GLOBALFOUNDRIES will perform DRC on these layers according to the following table and tape out these layers if no DRC violations are found.

    .. csv-table:: Iniline_table
        :file: tables_clear/4.2_inline_table_notes.csv
        :widths: 200, 200 ,400

    4. Remove non-digitized areas on field smaller than 1µm2

    5. NVT and PVT layers are used for ULP (Ultra Low Power) SRAM process only.

    6. For PIB to be processed in FAB2, PIB is (Pad@10.00@-5.00). For PIB to be processed in FAB6, PIB is (Pad@10.00@-10.00). Refer to 4.3 for data polarity.

    7. GLOBALFOUNFRIES reserves the right to add some “clean up” steps to improve process manufacturability