| 1.0 Purpose | |
| =========== | |
| This document provides topological layout rules to generate masks in a 0.18μm CMOS logic/analog | |
| salicide dual-gate-oxide technology operating at 1.8V/3.3V. The following options are available: | |
| * Salicide block mask to provide non-salicided diffused and poly regions | |
| * Thicker MtalTop | |
| * Polyimide layer passivation |