| RULE NO.,DESCRIPTION,LAYOUT RULE | |
| Layer ,Dualgate --- Dual Voltage, | |
| DV.1 ,Width,0.7 | |
| DV.2 ,Space,0.44 | |
| DV.3,Extension beyond active,0.24 | |
| DV.4,Space to unrelated active,0.24 | |
| DV.5,Space from Dualgate on active to 1.8V transistor gate sharing the same active,0.4 | |
| DV.6,Overlap of 3.3V transistor gate,0.4 |