docs/IC/physical_verification/design_manual/drm_02.rst

2.0 Scope
=========

2.1 This document covers rules from Nwell layer to passivation layer and scribe line layout.
    Device parameters, device models and process flow are available in separate documents.

2.2 This document also provides information on drawn layer definition, generated layer rules and mask layer numbers.

2.3 The dimensions stated in this document refer to the minimum allowed geometry or the window of allowed geometry. Deviations from these rules have to be approved by GLOBALFOUNDRIES.

2.4 Refer to YI-000-XX010 for the terminology used in GLOBALFOUNDRIES design rule specifications.

2.5 Two terms used in this document have the following specific meaning:
   - Design Rules (“Rules” or “Layout Rules”) specify layout dimensions that meet the Process and Electrical Parameter Specifications. Rules are implemented in the Design Rule Check (DRC) runsets. Prior to design data submission using the GLOBALFOUNDRIES Foundry Service Request Specification (CX-008) procedure, the design must pass all DRC tests. Rule violations must be waived through the Design Rule (DR) Waiver Request Procedure (YI-000) before design is accepted for tapeout.
   - Design Guidelines (“Guidelines” or “Layout Guidelines”) are provided on an “asis” basis, without warranty of any kind, express or implied, to assist the reader in designing circuits for improved manufacturability and reliability. Guidelines are neither implemented in DRC runsets nor reviewed in the Design Rule Waiver Request Procedure (YI-000).

2.6 Use the table below for processing of various metal-level options

Metal-level options for process with top via size 0.26 um:

 .. csv-table::
    :file: tables_clear/2.6_table_0.26.csv
    :widths: 100, 600

Metal-level options for process with top via size 0.36 um:

 .. csv-table::
    :file: tables_clear/2.6_table_0.36.csv
    :widths: 100, 600

.. Note::
   “*” 1. 0.26um Top Via is available for 0.18um GLOBALFOUNDRIES Baseline (CB) only;
       0.36um Top Via is available for 0.18um Industry Baseline (IB) and 0.18um Industry
       Compatible (IC) only;
       Process ID to differentiate 0.18um CB, IB, IC process:
       PID: A-BCDEF-GHI-JKLMNO-PQR-STU, where S is
       0** - 0.18um GLOBALFOUNDRIES Baseline (CB)
       T** - 0.18um Industry Baseline (IB)
       B** - 0.18um Industry Compatible (IC)

2.7 Refer to the reference documents for information on mask sizing and alignment sequence
(Bias Table), Optical Proximity Correction (OPC), Proprietary SRAM cells, and dummy
active generation.