docs/BCDLite/physical_verification/design_manual/tables_clear/7.7_POLY2.csv

"RULE
NO.",DESCRIPTION ,D/R,D/R,D/R,D/R
,,LV,"MV =5V
(V5_Xtor
enclosed)",MV=6V,"MV=5V
(Sub
nominal
PMOS)"
Layer ,PL --- Poly2,,,,
PL.1 ,Min. Interconnect width outside PLFUSE, 0.18 ,0.2, 0.2, 0.2
PL.1a, "Min. Interconnect width under PLFUSE [regardless of
LV or MV]",0.18,0.18,0.18,0.18
PL.2a ,Min. Gate width (Channel length) ,0.18 ,0.5 ,0.6 ,0.40
PL.2b ,Gate width for OTP cell area (identified by OTP_MK) ,NA ,NA ,0.45, NA
PL.3a ,"Min. Poly2 Space  on COMP
                                   on Field","0.25
0.25","0.4
0.25","0.4
0.25","0.4
0.25"
G.PL.3b ,"Min. Poly2 space on COMP for low active sheet
resistivity (guideline)",0.38, 0.4, 0.4, 0.4
PL.4 ,"Min. Poly2 Extension beyond COMP to form Poly2
end cap",0.22, 0.22 ,0.22, 0.22
PL.5a ,"Min. Poly2 on field space to COMP [Unrelated]Min.
Poly2 on field space to guard ring",0.10, 0.3 ,0.3 ,0.3
PL.5b ,"Min. Poly2 on field space to COMP [Related]" ,0.10, 0.3 ,0.3, 0.3
PL.6 ,Poly2 Gate with 90° bends on active are not allowed,,,,
PL.7 ,45 degree bend Gate width for NMOS and PMOS ,0.20 ,0.7 ,0.7 ,0.7
PL.8 ,"Poly2 coverage over the entire die shall be > 14%.
Dummy poly2 lines must be added to meet the
minimum poly2 density requirement.1",,,,
PL.10 ,"Minimum DNWELL enclose Poly2 (in LV & MV
Area)",0.5, 0.5, 0.5 ,0.5
PL.11 ,"Poly2 inter-connect connecting LV and MV areas
(area inside and outside DV2_D) are not allowed.
They shall be done though metal lines only.",,,,
PL.12a,V5_Xtor enclose 5V Comp,NA,0,NA,0
PL.12b,MOS_MK_TYPE1 enclose subnominal 5V Comp,NA,NA,NA,0
G.PL.13 ,Maximum Poly2 current density ,1mA/um,1mA/um,1mA/um,1mA/um