blob: 7b9a263c894ef42db1ee482c649a40ff91b6ee1f [file] [log] [blame]
RULE NO. ,DESCRIPTION ,D/R,D/R
,,LV,MV
Layer, NW=Nwell,,
NW.1a ,"Min Nwell width (This is only for litho purpose on the generated
area)",0.86 ,0.86
NW.1b ,Min width if used as a resistor(outside DNWELL only) ,2.0 ,2.0
NW.2a ,"Min. Nwell Space outside DNWELL [Same Potential]
Merge if the space is less (This rule is just applicable for Nwell
outside DNWELL)",0.6 ,0.74
NW.2b ,"Min. Nwell Space outside DNWELL [Diff Potential]
(Note: By default all Nwells inside DNWELL will be at the same
potential.)",1.4 ,1.7
NW.3 ,Min. Nwell to DNWELL space ,3.1 ,3.1
NW.4 ,Min. Nwell to LVPWELL space ,0 ,0
NW.5 ,Min. DNWELL enclose Nwell ,0.5 ,0.5
NW.6 ,Nwell resistors can only exist outside DNWELL,,