docs/BCDLite/physical_verification/design_manual/tables_clear/7.11_ESD.csv

RULE NO., DESCRIPTION ,LAYOUT RULE
Layer ,ESD --- ESD Implant,
ESD.1 ,Min. ESD width ,0.60
ESD.2 ,"Min. ESD space
(Merge if the space is less than 0.6um)",0.60
ESD.3a ,Min. ESD space to NCOMP ,0.60
ESD.3b ,Min/max space to a butted PCOMP ,0.00
ESD.4a ,Min. ESD extend beyond NCOMP ,0.24
ESD.4b ,Min. ESD overlap NCOMP ,0.45
ESD.5a ,Min. ESD area ,0.49 μm2
ESD.5b ,Min. ESD hole ,0.49 μm2
ESD.6 ,Min. ESD extend beyond Poly2 ,0.45
ESD.7 ,No ESD implant inside PCOMP
ESD.8 ,Min. ESD space to Nplus/Pplus ,0.30
ESD.PL, Min. gate length of MV gate NMOS* ,0.80
ESD.9 ,"ESD implant layer must be enclosed by DV2_D layer (as
ESD implant option is only for MV devices)",
ESD.10 ,"LVS_IO shall be drawn covering I/O MOS active area by
minimum enclosure except under ESD_HBM_MK layer",0