docs/BCDLite/physical_verification/design_manual/tables_clear/12_Metalslotting.csv

RULE NO.,DESCRIPTION,LAYOUT RULE
MSLOT.1,Maximum metal width without slotting,30
MSLOT.2,Minimum slot width(slot mark layers) ,2
MSLOT.3,"Slot length(slot mark layers)
           a. Minimum
           b. Maximum","
10
250"
MSLOT.3,"Slot Space(slot mark layers)
           a. Minimum
           b. Maximum","
10
30"
MSLOT.5,Minimum slot (slot mark layers) to metal edge spacing,10
MSLOT.6,For multiple slots that spans the metal width, slots should be staggered.
MSLOT.7,Minimum space from via-n to metal-n slot ,0.2
MSLOT.8,Minimum space from via-(n-1) / contact to metal-n slot ,0.2
MSLOT.9,NO slotting allowed for the following cases:,
,"
(a) Top Metal or METAL_SHIELD area directly under the Pad
(b) MIM bottom plate directly under FuseTop (For MIM option-A process).
MIM bottom plate directly under FuseTop (For MIM option-B process).
Bottom plate directly under FuseTop (For TaN resistor option-A process).
Bottom plate directly under TANRES (For TaN resistor option-B
process).
(c) Without metal shielding, Top Metal1 directly under FuseWindow_D
With metal shielding, Top Metal1 and Top Metal-12 directly under
FuseWindow_D
(d) Metal3 slots are not allowed to interact with via2 in FuseTop area (For
MIM option-A process).
MetalTop slots are not allowed to interact with top via in FuseTop area
(For MIM option-B process).
Metaln slots are not allowed to interact with Vian-1 in FuseTop area (For
TaN resistor option-A process).
METAL_SHIELD slot is not allowed to interact with
METAL_SHIELD_VIA in TANRES area (For TaN resistor option-B
process).",
,"(e) Top Metal or METAL_SHIELD area directly under UMB layers (except
for UMB used for WLP cu_PPI process)
Minimum distance to these layers ",5.0
MSLOT.10,"slot mark layer on the metal hole (same metal level
e.g. Metal1_Slot on the Metal1 hole) are not allowed",