docs/BCDLite/physical_verification/design_manual/tables_clear/10.0_SRAM.csv

RULE NO., DESCRIPTION LAYOUT,RULE
,"For use in SRAM strap cells and array edge cells as well as SRAM core
cells.",
S.DF.1a ,Minimum COMP width inside SramCore AND OPC_drc marking layers, 0.02
S.DF.3a.i,Space between COMP inside SRAM,0.26
S.DF.3a.ii,"Space between COMP (inside SramCore making) to COMP (outside
SramCore marking).",0.28
S.DF.3a.iii,Space between COMP inside SramCore AND OPC_drc marking layers,0.02
S.DF.4c ,Nwell enclose PCOMP inside Nwell ,0.25
S.DF.6 ,"Extension beyond gate or source/drain overhang inside SramCore AND
OPC_drc marking layers",0.03
S.DF.7 ,Space from LVPWELL to PCOMP inside DNWELL ,0.25
S.DF.8 ,LVPWELL enclose NCOMP inside LVPWELL ,0.355
S.PL.1.i,Poly2 interconnect width in parallel direction,0.18
S.PL.1.ii,"Inside SramCore AND OPC_drc marking layers, Poly2 interconnect width
in parallel direction",0.05
S.PL.3a.ii,Poly2 to Poly2 space on field (Poly2 width < 0.5),0.19
S.PL.3a.iii,"Poly2 (inside SramCore making) to Poly2 (outside SramCore making) space
on field",0.25
S.PL.3a.iv,"Inside SramCore AND OPC_drc marking layers, Poly2 to Poly2 space on
field (Poly2 width < 0.5)",0.03
S.PL.4,Poly2 end cap (width parallel to COMP),0.22
S.PL.4.i,Min width of chopped end cap (parallel to channel length direction),0.10
S.PL.4.ii,"Inside SramCore AND OPC_drc marking layers, Poly2 end cap (width
parallel to COMP)",0.03
S.PL.5b ,Space from field Poly2 to related COMP ,0.04
S.NP.12 ,"Overlap with P-channel Poly2 gate extension is forbidden within 0.25um of
P-Channel gate",
S.CO.1 ,Min contact width in parallel direction ,0.21
S.CO.1.i ,Min. contact area (μm2) ,0.0483
S.CO.1.ii ,Max. contact area (μm2), 0.0638
S.CO.2a ,Contact to Contact space inside SramCore marking 0,.21
S.CO.3 ,Poly2 enclose contact ,0.00
S.CO.3.i,"If Poly2 enclose contact by < 0.06μm on one side, adjacent Poly2 edges’
enclosure",0.06
S.CO.3.ii,"Inside SramCore AND OPC_drc marking layers If Poly2 enclose contact by
< 0.06μm on one side adjacent Poly2 edges enclosure",0.01
S.CO.4 ,COMP enclose contact ,0.00
S.CO.4.i,"If COMP enclose contact by < 0.06μm on one side adjacent COMP edges’
enclosure",0.06
S.CO.4.ii,"Inside SramCore AND OPC_drc marking layers If COMP enclose contact
by < 0.06μm on one side adjacent COMP edges’ enclosure",0.01
S.CO.6,Metal1 enclose contact,0.00
S.CO.6.i,Metal 1 (< 0.34μm) enclose contact at end-of-line side,0.00
S.CO.6.ii,"If metal 1 enclose contact by < 0.04μm on one side adjacent metal1 edges
enclosure",0.00
G.S.CO.6.iii,"Minimum metal 1 enclose contact on all sides for minimum contact resistance
variation (guideline)",0.00
S.CO.7,Space from COMP contact to Poly2,0.12
S.CO.7.i,"
Inside SramCore AND OPC_drc marking layers Space from COMP contact
to Poly2",0.07
S.CO.8,Space from Poly2 contact to COMP,0.13
S.CO.8.i,"Inside SramCore AND OPC_drc marking layers Space from Poly2 contact
to COMP",0.07
S.M1.1,Metal1 width in parallel direction,0.21
S.M1.1.i,"Inside SramCore AND OPC_drc marking layers Metal1 width in parallel
direction",0.035
S.M1.2a.i,Metal1 space in parallel direction,0.20
S.M1.2a.ii,"Metal1 (inside SramCore marking) to Metal1 (outside SramCore marking)
space in parallel direction",0.23
S.M1.2a.iii,"Metal1 (inside SramCore marking) to wide Metal1 (outside SramCore
marking length & width >10um) space in parallel direction",0.30
S.M1.2a.iv,"Inside SramCore AND OPC_drc marking layers Metal1 space in parallel
direction",0.13
S.M2.2a.i,"Metal2 (inside SramCore marking) to Metal2 (outside SramCore marking)
space in parallel direction",0.28
S.M2.3,Minimum Metal2 Area,0.12um2
S.V1.3,Metal1 enclose VIA1,0.0
S.V1.3.i,Metal1 (< 0.34μm) enclose contact at end-of-line side,0.0
S.V1.3.ii,"If Metal1 enclose via-n by < 0.04μm on one side adjacent metal1 edges
enclosure",0.0
G.S.V1.3.iii,"Minimum metal1 enclose via1 on all sides for minimum via1resistance
variation (guideline)",0.0