docs/BCDLite/physical_verification/design_manual/drm_07_2.rst

7.2 DNWELL
=================================

This layer is defined to put 1.8/6V CMOS devices inside deep Nwell, for better isolation from substrate noise. For
1.8V/6V/30V LDMOS process it is also used as the body of LDPMOS. Designer should make sure Nwell-taps for MV
area can only be connected to MV VDD & that for LV can only be connected to LV VDD.


 .. csv-table:: DNWELL
    :file: tables_clear/7.2_DNWELL.csv
    :widths: 100, 200 , 300

.. image:: images/DNWELL.png
    :width: 800
    :align: center
    :alt: DNWELL

7.2.1 Well Voltage Marking Layers
=================================
Well Voltage Marking layers can be used in applications where the ‘DNwell’ or ‘Nwell outside DNwell’ need to be
biased at a higher voltage (>14V & <30V). Four optional well voltage marking layers are available.

 .. csv-table:: Well_V_marking_layer1
    :file: tables_clear/7.2.1_Well_V_marking_layers.csv
    :widths: 100, 200 , 300

Following isolation rules are checked for ‘DNWELL’ / ‘Nwell outside DNWELL’ enclosed by respective well
voltage marking layers (Exclude the spacing rule check when MVSD/MVPSD form the drain extension of multi-
finger LDMOS):

 .. csv-table:: Well_V_marking_layer2
    :file: tables_clear/7.2.1_Well_V_marking_layers2.csv
    :widths: 100, 200 , 300