docs/BCDLite/physical_verification/design_manual/drm_04_1.rst

4.1 Drawn layer definition and abbreviation
===========================================


 .. csv-table:: Drawn layers
    :file: tables_clear/4.1_table_layerdiff.csv
    :widths: 100, 200, 400, 100, 100

 .. csv-table:: Drawn layers
    :file: tables_clear/4.1_table_layerdiff_cont.csv
    :widths: 100, 200, 400, 100, 100


.. note::

    1. Used in the dummy COMP, dummy poly2 & dummy metal generation algorithm (YI-141-GR010).

    2. See section 11 for complete list of analog-specific layers and masks.

    3. Based on the spec YI-103-SC001/YI-141-SC001.

    4. Metal1_Dummy and Metal2_Dummy are dummy fills for Metal1 and Metal2. Data type is used to
       differentiate between circuits and dummy Metal1 and Metal2. This separation is to facilitate generation
       of dummy poly2. Dummy poly2 needs to be generated when prime die poly2 density falls below poly2
       density requirement. Circuit and metal dummy fill will be “OR” after dummy poly2 is generated (where
       applicable).

    5. Metal3_Dummy, Metal4_Dummy, Metal5_Dummy and MetalTop_Dummy are metal dummy fills.
       These are separated from circuit metal by using different data type.
    6. Used for all logic, analog and RF processes.

    7. ESD is optional mask to provide ESD implant for MV I/Os.

    8. CAP_MK is used to define the bottom plate of the MIM Capacitor for DRC purpose. It will also be
       used for LVS purposes. Refer to EDA-CAD-000-GS003 (LVS Recognition and Extraction Guideline)
       for more information and guidelines on LVS marking layers.

    9. DRC_BJT is used for DRC purpose to avoid PL.6 and DF.3C rule.

    10. V5_XTOR is used as a marking layer to define 5V MV CMOS transistor. Minimum channel length for
        5V device is 0.5um while 6V device minimum channel length is 0.6um. Whenever transistor is
        enclosed by V5_Xtor layer, the minimum channel length is 0.5um.

    11. These layers are only for label drawing and not supposed to be part of the active circuits. Also these
        layers will be used in DRC and LVS for any wrong placement of label check.

    12. 35V_MK is used as a marking layer to define 35V LDMOS transistor.
    
    13. LVS_35V is used as LVS marking layer to define two finger 35V LDMOS unit device