ULL/klayout/drc/rule_decks/dualgate_2.drc

################################################################################################
# Copyright 2022 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the 'License');
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an 'AS IS' BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################################


if FEOL

    #================================================
    #-------------------DUALGATE_2-------------------
    #================================================ 

    # Rule DV2.1: Min. DV2 enclose DNWELL. is 0.5µm
    logger.info('Executing rule DV2.1')
    dv21_l1 = dualgate_2.enclosing(dnwell, 0.5.um, euclidian).polygons(0.001)
    dv21_l2 = dnwell.not_outside(dualgate_2).not(dualgate_2)
    dv21_l  = dv21_l1.or(dv21_l2)
    dv21_l.output('DV2.1', 'DV2.1 : Min. Dualgate enclose DNWELL. : 0.5µm')
    dv21_l1.forget
    dv21_l2.forget
    dv21_l.forget

    # Rule DV2.2: Min. DV2 Space. Merge if Space is less than this design rule. is 0.44µm
    logger.info('Executing rule DV2.2')
    dv22_l1  = dualgate_2.space(0.44.um, euclidian).polygons(0.001)
    dv22_l1.output('DV2.2', 'DV2.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm')
    dv22_l1.forget 

    # Rule DV2.3: Min. DV2 to COMP space [unrelated]. is 0.24µm
    logger.info('Executing rule DV2.3')
    dv23_l1  = dualgate_2.separation(comp.outside(dualgate_2), 0.24.um, euclidian).polygons(0.001)
    dv23_l1.output('DV2.3', 'DV2.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm')
    dv23_l1.forget 

    # rule DV2.4 is not a DRC check

    # Rule DV2.5: Min. DV2 width. is 0.7µm
    logger.info('Executing rule DV2.5')
    dv25_l1  = dualgate_2.width(0.7.um, euclidian).polygons(0.001)
    dv25_l1.output('DV2.5', 'DV2.5 : Min. Dualgate width. : 0.7µm')
    dv25_l1.forget 

    # Rule DV2.6: Min. DV2 enclose COMP is 0.24µm
    logger.info('Executing rule DV2.6')
    dv26_l1 = dualgate_2.enclosing(comp, 0.24.um, euclidian).polygons(0.001)
    dv26_l2 = comp.not_outside(dualgate_2).not(dualgate_2)
    dv26_l  = dv26_l1.or(dv26_l2)
    dv26_l.output('DV2.6', 'DV2.6 : Min. Dualgate enclose COMP : 0.24µm')
    dv26_l1.forget
    dv26_l2.forget
    dv26_l.forget

    # Rule DV2.7: COMP can not be partially overlapped by DV2.
    logger.info('Executing rule DV2.7')
    dv27_l1 = dualgate_2.not_outside(comp).not(dualgate_2.covering(comp))
    dv27_l1.output('DV2.7', 'DV2.7 : COMP can not be partially overlapped by DV2.')
    dv27_l1.forget


    # Rule DV2.8: Min DV2 Overlap of MV (5/6V) transistor gate is 0.4µm
    logger.info('Executing rule DV2.8')
    dv28_l1 = dualgate_2.enclosing(tgate, 0.4.um, euclidian).polygons(0.001)
    dv28_l2 = tgate.not_outside(dualgate_2).not(dualgate_2)
    dv28_l  = dv28_l1.or(dv28_l2)
    dv28_l.output('DV2.8', 'DV2.8 : Min Dualgate Overlap of MV (5/6V) transistor gate : 0.4µm')
    dv28_l1.forget
    dv28_l2.forget
    dv28_l.forget

    # Rule DV2.9 : Min Space to Dualgate is 1.0µm 
    logger.info('Executing rule DV2.9')
    dv29_l1 = dualgate_2.separation(dualgate,1.0.um).polygons(0.001)
    dv29_l1.output('DV2.9','DV2.9 : Min Space to Dualgate is 1.0µm')
    dv29_l1.forget

    # Rule DV2.10: 1.8V,3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.
    logger.info('Executing rule DV2.10')
    dv210_l1 = nwell.covering(pgate.and(dualgate_2)).covering(pgate.not_inside(v5_xtor).not_inside(dualgate_2).not_inside(dualgate))
    dv210_l1.output('DV2.10', 'DV2.10 : 1.8V,3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.')
    dv210_l1.forget

end #FEOL