BCDLite/klayout/lvs/rule_decks/mos_derivations.lvs

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# Copyright 2022 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
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#==================================
# ------ MOSFET DERIVATIONS -------
#==================================

logger.info('Starting MOSFET DERIVATIONS')

# general derivations used in MOS devices
nsd_sab = nsd.and(sab)
mos_exclude_layers = resistor.or(esd).or(pwhv).or(fusewindow_d).or(polyfuse)
                            .or(schottky_diode).or(zener).or(piscap).or(res_mk)
                            .or(fhres).or(mos_cap_mk).or(mvsd).or(mvpsd)
                            .or(lvs_rf).or(lvs_source).or(mk_35v)
                            .or(lvs_35v).or(esd_hbm_mk).or(hvpolyrs)
                            .or(swfet_mk).or(hvnddd).or(hvpddd)

# =======================
# ---- LV MOS Devices ----
# =======================
logger.info('Starting LV MOS layers DERIVATIONS')

# LV NMOS transistor outside DNWELL
nmos_1p8_g = ngate.not(dnwell).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor).not(mos_mk_type1)
                .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not_interacting(dni)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk)

# LV NMOS transistor inside DNWELL
nmos_1p8_dw_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor)
                    .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# LV NAT NMOS transistor outside DNWELL
nmos_1p8_nat_g = ngate.not(dnwell).and(nat).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor)
                .not(mos_exclude_layers).not(sab).not(nwell).not(lvpwell).not(mos_mk_type1)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# LV NMOS with drain sab outside DNWELL
nmos_1p8_sab_g = ngate.not(dnwell).interacting(elmd2_mk).interacting(sab).not(dualgate2_d)
                    .not(mos_exclude_layers).not(nwell).not(nat).not(v5_xtor).not(mos_mk_type1)
                    .not_interacting(elmd_mk).not(ldmos_xtor).not_interacting(dni)

# LV NMOS with drain sab inside DNWELL
nmos_1p8_dw_sab_g = ngate.and(dnwell).interacting(elmd2_mk).interacting(sab).and(lvpwell)
                    .not(mos_exclude_layers).not(nwell).not(nat).not(v5_xtor).not(dualgate2_d)
                    .not_interacting(elmd_mk).not(mos_mk_type1).not(ldmos_xtor).not_interacting(dni)

# LV PMOS transistor outside DNWELL
pmos_1p8_g = pgate.not(dnwell).and(nwell).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor)
                .not(mos_exclude_layers).not(sab).not(nat).not(lvpwell).not(mos_mk_type1)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# LV PMOS transistor inside DNWELL
pmos_1p8_dw_g = pgate.and(dnwell).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor).not(lvpwell)
                .not(mos_exclude_layers).not(sab).not(nat).not(mos_mk_type1).not_interacting(dni)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk)


# ========================
# ---- MV MOS Devices ----
# ========================
logger.info('Starting MV MOS layers DERIVATIONS')

# 5V NMOS transistor outside DNWELL
nmos_5p0_g = ngate.not(dnwell).and(v5_xtor).and(dualgate2_d).not(ldmos_xtor).not(mos_mk_type1)
                .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not_interacting(dni)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk)

# 5V NMOS transistor inside DNWELL
nmos_5p0_dw_g = ngate.and(dnwell).and(lvpwell).and(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
                    .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 5V PMOS transistor outside DNWELL
pmos_5p0_g = pgate.not(dnwell).and(nwell).and(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
                .not(mos_exclude_layers).not(sab).not(nat).not(lvpwell).not(mos_mk_type1)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 5V PMOS transistor inside DNWELL
pmos_5p0_dw_g = pgate.and(dnwell).and(v5_xtor).and(dualgate2_d).not(ldmos_xtor).not(lvpwell)
                .not(mos_exclude_layers).not(sab).not(nat).not(mos_mk_type1)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 6V NMOS transistor outside DNWELL
nmos_6p0_g = ngate.not(dnwell).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor).not(mos_mk_type1)
                .not(mos_exclude_layers).not(sab).not(nwell).not(nat)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 6V NMOS transistor inside DNWELL 
nmos_6p0_dw_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
                    .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 6V PMOS transistor outside DNWELL
pmos_6p0_g = pgate.not(dnwell).and(nwell).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
                .not(mos_exclude_layers).not(sab).not(nat).not(lvpwell).not(mos_mk_type1)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 6V PMOS transistor inside DNWELL
pmos_6p0_dw_g = pgate.and(dnwell).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor).not(lvpwell)
                    .not(mos_exclude_layers).not(sab).not(nat).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 6V NAT NMOS transistor outside DNWELL
nmos_6p0_nat_g = ngate.not(dnwell).and(nat).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
                    .not(mos_exclude_layers).not(sab).not(nwell).not(lvpwell).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 6V NAT PMOS transistor inside DNWELL
pmos_6p0_nat_dw_g = pgate.and(dnwell).not(v5_xtor).and(dualgate2_d).and(nat).not(ldmos_xtor)
                        .not(mos_exclude_layers).not(sab).not(lvpwell).not(mos_mk_type1)
                        .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)

# 6V Extended LDD NMOS
nmos_eldd_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).interacting(elmd_mk)
                .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
                .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)

# 6V DDD MV NMOS
nmos_ddd_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).interacting(dni)
                .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
                .not_interacting(elmd2_mk).not_interacting(elmd_mk).not(ldmos_xtor)

# 6V NMOS with drain sab outside DNWELL
nmos_6p0_sab_g = ngate.not(dnwell).not(nwell).not(v5_xtor).and(dualgate2_d).not_interacting(elmd_mk)
                    .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)

# 6V NMOS with drain sab inside DNWELL 
nmos_6p0_dw_sab_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).not_interacting(elmd_mk)
                    .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)

# 5V NMOS with drain sab outside DNWELL
nmos_5p0_sab_g = ngate.not(dnwell).not(nwell).and(v5_xtor).and(dualgate2_d).not_interacting(elmd_mk)
                    .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)

# 5V NMOS with drain sab inside DNWELL 
nmos_5p0_dw_sab_g = ngate.and(dnwell).and(lvpwell).and(v5_xtor).and(dualgate2_d).not_interacting(elmd_mk)
                    .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)
    
# 4.2V Hybrid NMOS inside DNWELL
nmos_4p2_dw_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).interacting(mos_mk_type4)
                    .interacting(mos_source_type1).not_interacting(dni).not_interacting(elmd_mk)
                    .not(mos_exclude_layers).not_interacting(sab).not(nwell).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not(ldmos_xtor).not(nat)
                    
# 4.2V Hybrid PMOS inside DNWELL
pmos_4p2_dw_g = pgate.and(dnwell).not(v5_xtor).and(dualgate2_d).interacting(mos_mk_type4)
                    .interacting(mos_source_type1).not_interacting(dni).not_interacting(elmd_mk)
                    .not(mos_exclude_layers).not_interacting(sab).not(nwell).not(mos_mk_type1)
                    .not_interacting(elmd2_mk).not(ldmos_xtor).not(nat)

# 4.2V Hybrid SAB NMOS inside DNWELL
nmos_4p2_dw_sab_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).interacting(mos_mk_type4)
                        .interacting(mos_source_type1).not_interacting(dni).not_interacting(elmd_mk)
                        .not(mos_exclude_layers).interacting(sab).not(nwell).not(mos_mk_type1)
                        .not_interacting(elmd2_mk).not(ldmos_xtor).not(nat)