ULL/klayout/lvs/rule_decks/diode_derivations.lvs

################################################################################################
# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################################

#================================
# ----- DIODE DERIVATIONS -------
#================================

logger.info('Starting DIODE DERIVATIONS')

#========================
# ---- DIODE EXCLUDE ----
#========================

diode_exclude = lvs_bjt.join(drc_bjt).join(sab).join(esd).join(resistor).join(fusetop).join(polyfuse)
.join(cap_mk).join(nat).join(fhres).join(fusewindow_d)
.join(piscap).join(mos_cap_mk).join(mim_l_mk).join(res_mk)

d_ncomp_lv = ncomp.not(nwell).not(v5_xtor).and(diode_mk).not(dv2)
d_pcomp_lv = pcomp.and(nwell).not(v5_xtor).and(diode_mk).not(dv2)

d_ncomp_mv = ncomp.not(nwell).not(v5_xtor).and(diode_mk).not(dualgate).and(dv2)
d_pcomp_mv = pcomp.and(nwell).not(v5_xtor).and(diode_mk).not(dualgate).and(dv2)

#================================
# ---- LV DIODE DERIVATIONS ----
#================================

# diode_np_1p8 (Model for 1.8V N+/Pwell diode outside DNWell)
diode_np_1p8_terminal_n = d_ncomp_lv.not(dnwell).not(dualgate)

# diode_np_1p8_dw (Model for 1.8V N+/Pwell diode inside DNWell)
diode_np_1p8_dw_terminal_n = d_ncomp_lv.and(dnwell).not(dualgate)

# diode_pn_1p8 (Model for 1.8V P+/Nwell diode outside DNWell)
diode_pn_1p8_terminal_p = d_pcomp_lv.not(dnwell).not(dualgate)

# diode_pn_1p8_dw (Model for 1.8V P+/Nwell diode inside DNWell)
diode_pn_1p8_dw_terminal_p = d_pcomp_lv.and(dnwell).not(dualgate)

# diode_np_3p3 (Model for 3.3V N+/Pwell diode outside DNwell)
diode_np_3p3_terminal_n = d_ncomp_lv.not(dnwell).and(dualgate)

# diode_np_3p3_dw (Model for 3.3V N+/Pwell diode inside DNwell)
diode_np_3p3_dw_terminal_n = d_ncomp_lv.and(dnwell).and(dualgate)

# diode_pn_3p3 (Model for 3.3V P+/Nwell diode outside DNwell)
diode_pn_3p3_terminal_p = d_pcomp_lv.not(dnwell).and(dualgate)

# diode_pn_3p3_dw (Model for 3.3V P+/Nwell diode inside DNwell)
diode_pn_3p3_dw_terminal_p = d_pcomp_lv.and(dnwell).and(dualgate)
          
#================================
# ---- MV DIODE DERIVATIONS ----
#================================

# diode_np_6p0 (Model for 6V N+/Pwell diode outside Dnwell)
diode_np_6p0_terminal_n = d_ncomp_mv.not(dnwell)

# diode_np_6p0_dw (Model for 6V N+/Pwell diode inside DNwell)
diode_np_6p0_dw_terminal_n = d_ncomp_mv.and(dnwell)

# diode_pn_6p0 (Model for 6V P+/Nwell diode outside DNwell)
diode_pn_6p0_terminal_p = d_pcomp_mv.not(dnwell)

# diode_pn_6p0_dw (Model for 6V P+/Nwell diode inside DNwell)
diode_pn_6p0_dw_terminal_p = d_pcomp_mv.and(dnwell)