docs/IC/physical_verification/design_manual/drm_05.rst

5.0 DFM (Design For Manufacturability) Guidelines
=================================================


1. Resolving common design rule violations in the pre-tapeout design review can minimize tapeout
cycletime. DRC runsets (YI-093-CC001, YI-093-HC001) are available from our
GLOBALFOUNDRIES EAM. Please read the disclaimers and notes in the runset specifications.
Should any discrepancy arise between this document and results from DRC runsets, the
specifications and rules in this document take precedence.

2. Relaxed designs with dimensions increased from baseline ground-rule minimums will generally
improve process and reliability yields. Minimum design dimensions should only be used to
decrease chip size or improve device performance.

3. Minimum lines and spaces increase circuit density. When circuit density is not limited by these
rules, increase the minimum line and space values by 10% to 20% as applicable during design
layout. This practice improves the product manufacturability, yields and performance by
reducing interconnect resistance and capacitance.

4. The minimum metal-overlap-of-contact and via rules are given to increase interconnect density.
Where interconnect is not limited by these rules, relax the metal-overlap-of-contact and via by
10%-20% as applicable during design layout. This will improve both manufacturing margins
and reliability.

5. Narrow polysilicon and diffusion lines are particularly susceptible to localized increases in sheet
resistance in a salicide process. In applications where DC voltage drops are critical, avoid using
narrow poly or diffusion lines.

6. Since thin-gate-oxide integrity is driven by random process defects, avoid using large gate oxide
areas as decoupling capacitors. Follow the antenna ratio rules to ensure reliable gate oxides.


7. Avoid long parallel routing of intra-layer metal lines. This practice reduces coupling
capacitance, improves circuit performance and suppresses cross-talk.

8. Use top-metal as power supply, ground, bus signal and global interconnect since it has the
lowest resistivity.

9. Subject to space availability, use redundant contacts and vias to provide design robustness
against interconnect high resistance and opens. Avoid using single contact for interlevel
connection unless absolutely necessary.
Place “multiple (≥2) plug” redundant contact or via connections for extremely isolated
locations, defined as having 25µm spacing to the nearest neighbor via or contact in the same
layer.
It is recommended to choose the larger top via size option when using thick top metal
(≥8KA AlCu). In addition, refer to section 14.4 to verify electromigration susceptibility.

10. Implementing poly and metal dummy pattern fill by designer is highly recommended when GDS
densities are below the minimum rules specified. Control of dummy fill and minimized impact
to critical path circuitry are then assured in layout. Our DRC runsets implement GDS pattern
density checks.

11. If customers choose to use their algorithms rather than GLOBALFOUNDRIES’s generation
algorithms in section 4.2 to generate implant layers (TN, TP, HVN), drawn implant layer rules
in section 7.13 to 7.15 must be applied during DRC.

12. As product labels are placed in the chip area and not in the scribe line, labels and logos must
obey the design rules in this manual so as to prevent impact to circuit functionality.
GLOBALFOUNDRIES does not provide logo block marking layer to suppress DRC on logos.