docs/IC/physical_verification/design_manual/drm_04_1.rst

4.1 Drawn layer definition and abbreviation
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The following layers are drawn directly on the layout system.

 .. csv-table:: Drawn layers
    :file: tables_clear/4.1_table_layerdiff.csv
    :widths: 150, 150,150,150,150,150

.. note::

    1. Used in the dummy active generation algorithm (YI-093-GR008).

    2. See section 11 for complete list of analog-specific layers and masks.

    3. Refer to YI-103-SC001for 0.18um SRAM cell designs.

    4. Metal1_Dummy and Meta2_Dummy are dummy fills for Metal1 and Metal2. Datatype is used to differentiate between circuit and dummy Metal1 and Metal2. This separation is to facilitate generation of dummy poly. Dummy poly needs to be generated when prime die poly density falls below poly density requirement. Circuit and metal dummy fill will be “OR” after dummy poly is generated (where applicable).

    5. Meta3_Dummy, Meta4_Dummy, Meta5_Dummy and MetalTop_Dummy are metal dummy fills. These are separated from circuit metal by using different data type.

    6. Used for both logical and analog/RF processes.ed in DRC and LVS for any wrong placement of label check.

    7. ESD is optional mask to provide ESD implant.

    8. LVS_CAP is used to define the bottom plate of the MIM Capacitor for DRC purpose. It will also be used for LVS purposes. Refer to EDA-CAD-000-GS003 (LVS Recognition and Extraction Guideline) for more information and guidelines on LVS marking layers.

    9. LVS_BJT is used for DRC purpose to avoid PL.6 rule.

    10. Used for alignment marking purpose for the database merging operation of black-box IPs,
        where Data type n is IP vendor specific.