docs/BCDLite/physical_verification/design_manual/drm_02.rst

2.0 Scope
=========

2.1 This document covers rules from Deep Nwell layer to passivation layer and scribe line layout.
Device parameters, device models and process flow are available in separate documents

2.2 This document also provides information on drawn layer definition, generated layer rules and mask
layer numbers.

2.2 The dimensions stated in this document refer to the minimum allowed geometry or the window of
allowed geometry. Deviations from these rules have to be approved by GLOBALFOUNDRIES.

2.4 Refer to YI-000-XX010 for the terminology used in GLOBALFOUNDRIES design rule specifications.

2.5 Two terms used in this document have the following specific meanings:

    2.5.1 Design Rules (“Rules” or “Layout Rules”) specify layout dimensions that meet the Process
          and Electrical Parameter Specifications. Rules are implemented in the Design Rule Check
          (DRC) runsets. Prior to design data submission using the GLOBALFOUNDRIES Foundry
          Service Request Specification (CX-008) procedure, the design must pass all DRC tests. Rule
          violations must be waived through the Design Rule (DR) Waiver Request Procedure (CX-020)
          before design is accepted for tapeout.
    2.5.2 Design Guidelines (“Guidelines” or “Layout Guidelines”) are provided on an “as is” basis,
          without warranty of any kind, express or implied, to assist the reader in designing circuits for
          improved manufacturability and reliability. Guidelines are neither implemented in DRC
          runsets nor reviewed in the Design Rule Waiver Request Procedure (CX-020). Design
          Guideline is identified by the initial letter of “G”, for “G.xxx” case, It is default turn-off in
          DRC runset. User has freedom to turn it on and to check if Guidelines are fulfilled. for
          “G_xxx” case, It is default turn-on in DRC run set.

2.6 Refer to the reference documents for information on mask sizing and alignment sequence (Bias Table),
    Optical Proximity Correction (OPC), Proprietary SRAM cells, and dummy COMP generation.

2.7 GLOBALFOUNDRIES does not own any responsibility for any devices (e.g. transistors, passive
    devices, NVM cells, fuse cell or others.) which are not offered by GLOBALFOUNDRIES PDK of this
    technology, irrespective of those devices passing or failing design rule check.

2.8 Use the table below for Process Identification on 0.9um & 3um MetalTop options:

 .. csv-table:: Mask layers
    :file: tables_clear/2.8_Procces_identification.csv
    :widths: 100, 200, 100

2.8 Use the table below for processing of various metal level options for Global Foundries INTERNAL
    REFERENCE ONLY (e.g. frame structure, scribeline monitoring structures, testchip layout etc.)

 .. csv-table:: levelsofmetal1
    :file: tables_clear/2.8_met_levels8_1.csv
    :widths: 100, 200

Use the table below for processing of various metal level options for DESIGN ACTIVITIES (e.g.
product/prototype design-in, libraries solutions, IPs solutions etc.)

 .. csv-table:: levelsofmetal2
    :file: tables_clear/2.8_met_levels8_2.csv
    :widths: 100, 200

2.9 Options for BEOL with METAL_SHIELD:
    2.9.1 BEOL metals and via include Metal1, Via1, Metal2, Via2, Metal3, Via3, Metal4, Via4,
          Metal5, Via5, MetalTop, METAL_SHIELD_VIA and METAL_SHIELD (The last metal layer
          is METAL_SHIELD). MetalTop thickness is 0.9um. METAL_SHIELD thickness is 0.9um or
          3.0um.

    2.9.2 BEOL metals and via include Metal1, Via1, Metal2, Via2, Metal3, Via3, Metal4, Via4, Metal5
          (Metal 5 must comply with MetalTop rule), METAL_SHIELD_VIA and METAL_SHIELD
          (The last metal layer is METAL_SHIELD). Metal5 thickness is 0.9um. METAL_SHIELD
          thickness is 0.9um or 3.0um.

    2.9.3 4LM + METAL_SHIELD and below BEOL options are prohibited.