ULL/klayout/lvs/rule_decks/mos_derivations.lvs

################################################################################################
# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################################

#==================================
# ------ MOSFET DERIVATIONS -------
#==================================

logger.info('Starting MOSFET DERIVATIONS')

#====================
# --- MOS EXCLUDE ---
#====================

mos_exclude = sab.join(esd).join(resistor)
                 .join(polyfuse).join(cap_mk).join(diode_mk)
                 .join(drc_bjt).join(lvs_bjt).join(fhres)
                 .join(fusewindow_d).join(fusetop).join(piscap)
                 .join(mos_cap_mk).join(mim_l_mk)


ngate_pw_base = ngate_pw.not(mos_exclude).not(nat)
ngate_pw_lv = ngate_pw_base.not(dv2).not(v5_xtor)
ngate_pw_mv = ngate_pw_base.and(dv2).not(dualgate)

ngate_dn_base = ngate_dn.not(nwell).not(mos_exclude).not(nat)
ngate_dn_lv = ngate_dn_base.not(dv2).not(v5_xtor)
ngate_dn_mv = ngate_dn_base.and(dv2).not(dualgate)

pgate_base = pgate.not(dnwell).not(mos_exclude).not(nat)
pgate_lv = pgate_base.not(dv2).not(v5_xtor)
pgate_mv = pgate_base.and(dv2).not(dualgate)

pgate_dn_base = pgate_dn.not(mos_exclude).not(nat)
pgate_dn_lv = pgate_dn_base.not(dv2).not(v5_xtor)
pgate_dn_mv = pgate_dn_base.and(dv2).not(dualgate)

ngate_nat_base = ngate.and(nat).not(mos_exclude)
ngate_nat_lv = ngate_nat_base.not(dv2).not(v5_xtor)
ngate_nat_mv = ngate_nat_base.and(dv2).not(dualgate)

#=================================
# ---- LV (1.8V) TRANSISTORS ----
#=================================

logger.info('Starting LV (1.8V) TRANSISTORS layers DERIVATIONS')

# nfet_01v8: Model for LV NMOS outside Dnwell [nmos_1p8]
ngate_1p8 = ngate_pw_lv.not(dualgate)

# nfet_01v8_dn: Model for LV NMOS Inside Dnwell [nmos_1p8 _dw]
ngate_1p8_dn = ngate_dn_lv.not(dualgate)

# pfet_01v8: Model for LV PMOS outside Dnwell [pmos_1p8]
pgate_1p8 = pgate_lv.not(dualgate)

# pfet_01v8_dn: Model for LV PMOS Inside Dnwell [pmos_1p8_dw] 
pgate_1p8_dn = pgate_dn_lv.not(dualgate)
                    
# nfet_01v8_nvt: Model for LV native Vt NMOS [nmos_1p8_nat]
ngate_1p8_nat = ngate_nat_lv.not(dualgate)

#================================
# ---- LV (3.3V) TRANSISTORS ----
#================================

logger.info('Starting 3.3V TRANSISTORS layers DERIVATIONS')

# nfet_03v3: Model for 3.3V NMOS outside Dnwell [nmos_3p3]
ngate_3p3 = ngate_pw_lv.and(dualgate)
      
# nfet_03v3_dn: Model for 3.3V NMOS Inside Dnwell [nmos_3p3_dw]
ngate_3p3_dn = ngate_dn_lv.and(dualgate)
                    
# pfet_03v3: Model for 3.3V PMOS outside Dnwell [pmos_3p3]
pgate_3p3 = pgate_lv.and(dualgate)

# pfet_03v3_dn: Model for 3.3V PMOS Inside Dnwell [pmos_3p3_dw]
pgate_3p3_dn = pgate_dn_lv.and(dualgate)

# nfet_03v3_nvt: Model for 3.3V native Vt NMOS [nmos_3p3_nat]
ngate_3p3_nat = ngate_nat_lv.and(dualgate)

#==============================
# ---- MV (5V) TRANSISTORS ----
#==============================

logger.info('Starting MV (5V) TRANSISTORS layers DERIVATIONS')

# nfet_05v0: Model for MV NMOS outside Dnwell [nmos_5p0]
ngate_5p0 = ngate_pw_mv.and(v5_xtor)

# nfet_05v0_dn: Model for MV NMOS Inside Dnwell [nmos_5p0_dw]
ngate_5p0_dn = ngate_dn_mv.and(v5_xtor)
    
# pfet_05v0: Model for MV PMOS Outside Dnwell [pmos_5p0]
pgate_5p0 = pgate_mv.and(v5_xtor)

# pfet_05v0_dn: Model for MV PMOS Inside Dnwell [pmos_5p0_dw]
pgate_5p0_dn = pgate_dn_mv.and(v5_xtor)

#==============================
# ---- MV (6V) TRANSISTORS ----
#==============================

logger.info('Starting MV (6V) TRANSISTORS layers DERIVATIONS')

# nfet_06v0: Model for MV NMOS outside Dnwell [nmos_6p0]
ngate_6p0 = ngate_pw_mv.not(v5_xtor)

# nfet_06v0_dn: Model for MV NMOS Inside Dnwell [nmos_6p0_dw]
ngate_6p0_dn = ngate_dn_mv.not(v5_xtor)
   
# pfet_06v0: Model for MV PMOS Outside Dnwell [pmos_6p0]
pgate_6p0 = pgate_mv.not(v5_xtor)

# pfet_06v0_dn: Model for MV PMOS Inside Dnwell [pmos_6p0_dw]
pgate_6p0_dn = pgate_dn_mv.not(v5_xtor)

# nfet_06v0_nvt: Model for 6.0V Native Vt NMOS [nmos_6p0_nat]
ngate_6p0_nat = ngate_nat_mv.not(v5_xtor)