blob: a36397edbe0cd9cf0d33e2234816f2eef0fd7bcb [file] [log] [blame]
################################################################################################
# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################################
#==================================
# ------ PISCAP DERIVATIONS -------
#==================================
logger.info('Starting PISCAP DERIVATIONS')
piscap_exclude = lvpwell.join(pplus).join(resistor)
.join(esd).join(sab).join(dni)
.join(pwhv).join(fusewindow_d).join(polyfuse)
.join(schottky_diode).join(zener).join(res_mk)
.join(diode_mk).join(v5_xtor).join(drc_bjt)
.join(nat).join(fhres).join(mos_cap_mk)
.join(mvsd).join(mvpsd).join(elmd_mk)
.join(elmd2_mk).join(lvs_rf).join(lvs_source)
.join(mk_35v).join(well_diode_mk).join(esd_hbm_mk)
.join(mos_mk_type1).join(swfet_mk).join(lvs_35v)
.join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
ngate_nw = nplus.and(tgate).and(piscap).and(nwell).not(piscap_exclude)
ngate_nw_lv = ngate_nw.not(dualgate2_d)
ngate_nw_mv = ngate_nw.and(dualgate2_d)
#====================
# --- PIS 1P8 CAP ---
#====================
# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
cap_pis_01v8_gate = ngate_nw_lv.not(dnwell)
# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
cap_pis_01v8_dn_gate = ngate_nw_lv.and(dnwell)
#====================
# --- PIS 6P0 CAP ---
#====================
# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
cap_pis_06v0_gate = ngate_nw_mv.not(dnwell)
# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
cap_pis_06v0_dn_gate = ngate_nw_mv.and(dnwell)