BCDLite/klayout/lvs/rule_decks/mos_derivations.lvs

################################################################################################
# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################################

#==================================
# ------ MOSFET DERIVATIONS -------
#==================================

logger.info('Starting MOSFET DERIVATIONS')

#====================
# --- MOS EXCLUDE ---
#====================

mos_exclude = sab.join(resistor).join(esd).join(dni)
                 .join(pwhv).join(fusewindow_d).join(polyfuse)
                 .join(schottky_diode).join(zener).join(piscap)
                 .join(res_mk).join(drc_bjt).join(fhres)
                 .join(mos_cap_mk).join(mvsd).join(mvpsd)
                 .join(elmd_mk).join(lvs_rf).join(lvs_source)
                 .join(mk_35v).join(lvs_35v).join(esd_hbm_mk)
                 .join(swfet_mk).join(hvnddd).join(hvpddd)
                 .join(hvpolyrs).join(ldmos_xtor)

#=================================
# ---- LV (1.8V) TRANSISTORS ----
#=================================

logger.info('Starting LV (1.8V) TRANSISTORS layers DERIVATIONS')

# nfet_01v8: Model for LV NMOS outside Dnwell [nmos_1p8]
ngate_1p8 = ngate_all.not(dualgate2_d).not(v5_xtor).not(nat).not(mos_exclude)

# nfet_01v8_dn: Model for LV NMOS Inside Dnwell [nmos_1p8 _dw]
ngate_1p8_dn = ngate_dn.not(nwell).not(dualgate2_d).not(v5_xtor).not(nat).not(mos_exclude)

# pfet_01v8: Model for LV PMOS outside Dnwell [pmos_1p8]
pgate_1p8 = pgate.not(dnwell).not(dualgate2_d).not(v5_xtor).not(nat).not(mos_exclude)

# pfet_01v8_dn: Model for LV PMOS Inside Dnwell [pmos_1p8_dw] 
pgate_1p8_dn = pgate_dn.not(dualgate2_d).not(v5_xtor).not(nat).not(mos_exclude)

# nfet_01v8_nvt: Model for LV native Vt NMOS [nmos_1p8_nat]
ngate_1p8_nat = ngate.and(nat).not(dualgate2_d).not(v5_xtor).not(mos_exclude)

#==============================
# ---- MV (5V) TRANSISTORS ----
#==============================

logger.info('Starting MV (5V) TRANSISTORS layers DERIVATIONS')

# nfet_05v0: Model for MV NMOS outside Dnwell [nmos_5p0]
ngate_5p0 = ngate_all.and(dualgate2_d).and(v5_xtor).not(nat).not(mos_exclude)

# nfet_05v0_dn: Model for MV NMOS Inside Dnwell [nmos_5p0_dw]
ngate_5p0_dn = ngate_dn.and(dualgate2_d).and(v5_xtor).not(nat).not(mos_exclude)

# pfet_05v0: Model for MV PMOS Outside Dnwell [pmos_5p0]
pgate_5p0 = pgate.not(dnwell).and(dualgate2_d).and(v5_xtor).not(nat).not(mos_exclude)

# pfet_05v0_dn: Model for MV PMOS Inside Dnwell [pmos_5p0_dw]
pgate_5p0_dn = pgate_dn.and(nwell).and(dualgate2_d).and(v5_xtor).not(nat).not(mos_exclude)

#==============================
# ---- MV (6V) TRANSISTORS ----
#==============================

logger.info('Starting MV (6V) TRANSISTORS layers DERIVATIONS')

# nfet_06v0: Model for MV NMOS outside Dnwell [nmos_6p0]
ngate_6p0 = ngate_all.and(dualgate2_d).not(v5_xtor).not(nat).not(mos_exclude)

# nfet_06v0_dn: Model for MV NMOS Inside Dnwell [nmos_6p0_dw]
ngate_6p0_dn = ngate_dn.and(dualgate2_d).not(v5_xtor).not(nat).not(mos_exclude)

# pfet_06v0: Model for MV PMOS Outside Dnwell [pmos_6p0]
pgate_6p0 = pgate.not(dnwell).and(dualgate2_d).not(v5_xtor).not(nat).not(mos_exclude)

# pfet_06v0_dn: Model for MV PMOS Inside Dnwell [pmos_6p0_dw]
pgate_6p0_dn = pgate_dn.and(dualgate2_d).not(v5_xtor).not(nat).not(mos_exclude)

# nfet_06v0_nvt: Model for 6.0V Native Vt NMOS [nmos_6p0_nat]
ngate_6p0_nat = ngate.and(nat).and(dualgate2_d).not(v5_xtor).not(mos_exclude)

# pfet_06v0_nvt_dn: Model for 6.0V Native Vt PMOS Inside Dnwell [pmos_6p0_nat_dw]
pgate_6p0_nat_dn = pgate_dn.not(nwell).and(nat).and(dualgate2_d).not(v5_xtor).not(mos_exclude)