ULL/klayout/lvs/rule_decks/mos_derivations.lvs

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# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
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#     https://www.apache.org/licenses/LICENSE-2.0
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# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
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#==================================
# ------ MOSFET DERIVATIONS -------
#==================================

logger.info('Starting MOSFET DERIVATIONS')

#=================================
# ---- LV (1.8V) TRANSISTORS ----
#=================================

logger.info('Starting LV (1.8V) TRANSISTORS layers DERIVATIONS')

# nmos_1p8 _dw (LV NMOS Inside Dnwell)
ngate_1p8_dw = ngate_dw.not(nwell).not(dualgate).not(sab).not(esd).not(resistor).not(fusetop).not(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# nmos_1p8 (LV NMOS outside Dnwell)
ngate_1p8 = ngate.and(lvpwell).outside(dnwell).not(nwell).not(dualgate).not(sab).not(esd).not(resistor).not(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d).not(fusetop)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# pmos_1p8_dw (LV PMOS Inside Dnwell)
pgate_1p8_dw = pgate_dw.and(nwell).not(dualgate).not(sab).not(esd).not(resistor).not(fusetop).not(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# pmos_1p8 (LV PMOS outside Dnwell)
pgate_1p8 = pgate.outside(lvpwell).and(nwell).outside(dnwell).not(dualgate).not(sab).not(esd).not(resistor)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat).not(dv2)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(fusetop)

# nmos_1p8_nat (LV native Vt NMOS)
ngate_1p8_nat = ngate.outside(lvpwell).not(nwell).outside(dnwell).and(nat).not(dualgate).not(sab).not(esd).not(resistor)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(fusetop).not(dv2)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)


#===========================
# ---- 3.3V TRANSISTORS ----
#===========================

logger.info('Starting 3.3V TRANSISTORS layers DERIVATIONS')

# nmos_3p3_dw (NMOS Inside Dnwell)
ngate_3p3_dw = ngate_dw.not(nwell).and(dualgate).not(sab).not(esd).not(resistor).not(fusetop).not(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# nmos_3p3 (NMOS outside Dnwell)
ngate_3p3 = ngate.and(lvpwell).outside(dnwell).not(nwell).and(dualgate).not(sab).not(esd).not(resistor).not(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d).not(fusetop)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# pmos_3p3_dw (PMOS Inside Dnwell)
pgate_3p3_dw = pgate_dw.and(nwell).and(dualgate).not(sab).not(esd).not(resistor).not(fusetop).not(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# pmos_3p3 (PMOS outside Dnwell)
pgate_3p3 = pgate.outside(lvpwell).and(nwell).outside(dnwell).and(dualgate).not(sab).not(esd).not(resistor)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat).not(dv2)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(fusetop)

# nmos_3p3_nat (3.3V Native Vt NMOS)
ngate_3p3_nat = ngate.outside(lvpwell).not(nwell).outside(dnwell).and(nat).and(dualgate).not(sab).not(esd).not(resistor)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(fusetop).not(dv2)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)


#==============================
# ---- MV (6V) TRANSISTORS ----
#==============================

logger.info('Starting MV (6V) TRANSISTORS layers DERIVATIONS')

# nmos_6p0_dw (MV NMOS Inside Dnwell)
ngate_6p0_dw = ngate_dw.not(nwell).not(dualgate).not(sab).not(esd).not(resistor).not(fusetop).and(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# nmos_6p0 (MV NMOS outside Dnwell)
ngate_6p0 = ngate.and(lvpwell).outside(dnwell).not(nwell).not(dualgate).not(sab).not(esd).not(resistor).and(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d).not(fusetop)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# pmos_6p0_dw (MV PMOS Inside Dnwell)
pgate_6p0_dw = pgate_dw.and(nwell).not(dualgate).not(sab).not(esd).not(resistor).not(fusetop).and(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)
                    
# pmos_6p0 (MV PMOS Outside Dnwell)
pgate_6p0 = pgate.outside(lvpwell).and(nwell).outside(dnwell).not(dualgate).not(sab).not(esd).not(resistor).and(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(fusetop)

# nmos_6p0_nat  (MV native Vt NMOS)
ngate_6p0_nat = ngate.outside(lvpwell).not(nwell).outside(dnwell).and(nat).not(dualgate).and(dv2).not(resistor)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(fusetop)
                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d).not(esd)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(sab)


#==============================
# ---- MV (5V) TRANSISTORS ----
#==============================

logger.info('Starting MV (5V) TRANSISTORS layers DERIVATIONS')

# nmos_5p0_dw (MV NMOS Inside Dnwell)
ngate_5p0_dw = ngate_dw.not(nwell).not(dualgate).not(sab).not(esd).not(resistor).and(v5_xtor).and(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .not(fusetop).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# nmos_5p0 (MV NMOS outside Dnwell)
ngate_5p0 = ngate.and(lvpwell).outside(dnwell).not(nwell).not(dualgate).not(sab).not(esd).not(resistor).and(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .and(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d).not(fusetop)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# pmos_5p0_dw (MV PMOS Inside Dnwell)
pgate_5p0_dw = pgate_dw.and(nwell).not(dualgate).not(sab).not(esd).not(resistor).not(fusetop).and(dv2)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
                    .and(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)

# pmos_5p0 (MV PMOS Outside Dnwell)
pgate_5p0 = pgate.outside(lvpwell).and(nwell).outside(dnwell).not(dualgate).not(sab).not(esd).not(resistor)
                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat).and(dv2)
                    .and(v5_xtor).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusewindow_d)
                    .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(fusetop)