| ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/__user_analog_project_wrapper.v |
| ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/__user_project_wrapper.v |
| ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/caravel.v.orig |
| ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/gpio_defaults_block.v |
| ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/user_project_wrapper.v |
| read_liberty /home/kareem_farid/gf180.new/pdk/gf180mcuC/libs.ref//gf180mcu_sc7_hv/liberty/GF018hv5v_mcu_sc7_TT_5P0V_25C.lib |
| read_liberty /home/kareem_farid/gf180.new/pdk/gf180mcuC/libs.ref//gf180mcu_sram/liberty/GF018_5VGreen_SRAM_1P_128x8M8WM1_tt_5p0v_25c.lib |
| read_liberty /home/kareem_farid/gf180.new/pdk/gf180mcuC/libs.ref//gf180mcu_sram/liberty/GF018_5VGreen_SRAM_1P_512x8M8WM1_tt_5p0v_25c.lib |
| read_liberty /home/kareem_farid/gf180.new/pdk/gf180mcuC/libs.ref//gf180mcu_sram/liberty/GF018_5VGreen_SRAM_1P_256x8M8WM1_tt_5p0v_25c.lib |
| read_liberty /home/kareem_farid/gf180.new/pdk/gf180mcuC/libs.ref//gf180mcu_sram/liberty/GF018_5VGreen_SRAM_1P_64x8M8WM1_tt_5p0v_25c.lib |
| read_liberty /home/kareem_farid/gf180.new/pdk/gf180mcuC/libs.ref//gf180mcu_io/liberty/GF018green_ipio_5p0c_75_TT_5P00V_25C_5P00V.lib |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/user_id_programming.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/gpio_control_block.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/housekeeping.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/gpio_defaults_block_007.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/caravel_clocking.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/caravel.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/spare_logic_block.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/gpio_defaults_block_009.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/mgmt_protect.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/bla |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/chip_io.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/digital_pll.v |
| read_verilog /home/kareem_farid/gf180.new/caravel/mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v |
| Warning: /home/kareem_farid/gf180.new/caravel/mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v line 3814, module user_project_wrapper not found. Creating black box for mprj. |
| Warning: /home/kareem_farid/gf180.new/caravel/mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v line 3891, module simple_por not found. Creating black box for por_inst. |
| read_spef -path gpio_control_in_2[2] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[2\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[2\]/one. |
| read_spef -path gpio_control_in_2[11] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[11\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[11\]/one. |
| read_spef -path clock_ctrl /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_clocking_nom.spef |
| read_spef -path gpio_control_in_1[3] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[3\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[3\]/one. |
| read_spef -path spare_logic[1] /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 370, *290 not connected to net spare_logic\[1\]/spare_xfq[0]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 377, *290 not connected to net spare_logic\[1\]/spare_xfq[0]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 386, *291 not connected to net spare_logic\[1\]/spare_xfq[1]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 390, *291 not connected to net spare_logic\[1\]/spare_xfq[1]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 569, instance spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 573, *292 not connected to net spare_logic\[1\]/net4. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 574, net spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 588, net spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 590, *292 not connected to net spare_logic\[1\]/net4. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 596, instance spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 600, *301 not connected to net spare_logic\[1\]/net6. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 601, net spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 613, net spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 615, *301 not connected to net spare_logic\[1\]/net6. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 621, instance spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 625, *300 not connected to net spare_logic\[1\]/net8. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 626, net spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 634, net spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 635, *300 not connected to net spare_logic\[1\]/net8. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 642, instance spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 646, *301 not connected to net spare_logic\[1\]/net10. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 647, net spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 658, net spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 659, *301 not connected to net spare_logic\[1\]/net10. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 666, instance spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 670, *296 not connected to net spare_logic\[1\]/net12. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 671, net spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 686, net spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 688, *296 not connected to net spare_logic\[1\]/net12. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 694, instance spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 698, *297 not connected to net spare_logic\[1\]/net14. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 699, net spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 710, net spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 711, *297 not connected to net spare_logic\[1\]/net14. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 718, instance spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 722, *296 not connected to net spare_logic\[1\]/net16. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 723, net spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 730, net spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 731, *296 not connected to net spare_logic\[1\]/net16. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 738, instance spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 742, *297 not connected to net spare_logic\[1\]/net18. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 743, net spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 760, net spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 762, *297 not connected to net spare_logic\[1\]/net18. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 768, instance spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 772, *296 not connected to net spare_logic\[1\]/net20. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 773, net spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 784, net spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 785, *296 not connected to net spare_logic\[1\]/net20. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 792, instance spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 796, *297 not connected to net spare_logic\[1\]/net22. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 797, net spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 807, net spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 808, *297 not connected to net spare_logic\[1\]/net22. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 815, instance spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 819, *290 not connected to net spare_logic\[1\]/net24. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 820, net spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 828, net spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 830, *290 not connected to net spare_logic\[1\]/net24. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 836, instance spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 840, *293 not connected to net spare_logic\[1\]/net26. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 841, net spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 857, net spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 858, *293 not connected to net spare_logic\[1\]/net26. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 865, instance spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 869, *291 not connected to net spare_logic\[1\]/net28. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 870, net spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 881, net spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 882, *291 not connected to net spare_logic\[1\]/net28. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 889, instance spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 893, *290 not connected to net spare_logic\[1\]/net30. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 894, net spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 906, net spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 907, *290 not connected to net spare_logic\[1\]/net30. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 914, instance spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 918, *291 not connected to net spare_logic\[1\]/net32. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 919, net spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 931, net spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 933, *291 not connected to net spare_logic\[1\]/net32. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 939, instance spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 943, *290 not connected to net spare_logic\[1\]/net34. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 944, net spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 953, net spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 954, *290 not connected to net spare_logic\[1\]/net34. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 961, instance spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 965, *291 not connected to net spare_logic\[1\]/net36. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 966, net spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 979, net spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 981, *291 not connected to net spare_logic\[1\]/net36. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 987, instance spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 991, *290 not connected to net spare_logic\[1\]/net38. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 992, net spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1000, net spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1001, *290 not connected to net spare_logic\[1\]/net38. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1008, instance spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1012, *291 not connected to net spare_logic\[1\]/net40. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1013, net spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1027, net spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1029, *291 not connected to net spare_logic\[1\]/net40. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1034, instance spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1038, net spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1041, net spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1046, instance spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1050, net spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1056, net spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1061, instance spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1065, net spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1068, net spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1074, instance spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1078, *294 not connected to net spare_logic\[1\]/net42. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1079, net spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1085, net spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1087, *294 not connected to net spare_logic\[1\]/net42. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1092, instance spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1096, net spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1098, net spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1104, instance spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1108, *295 not connected to net spare_logic\[1\]/net44. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1109, net spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1118, net spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1119, *295 not connected to net spare_logic\[1\]/net44. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1126, instance spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1130, *258 not connected to net spare_logic\[1\]/net46. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1131, net spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1142, net spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1143, *258 not connected to net spare_logic\[1\]/net46. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1150, instance spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1154, *298 not connected to net spare_logic\[1\]/net48. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1155, net spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1163, net spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1164, *298 not connected to net spare_logic\[1\]/net48. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1171, instance spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1175, *299 not connected to net spare_logic\[1\]/net50. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1176, net spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1184, net spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1186, *299 not connected to net spare_logic\[1\]/net50. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1192, instance spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1196, *298 not connected to net spare_logic\[1\]/net52. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1197, net spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1205, net spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1207, *298 not connected to net spare_logic\[1\]/net52. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1213, instance spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1217, *299 not connected to net spare_logic\[1\]/net54. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1218, net spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1235, net spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1236, *299 not connected to net spare_logic\[1\]/net54. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1243, instance spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1247, *300 not connected to net spare_logic\[1\]/net56. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1248, net spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1258, net spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1259, *300 not connected to net spare_logic\[1\]/net56. |
| read_spef -path mgmt_buffers /home/kareem_farid/gf180.new/caravel/caravel/spef/mgmt_protect_nom.spef |
| read_spef -path gpio_control_in_1a[3] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1a\[3\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1a\[3\]/one. |
| read_spef -path gpio_control_bidir_1[1] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 724, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 744, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1057, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1084, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1108, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1110, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1111, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1112, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1113, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1114, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1121, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1123, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2239, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2301, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2303, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2304, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2305, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2306, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2307, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2309, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2310, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2312, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2773, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2774, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2879, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2906, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2908, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3385, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3386, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3387, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3468, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3524, pin one not found. |
| read_spef -path gpio_control_bidir_2[0] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 724, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 744, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1057, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1084, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1108, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1110, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1111, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1112, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1113, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1114, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1121, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1123, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2239, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2301, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2303, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2304, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2305, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2306, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2307, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2309, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2310, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2312, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2773, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2774, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2879, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2906, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2908, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3385, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3386, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3387, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3468, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3524, pin one not found. |
| read_spef -path gpio_control_in_2[4] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[4\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[4\]/one. |
| read_spef -path gpio_control_in_2[13] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[13\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[13\]/one. |
| read_spef -path gpio_control_in_1[5] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[5\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[5\]/one. |
| read_spef -path spare_logic[3] /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 370, *290 not connected to net spare_logic\[3\]/spare_xfq[0]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 377, *290 not connected to net spare_logic\[3\]/spare_xfq[0]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 386, *291 not connected to net spare_logic\[3\]/spare_xfq[1]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 390, *291 not connected to net spare_logic\[3\]/spare_xfq[1]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 569, instance spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 573, *292 not connected to net spare_logic\[3\]/net4. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 574, net spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 588, net spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 590, *292 not connected to net spare_logic\[3\]/net4. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 596, instance spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 600, *301 not connected to net spare_logic\[3\]/net6. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 601, net spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 613, net spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 615, *301 not connected to net spare_logic\[3\]/net6. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 621, instance spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 625, *300 not connected to net spare_logic\[3\]/net8. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 626, net spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 634, net spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 635, *300 not connected to net spare_logic\[3\]/net8. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 642, instance spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 646, *301 not connected to net spare_logic\[3\]/net10. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 647, net spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 658, net spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 659, *301 not connected to net spare_logic\[3\]/net10. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 666, instance spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 670, *296 not connected to net spare_logic\[3\]/net12. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 671, net spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 686, net spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 688, *296 not connected to net spare_logic\[3\]/net12. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 694, instance spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 698, *297 not connected to net spare_logic\[3\]/net14. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 699, net spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 710, net spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 711, *297 not connected to net spare_logic\[3\]/net14. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 718, instance spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 722, *296 not connected to net spare_logic\[3\]/net16. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 723, net spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 730, net spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 731, *296 not connected to net spare_logic\[3\]/net16. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 738, instance spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 742, *297 not connected to net spare_logic\[3\]/net18. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 743, net spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 760, net spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 762, *297 not connected to net spare_logic\[3\]/net18. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 768, instance spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 772, *296 not connected to net spare_logic\[3\]/net20. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 773, net spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 784, net spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 785, *296 not connected to net spare_logic\[3\]/net20. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 792, instance spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 796, *297 not connected to net spare_logic\[3\]/net22. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 797, net spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 807, net spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 808, *297 not connected to net spare_logic\[3\]/net22. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 815, instance spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 819, *290 not connected to net spare_logic\[3\]/net24. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 820, net spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 828, net spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 830, *290 not connected to net spare_logic\[3\]/net24. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 836, instance spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 840, *293 not connected to net spare_logic\[3\]/net26. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 841, net spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 857, net spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 858, *293 not connected to net spare_logic\[3\]/net26. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 865, instance spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 869, *291 not connected to net spare_logic\[3\]/net28. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 870, net spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 881, net spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 882, *291 not connected to net spare_logic\[3\]/net28. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 889, instance spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 893, *290 not connected to net spare_logic\[3\]/net30. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 894, net spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 906, net spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 907, *290 not connected to net spare_logic\[3\]/net30. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 914, instance spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 918, *291 not connected to net spare_logic\[3\]/net32. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 919, net spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 931, net spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 933, *291 not connected to net spare_logic\[3\]/net32. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 939, instance spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 943, *290 not connected to net spare_logic\[3\]/net34. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 944, net spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 953, net spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 954, *290 not connected to net spare_logic\[3\]/net34. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 961, instance spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 965, *291 not connected to net spare_logic\[3\]/net36. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 966, net spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 979, net spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 981, *291 not connected to net spare_logic\[3\]/net36. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 987, instance spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 991, *290 not connected to net spare_logic\[3\]/net38. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 992, net spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1000, net spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1001, *290 not connected to net spare_logic\[3\]/net38. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1008, instance spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1012, *291 not connected to net spare_logic\[3\]/net40. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1013, net spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1027, net spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1029, *291 not connected to net spare_logic\[3\]/net40. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1034, instance spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1038, net spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1041, net spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1046, instance spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1050, net spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1056, net spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1061, instance spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1065, net spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1068, net spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1074, instance spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1078, *294 not connected to net spare_logic\[3\]/net42. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1079, net spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1085, net spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1087, *294 not connected to net spare_logic\[3\]/net42. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1092, instance spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1096, net spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1098, net spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1104, instance spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1108, *295 not connected to net spare_logic\[3\]/net44. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1109, net spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1118, net spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1119, *295 not connected to net spare_logic\[3\]/net44. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1126, instance spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1130, *258 not connected to net spare_logic\[3\]/net46. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1131, net spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1142, net spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1143, *258 not connected to net spare_logic\[3\]/net46. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1150, instance spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1154, *298 not connected to net spare_logic\[3\]/net48. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1155, net spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1163, net spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1164, *298 not connected to net spare_logic\[3\]/net48. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1171, instance spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1175, *299 not connected to net spare_logic\[3\]/net50. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1176, net spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1184, net spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1186, *299 not connected to net spare_logic\[3\]/net50. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1192, instance spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1196, *298 not connected to net spare_logic\[3\]/net52. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1197, net spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1205, net spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1207, *298 not connected to net spare_logic\[3\]/net52. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1213, instance spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1217, *299 not connected to net spare_logic\[3\]/net54. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1218, net spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1235, net spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1236, *299 not connected to net spare_logic\[3\]/net54. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1243, instance spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1247, *300 not connected to net spare_logic\[3\]/net56. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1248, net spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1258, net spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1259, *300 not connected to net spare_logic\[3\]/net56. |
| read_spef -path gpio_control_in_1a[5] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1a\[5\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1a\[5\]/one. |
| read_spef -path gpio_control_bidir_2[2] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 724, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 744, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1057, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1084, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1108, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1110, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1111, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1112, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1113, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1114, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1121, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1123, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2239, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2301, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2303, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2304, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2305, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2306, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2307, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2309, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2310, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2312, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2773, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2774, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2879, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2906, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2908, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3385, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3386, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3387, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3468, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3524, pin one not found. |
| read_spef -path gpio_control_in_2[6] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[6\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[6\]/one. |
| read_spef -path gpio_control_in_2[15] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[15\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[15\]/one. |
| read_spef -path gpio_control_in_1[7] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[7\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[7\]/one. |
| read_spef -path gpio_control_in_1[0] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[0\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[0\]/one. |
| read_spef -path gpio_control_in_2[8] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[8\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[8\]/one. |
| read_spef -path gpio_control_in_1a[0] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1a\[0\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1a\[0\]/one. |
| read_spef -path gpio_control_in_1[9] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[9\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[9\]/one. |
| read_spef -path gpio_control_in_1[10] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[10\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[10\]/one. |
| read_spef -path gpio_control_in_2[1] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[1\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[1\]/one. |
| read_spef -path gpio_control_in_2[10] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[10\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[10\]/one. |
| read_spef -path gpio_control_in_1[2] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[2\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[2\]/one. |
| read_spef -path spare_logic[0] /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 370, *290 not connected to net spare_logic\[0\]/spare_xfq[0]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 377, *290 not connected to net spare_logic\[0\]/spare_xfq[0]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 386, *291 not connected to net spare_logic\[0\]/spare_xfq[1]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 390, *291 not connected to net spare_logic\[0\]/spare_xfq[1]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 569, instance spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 573, *292 not connected to net spare_logic\[0\]/net4. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 574, net spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 588, net spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 590, *292 not connected to net spare_logic\[0\]/net4. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 596, instance spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 600, *301 not connected to net spare_logic\[0\]/net6. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 601, net spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 613, net spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 615, *301 not connected to net spare_logic\[0\]/net6. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 621, instance spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 625, *300 not connected to net spare_logic\[0\]/net8. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 626, net spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 634, net spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 635, *300 not connected to net spare_logic\[0\]/net8. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 642, instance spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 646, *301 not connected to net spare_logic\[0\]/net10. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 647, net spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 658, net spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 659, *301 not connected to net spare_logic\[0\]/net10. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 666, instance spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 670, *296 not connected to net spare_logic\[0\]/net12. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 671, net spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 686, net spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 688, *296 not connected to net spare_logic\[0\]/net12. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 694, instance spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 698, *297 not connected to net spare_logic\[0\]/net14. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 699, net spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 710, net spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 711, *297 not connected to net spare_logic\[0\]/net14. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 718, instance spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 722, *296 not connected to net spare_logic\[0\]/net16. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 723, net spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 730, net spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 731, *296 not connected to net spare_logic\[0\]/net16. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 738, instance spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 742, *297 not connected to net spare_logic\[0\]/net18. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 743, net spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 760, net spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 762, *297 not connected to net spare_logic\[0\]/net18. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 768, instance spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 772, *296 not connected to net spare_logic\[0\]/net20. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 773, net spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 784, net spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 785, *296 not connected to net spare_logic\[0\]/net20. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 792, instance spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 796, *297 not connected to net spare_logic\[0\]/net22. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 797, net spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 807, net spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 808, *297 not connected to net spare_logic\[0\]/net22. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 815, instance spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 819, *290 not connected to net spare_logic\[0\]/net24. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 820, net spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 828, net spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 830, *290 not connected to net spare_logic\[0\]/net24. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 836, instance spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 840, *293 not connected to net spare_logic\[0\]/net26. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 841, net spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 857, net spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 858, *293 not connected to net spare_logic\[0\]/net26. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 865, instance spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 869, *291 not connected to net spare_logic\[0\]/net28. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 870, net spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 881, net spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 882, *291 not connected to net spare_logic\[0\]/net28. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 889, instance spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 893, *290 not connected to net spare_logic\[0\]/net30. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 894, net spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 906, net spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 907, *290 not connected to net spare_logic\[0\]/net30. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 914, instance spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 918, *291 not connected to net spare_logic\[0\]/net32. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 919, net spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 931, net spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 933, *291 not connected to net spare_logic\[0\]/net32. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 939, instance spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 943, *290 not connected to net spare_logic\[0\]/net34. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 944, net spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 953, net spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 954, *290 not connected to net spare_logic\[0\]/net34. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 961, instance spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 965, *291 not connected to net spare_logic\[0\]/net36. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 966, net spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 979, net spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 981, *291 not connected to net spare_logic\[0\]/net36. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 987, instance spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 991, *290 not connected to net spare_logic\[0\]/net38. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 992, net spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1000, net spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1001, *290 not connected to net spare_logic\[0\]/net38. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1008, instance spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1012, *291 not connected to net spare_logic\[0\]/net40. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1013, net spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1027, net spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1029, *291 not connected to net spare_logic\[0\]/net40. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1034, instance spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1038, net spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1041, net spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1046, instance spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1050, net spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1056, net spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1061, instance spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1065, net spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1068, net spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1074, instance spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1078, *294 not connected to net spare_logic\[0\]/net42. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1079, net spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1085, net spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1087, *294 not connected to net spare_logic\[0\]/net42. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1092, instance spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1096, net spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1098, net spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1104, instance spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1108, *295 not connected to net spare_logic\[0\]/net44. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1109, net spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1118, net spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1119, *295 not connected to net spare_logic\[0\]/net44. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1126, instance spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1130, *258 not connected to net spare_logic\[0\]/net46. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1131, net spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1142, net spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1143, *258 not connected to net spare_logic\[0\]/net46. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1150, instance spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1154, *298 not connected to net spare_logic\[0\]/net48. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1155, net spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1163, net spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1164, *298 not connected to net spare_logic\[0\]/net48. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1171, instance spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1175, *299 not connected to net spare_logic\[0\]/net50. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1176, net spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1184, net spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1186, *299 not connected to net spare_logic\[0\]/net50. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1192, instance spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1196, *298 not connected to net spare_logic\[0\]/net52. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1197, net spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1205, net spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1207, *298 not connected to net spare_logic\[0\]/net52. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1213, instance spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1217, *299 not connected to net spare_logic\[0\]/net54. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1218, net spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1235, net spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1236, *299 not connected to net spare_logic\[0\]/net54. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1243, instance spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1247, *300 not connected to net spare_logic\[0\]/net56. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1248, net spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1258, net spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1259, *300 not connected to net spare_logic\[0\]/net56. |
| read_spef -path pll /home/kareem_farid/gf180.new/caravel/caravel/spef/digital_pll_nom.spef |
| read_spef -path gpio_control_in_1a[2] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1a\[2\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1a\[2\]/one. |
| read_spef -path gpio_control_bidir_1[0] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 724, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 744, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1057, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1084, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1108, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1110, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1111, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1112, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1113, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1114, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1121, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1123, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2239, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2301, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2303, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2304, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2305, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2306, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2307, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2309, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2310, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2312, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2773, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2774, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2879, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2906, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2908, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3385, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3386, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3387, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3468, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3524, pin one not found. |
| read_spef -path gpio_control_in_2[3] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[3\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[3\]/one. |
| read_spef -path gpio_control_in_2[12] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[12\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[12\]/one. |
| read_spef -path gpio_control_in_1[4] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[4\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[4\]/one. |
| read_spef -path spare_logic[2] /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 370, *290 not connected to net spare_logic\[2\]/spare_xfq[0]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 377, *290 not connected to net spare_logic\[2\]/spare_xfq[0]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 386, *291 not connected to net spare_logic\[2\]/spare_xfq[1]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 390, *291 not connected to net spare_logic\[2\]/spare_xfq[1]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 569, instance spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 573, *292 not connected to net spare_logic\[2\]/net4. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 574, net spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 588, net spare_logic_const_zero\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 590, *292 not connected to net spare_logic\[2\]/net4. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 596, instance spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 600, *301 not connected to net spare_logic\[2\]/net6. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 601, net spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 613, net spare_logic_const_zero\[10\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 615, *301 not connected to net spare_logic\[2\]/net6. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 621, instance spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 625, *300 not connected to net spare_logic\[2\]/net8. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 626, net spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 634, net spare_logic_const_zero\[11\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 635, *300 not connected to net spare_logic\[2\]/net8. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 642, instance spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 646, *301 not connected to net spare_logic\[2\]/net10. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 647, net spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 658, net spare_logic_const_zero\[12\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 659, *301 not connected to net spare_logic\[2\]/net10. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 666, instance spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 670, *296 not connected to net spare_logic\[2\]/net12. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 671, net spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 686, net spare_logic_const_zero\[13\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 688, *296 not connected to net spare_logic\[2\]/net12. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 694, instance spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 698, *297 not connected to net spare_logic\[2\]/net14. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 699, net spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 710, net spare_logic_const_zero\[14\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 711, *297 not connected to net spare_logic\[2\]/net14. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 718, instance spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 722, *296 not connected to net spare_logic\[2\]/net16. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 723, net spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 730, net spare_logic_const_zero\[15\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 731, *296 not connected to net spare_logic\[2\]/net16. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 738, instance spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 742, *297 not connected to net spare_logic\[2\]/net18. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 743, net spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 760, net spare_logic_const_zero\[16\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 762, *297 not connected to net spare_logic\[2\]/net18. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 768, instance spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 772, *296 not connected to net spare_logic\[2\]/net20. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 773, net spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 784, net spare_logic_const_zero\[17\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 785, *296 not connected to net spare_logic\[2\]/net20. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 792, instance spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 796, *297 not connected to net spare_logic\[2\]/net22. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 797, net spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 807, net spare_logic_const_zero\[18\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 808, *297 not connected to net spare_logic\[2\]/net22. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 815, instance spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 819, *290 not connected to net spare_logic\[2\]/net24. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 820, net spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 828, net spare_logic_const_zero\[19\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 830, *290 not connected to net spare_logic\[2\]/net24. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 836, instance spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 840, *293 not connected to net spare_logic\[2\]/net26. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 841, net spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 857, net spare_logic_const_zero\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 858, *293 not connected to net spare_logic\[2\]/net26. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 865, instance spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 869, *291 not connected to net spare_logic\[2\]/net28. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 870, net spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 881, net spare_logic_const_zero\[20\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 882, *291 not connected to net spare_logic\[2\]/net28. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 889, instance spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 893, *290 not connected to net spare_logic\[2\]/net30. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 894, net spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 906, net spare_logic_const_zero\[21\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 907, *290 not connected to net spare_logic\[2\]/net30. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 914, instance spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 918, *291 not connected to net spare_logic\[2\]/net32. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 919, net spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 931, net spare_logic_const_zero\[22\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 933, *291 not connected to net spare_logic\[2\]/net32. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 939, instance spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 943, *290 not connected to net spare_logic\[2\]/net34. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 944, net spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 953, net spare_logic_const_zero\[23\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 954, *290 not connected to net spare_logic\[2\]/net34. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 961, instance spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 965, *291 not connected to net spare_logic\[2\]/net36. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 966, net spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 979, net spare_logic_const_zero\[24\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 981, *291 not connected to net spare_logic\[2\]/net36. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 987, instance spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 991, *290 not connected to net spare_logic\[2\]/net38. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 992, net spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1000, net spare_logic_const_zero\[25\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1001, *290 not connected to net spare_logic\[2\]/net38. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1008, instance spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1012, *291 not connected to net spare_logic\[2\]/net40. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1013, net spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1027, net spare_logic_const_zero\[26\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1029, *291 not connected to net spare_logic\[2\]/net40. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1034, instance spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1038, net spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1041, net spare_logic_const_one\[0\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1046, instance spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1050, net spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1056, net spare_logic_const_one\[1\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1061, instance spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1065, net spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1068, net spare_logic_const_one\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1074, instance spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1078, *294 not connected to net spare_logic\[2\]/net42. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1079, net spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1085, net spare_logic_const_zero\[2\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1087, *294 not connected to net spare_logic\[2\]/net42. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1092, instance spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1096, net spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1098, net spare_logic_const_one\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1104, instance spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1108, *295 not connected to net spare_logic\[2\]/net44. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1109, net spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1118, net spare_logic_const_zero\[3\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1119, *295 not connected to net spare_logic\[2\]/net44. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1126, instance spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1130, *258 not connected to net spare_logic\[2\]/net46. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1131, net spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1142, net spare_logic_const_zero\[4\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1143, *258 not connected to net spare_logic\[2\]/net46. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1150, instance spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1154, *298 not connected to net spare_logic\[2\]/net48. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1155, net spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1163, net spare_logic_const_zero\[5\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1164, *298 not connected to net spare_logic\[2\]/net48. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1171, instance spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1175, *299 not connected to net spare_logic\[2\]/net50. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1176, net spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1184, net spare_logic_const_zero\[6\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1186, *299 not connected to net spare_logic\[2\]/net50. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1192, instance spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1196, *298 not connected to net spare_logic\[2\]/net52. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1197, net spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1205, net spare_logic_const_zero\[7\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1207, *298 not connected to net spare_logic\[2\]/net52. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1213, instance spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1217, *299 not connected to net spare_logic\[2\]/net54. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1218, net spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1235, net spare_logic_const_zero\[8\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1236, *299 not connected to net spare_logic\[2\]/net54. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1243, instance spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1247, *300 not connected to net spare_logic\[2\]/net56. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1248, net spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1258, net spare_logic_const_zero\[9\] not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/spare_logic_block_nom.spef line 1259, *300 not connected to net spare_logic\[2\]/net56. |
| read_spef -path gpio_control_in_1a[4] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1a\[4\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1a\[4\]/one. |
| read_spef -path gpio_control_bidir_2[1] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 724, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 744, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1057, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1084, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1108, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1109, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1110, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1111, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1112, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1113, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1114, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1121, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1123, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2239, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2301, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2303, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2304, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2305, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2306, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2307, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2308, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2309, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2310, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2312, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2773, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2774, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2879, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2906, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 2908, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3385, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3386, pin one not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3387, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3468, pin zero not found. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 3524, pin one not found. |
| read_spef -path gpio_control_in_2[5] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[5\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[5\]/one. |
| read_spef -path gpio_control_in_2[14] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[14\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[14\]/one. |
| read_spef -path gpio_control_in_1[6] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[6\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[6\]/one. |
| read_spef -path soc /home/kareem_farid/gf180.new/caravel/mgmt_soc_litex/spef/mgmt_core_wrapper_nom.spef |
| read_spef -path gpio_control_in_2[7] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[7\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[7\]/one. |
| read_spef -path gpio_control_in_1[8] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[8\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[8\]/one. |
| read_spef -path gpio_control_in_2[0] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[0\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[0\]/one. |
| read_spef -path gpio_control_in_1[1] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1\[1\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1\[1\]/one. |
| read_spef -path housekeeping /home/kareem_farid/gf180.new/caravel/caravel/spef/housekeeping_nom.spef |
| read_spef -path gpio_control_in_2[9] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_2\[9\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_2\[9\]/one. |
| read_spef -path gpio_control_in_1a[1] /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1104, one not connected to net gpio_control_in_1a\[1\]/one. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/gpio_control_block_nom.spef line 1127, one not connected to net gpio_control_in_1a\[1\]/one. |
| read_spef /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9197, *2317 not connected to net la_data_in_user\[0\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9212, *2317 not connected to net la_data_in_user\[0\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9220, *2317 not connected to net la_data_in_user\[10\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9253, *2317 not connected to net la_data_in_user\[10\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9261, *2317 not connected to net la_data_in_user\[11\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9288, *2317 not connected to net la_data_in_user\[11\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9296, *2317 not connected to net la_data_in_user\[12\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9321, *2317 not connected to net la_data_in_user\[12\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9329, *2317 not connected to net la_data_in_user\[13\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9361, *2317 not connected to net la_data_in_user\[13\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9369, *2317 not connected to net la_data_in_user\[14\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9387, *2317 not connected to net la_data_in_user\[14\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9395, *2317 not connected to net la_data_in_user\[15\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9417, *2317 not connected to net la_data_in_user\[15\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9425, *2317 not connected to net la_data_in_user\[16\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9439, *2317 not connected to net la_data_in_user\[16\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9447, *2317 not connected to net la_data_in_user\[17\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9463, *2317 not connected to net la_data_in_user\[17\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9471, *2317 not connected to net la_data_in_user\[18\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9485, *2317 not connected to net la_data_in_user\[18\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9493, *2317 not connected to net la_data_in_user\[19\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9508, *2317 not connected to net la_data_in_user\[19\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9516, *2317 not connected to net la_data_in_user\[1\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9532, *2317 not connected to net la_data_in_user\[1\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9540, *2317 not connected to net la_data_in_user\[20\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9555, *2317 not connected to net la_data_in_user\[20\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9563, *2317 not connected to net la_data_in_user\[21\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9577, *2317 not connected to net la_data_in_user\[21\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9585, *2317 not connected to net la_data_in_user\[22\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9616, *2317 not connected to net la_data_in_user\[22\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9624, *2317 not connected to net la_data_in_user\[23\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9647, *2317 not connected to net la_data_in_user\[23\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9655, *2317 not connected to net la_data_in_user\[24\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9678, *2317 not connected to net la_data_in_user\[24\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9686, *2317 not connected to net la_data_in_user\[25\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9702, *2317 not connected to net la_data_in_user\[25\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9710, *2317 not connected to net la_data_in_user\[26\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9728, *2317 not connected to net la_data_in_user\[26\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9736, *2317 not connected to net la_data_in_user\[27\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9752, *2317 not connected to net la_data_in_user\[27\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9760, *2317 not connected to net la_data_in_user\[28\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9776, *2317 not connected to net la_data_in_user\[28\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9784, *2317 not connected to net la_data_in_user\[29\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9802, *2317 not connected to net la_data_in_user\[29\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9810, *2317 not connected to net la_data_in_user\[2\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9826, *2317 not connected to net la_data_in_user\[2\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9834, *2317 not connected to net la_data_in_user\[30\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9853, *2317 not connected to net la_data_in_user\[30\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9861, *2317 not connected to net la_data_in_user\[31\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 9877, *2317 not connected to net la_data_in_user\[31\]. |
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| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 31505, *2317 not connected to net user_io_in\[0\]. |
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| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32203, *2317 not connected to net user_io_in\[3\]. |
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| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32224, *2317 not connected to net user_io_in\[4\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32236, *2317 not connected to net user_io_in\[4\]. |
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| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32266, *2317 not connected to net user_io_in\[6\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32286, *2317 not connected to net user_io_in\[6\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32294, *2317 not connected to net user_io_in\[7\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32325, *2317 not connected to net user_io_in\[7\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32333, *2317 not connected to net user_io_in\[8\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32365, *2317 not connected to net user_io_in\[8\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32373, *2317 not connected to net user_io_in\[9\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32401, *2317 not connected to net user_io_in\[9\]. |
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| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32454, *2317 not connected to net user_io_oeb\[10\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32467, *2317 not connected to net user_io_oeb\[11\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32484, *2317 not connected to net user_io_oeb\[11\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32497, *2317 not connected to net user_io_oeb\[12\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32515, *2317 not connected to net user_io_oeb\[12\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32528, *2317 not connected to net user_io_oeb\[13\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32535, *2317 not connected to net user_io_oeb\[13\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32546, *2317 not connected to net user_io_oeb\[14\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32557, *2317 not connected to net user_io_oeb\[14\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32567, *2317 not connected to net user_io_oeb\[15\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32578, *2317 not connected to net user_io_oeb\[15\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32589, *2317 not connected to net user_io_oeb\[16\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32593, *2317 not connected to net user_io_oeb\[16\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32602, *2317 not connected to net user_io_oeb\[17\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32607, *2317 not connected to net user_io_oeb\[17\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32617, *2317 not connected to net user_io_oeb\[18\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32624, *2317 not connected to net user_io_oeb\[18\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32634, *2317 not connected to net user_io_oeb\[19\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32646, *2317 not connected to net user_io_oeb\[19\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32656, *2317 not connected to net user_io_oeb\[1\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32667, *2317 not connected to net user_io_oeb\[1\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32678, *2317 not connected to net user_io_oeb\[20\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32684, *2317 not connected to net user_io_oeb\[20\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32693, *2317 not connected to net user_io_oeb\[21\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32700, *2317 not connected to net user_io_oeb\[21\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32709, *2317 not connected to net user_io_oeb\[22\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32716, *2317 not connected to net user_io_oeb\[22\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32726, *2317 not connected to net user_io_oeb\[23\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32741, *2317 not connected to net user_io_oeb\[23\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32752, *2317 not connected to net user_io_oeb\[24\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32760, *2317 not connected to net user_io_oeb\[24\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32770, *2317 not connected to net user_io_oeb\[25\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32783, *2317 not connected to net user_io_oeb\[25\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32794, *2317 not connected to net user_io_oeb\[26\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32807, *2317 not connected to net user_io_oeb\[26\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32818, *2317 not connected to net user_io_oeb\[27\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32831, *2317 not connected to net user_io_oeb\[27\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32842, *2317 not connected to net user_io_oeb\[28\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32857, *2317 not connected to net user_io_oeb\[28\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32868, *2317 not connected to net user_io_oeb\[29\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32881, *2317 not connected to net user_io_oeb\[29\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32892, *2317 not connected to net user_io_oeb\[2\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32904, *2317 not connected to net user_io_oeb\[2\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32915, *2317 not connected to net user_io_oeb\[30\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32929, *2317 not connected to net user_io_oeb\[30\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32940, *2317 not connected to net user_io_oeb\[31\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32951, *2317 not connected to net user_io_oeb\[31\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32962, *2317 not connected to net user_io_oeb\[32\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32979, *2317 not connected to net user_io_oeb\[32\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 32990, *2317 not connected to net user_io_oeb\[33\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33005, *2317 not connected to net user_io_oeb\[33\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33016, *2317 not connected to net user_io_oeb\[34\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33027, *2317 not connected to net user_io_oeb\[34\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33038, *2317 not connected to net user_io_oeb\[35\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33052, *2317 not connected to net user_io_oeb\[35\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33063, *2317 not connected to net user_io_oeb\[36\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33080, *2317 not connected to net user_io_oeb\[36\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33091, *2317 not connected to net user_io_oeb\[37\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33102, *2317 not connected to net user_io_oeb\[37\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33113, *2317 not connected to net user_io_oeb\[3\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33125, *2317 not connected to net user_io_oeb\[3\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33136, *2317 not connected to net user_io_oeb\[4\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33151, *2317 not connected to net user_io_oeb\[4\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33162, *2317 not connected to net user_io_oeb\[5\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33179, *2317 not connected to net user_io_oeb\[5\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33190, *2317 not connected to net user_io_oeb\[6\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33204, *2317 not connected to net user_io_oeb\[6\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33217, *2317 not connected to net user_io_oeb\[7\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33243, *2317 not connected to net user_io_oeb\[7\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33256, *2317 not connected to net user_io_oeb\[8\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33277, *2317 not connected to net user_io_oeb\[8\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33290, *2317 not connected to net user_io_oeb\[9\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33313, *2317 not connected to net user_io_oeb\[9\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33326, *2317 not connected to net user_io_out\[0\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33340, *2317 not connected to net user_io_out\[0\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33351, *2317 not connected to net user_io_out\[10\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33373, *2317 not connected to net user_io_out\[10\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33386, *2317 not connected to net user_io_out\[11\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33416, *2317 not connected to net user_io_out\[11\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33429, *2317 not connected to net user_io_out\[12\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33447, *2317 not connected to net user_io_out\[12\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33460, *2317 not connected to net user_io_out\[13\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33468, *2317 not connected to net user_io_out\[13\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33479, *2317 not connected to net user_io_out\[14\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33495, *2317 not connected to net user_io_out\[14\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33506, *2317 not connected to net user_io_out\[15\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33515, *2317 not connected to net user_io_out\[15\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33525, *2317 not connected to net user_io_out\[16\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33532, *2317 not connected to net user_io_out\[16\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33542, *2317 not connected to net user_io_out\[17\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33545, *2317 not connected to net user_io_out\[17\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33554, *2317 not connected to net user_io_out\[18\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33559, *2317 not connected to net user_io_out\[18\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33569, *2317 not connected to net user_io_out\[19\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33580, *2317 not connected to net user_io_out\[19\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33591, *2317 not connected to net user_io_out\[1\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33606, *2317 not connected to net user_io_out\[1\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33619, *2317 not connected to net user_io_out\[20\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33628, *2317 not connected to net user_io_out\[20\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33639, *2317 not connected to net user_io_out\[21\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33646, *2317 not connected to net user_io_out\[21\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33656, *2317 not connected to net user_io_out\[22\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33666, *2317 not connected to net user_io_out\[22\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33676, *2317 not connected to net user_io_out\[23\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33693, *2317 not connected to net user_io_out\[23\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33706, *2317 not connected to net user_io_out\[24\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33711, *2317 not connected to net user_io_out\[24\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33721, *2317 not connected to net user_io_out\[25\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33732, *2317 not connected to net user_io_out\[25\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33743, *2317 not connected to net user_io_out\[26\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33754, *2317 not connected to net user_io_out\[26\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33765, *2317 not connected to net user_io_out\[27\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33778, *2317 not connected to net user_io_out\[27\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33789, *2317 not connected to net user_io_out\[28\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33802, *2317 not connected to net user_io_out\[28\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33813, *2317 not connected to net user_io_out\[29\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33827, *2317 not connected to net user_io_out\[29\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33838, *2317 not connected to net user_io_out\[2\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33851, *2317 not connected to net user_io_out\[2\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33862, *2317 not connected to net user_io_out\[30\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33877, *2317 not connected to net user_io_out\[30\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33888, *2317 not connected to net user_io_out\[31\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33900, *2317 not connected to net user_io_out\[31\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33911, *2317 not connected to net user_io_out\[32\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33927, *2317 not connected to net user_io_out\[32\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33938, *2317 not connected to net user_io_out\[33\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33952, *2317 not connected to net user_io_out\[33\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33963, *2317 not connected to net user_io_out\[34\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33977, *2317 not connected to net user_io_out\[34\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33988, *2317 not connected to net user_io_out\[35\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 33999, *2317 not connected to net user_io_out\[35\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34010, *2317 not connected to net user_io_out\[36\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34023, *2317 not connected to net user_io_out\[36\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34034, *2317 not connected to net user_io_out\[37\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34046, *2317 not connected to net user_io_out\[37\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34057, *2317 not connected to net user_io_out\[3\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34068, *2317 not connected to net user_io_out\[3\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34079, *2317 not connected to net user_io_out\[4\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34091, *2317 not connected to net user_io_out\[4\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34094, *2317 not connected to net user_io_out\[4\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34103, *2317 not connected to net user_io_out\[5\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34115, *2317 not connected to net user_io_out\[5\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34126, *2317 not connected to net user_io_out\[6\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34148, *2317 not connected to net user_io_out\[6\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34160, *2317 not connected to net user_io_out\[7\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34171, *2317 not connected to net user_io_out\[7\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34182, *2317 not connected to net user_io_out\[8\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34193, *2317 not connected to net user_io_out\[8\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34204, *2317 not connected to net user_io_out\[9\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34213, *2317 not connected to net user_io_out\[9\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34310, *2317 not connected to net user_irq_core\[0\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34322, *2317 not connected to net user_irq_core\[0\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34357, *2317 not connected to net user_irq_core\[2\]. |
| Warning: /home/kareem_farid/gf180.new/caravel/caravel/spef/caravel_nom.spef line 34369, *2317 not connected to net user_irq_core\[2\]. |
| read_sdc -echo /home/kareem_farid/gf180.new/caravel/caravel/sdc/caravel.sdc |
| set ::env(IO_PCT) "0.2" |
| set ::env(SYNTH_MAX_FANOUT) "5" |
| set ::env(SYNTH_CAP_LOAD) "72.91" |
| set ::env(SYNTH_TIMING_DERATE) 0.05 |
| set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.25 |
| set ::env(SYNTH_CLOCK_TRANSITION) 0.15 |
| ## MASTER CLOCKS |
| create_clock [get_ports {"clock"} ] -name "clock" -period 25 |
| set_propagated_clock [get_clocks {"clock"}] |
| ## INPUT/OUTPUT DELAYS |
| set input_delay_value 1 |
| set output_delay_value [expr 25 * $::env(IO_PCT)] |
| puts "\[INFO\]: Setting output delay to: $output_delay_value" |
| [INFO]: Setting output delay to: 5.0 |
| puts "\[INFO\]: Setting input delay to: $input_delay_value" |
| [INFO]: Setting input delay to: 1 |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {gpio}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[0]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[1]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[2]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[3]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[4]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[5]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[6]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[7]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[8]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[9]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[10]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[11]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[12]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[13]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[14]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[15]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[16]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[17]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[18]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[19]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[20]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}] |
| set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}] |
| set_output_delay 4.5 -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}] |
| set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}] |
| set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}] |
| set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}] |
| set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design] |
| ## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled |
| # set_case_analysis 0 [get_pins housekeeping/_4449_/S] |
| # set_case_analysis 0 [get_pins housekeeping/_4450_/S] |
| ## FALSE PATHS (ASYNCHRONOUS INPUTS) |
| set_false_path -from [get_ports {resetb}] |
| set_false_path -from [get_ports mprj_io[*]] |
| set_false_path -from [get_ports gpio] |
| # TODO set this as parameter |
| set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] |
| puts "\[INFO\]: Setting load to: $cap_load" |
| [INFO]: Setting load to: 0.07291 |
| set_load $cap_load [all_outputs] |
| puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" |
| [INFO]: Setting timing derate to: 0.5 % |
| set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] |
| set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] |
| puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)" |
| [INFO]: Setting clock uncertainity to: 0.25 |
| set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {clock}] |
| puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)" |
| [INFO]: Setting clock transition to: 0.15 |
| set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}] |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11221_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.70 0.14 16.69 ^ housekeeping/_11221_/RN (DFFRNQ_X1_7T5P0) |
| 16.69 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 3.51 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.46 3.97 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 3.97 ^ housekeeping/_11221_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.03 clock reconvergence pessimism |
| 0.43 4.45 library removal time |
| 4.45 data required time |
| ----------------------------------------------------------------------------- |
| 4.45 data required time |
| -16.69 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.24 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11224_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.71 0.14 16.70 ^ housekeeping/_11224_/RN (DFFRNQ_X1_7T5P0) |
| 16.70 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 3.51 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.46 3.97 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 3.97 ^ housekeeping/_11224_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.03 clock reconvergence pessimism |
| 0.43 4.45 library removal time |
| 4.45 data required time |
| ----------------------------------------------------------------------------- |
| 4.45 data required time |
| -16.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.24 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11683_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.71 0.14 16.70 ^ housekeeping/_11683_/RN (DFFRNQ_X1_7T5P0) |
| 16.70 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 3.51 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.46 3.97 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 3.97 ^ housekeeping/_11683_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.03 clock reconvergence pessimism |
| 0.43 4.46 library removal time |
| 4.46 data required time |
| ----------------------------------------------------------------------------- |
| 4.46 data required time |
| -16.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.24 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11257_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.71 0.14 16.70 ^ housekeeping/_11257_/RN (DFFRNQ_X1_7T5P0) |
| 16.70 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 3.51 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.46 3.97 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 3.98 ^ housekeeping/_11257_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.23 clock uncertainty |
| -0.20 4.03 clock reconvergence pessimism |
| 0.43 4.46 library removal time |
| 4.46 data required time |
| ----------------------------------------------------------------------------- |
| 4.46 data required time |
| -16.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.24 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11258_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.14 16.70 ^ housekeeping/_11258_/RN (DFFRNQ_X1_7T5P0) |
| 16.70 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 3.51 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.46 3.97 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.01 3.98 ^ housekeeping/_11258_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.23 clock uncertainty |
| -0.20 4.03 clock reconvergence pessimism |
| 0.43 4.46 library removal time |
| 4.46 data required time |
| ----------------------------------------------------------------------------- |
| 4.46 data required time |
| -16.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.25 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11223_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.15 16.70 ^ housekeeping/_11223_/RN (DFFRNQ_X1_7T5P0) |
| 16.70 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 3.51 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.46 3.97 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 3.98 ^ housekeeping/_11223_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.23 clock uncertainty |
| -0.20 4.03 clock reconvergence pessimism |
| 0.43 4.46 library removal time |
| 4.46 data required time |
| ----------------------------------------------------------------------------- |
| 4.46 data required time |
| -16.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.25 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11205_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.71 0.14 16.70 ^ housekeeping/_11205_/RN (DFFRNQ_X2_7T5P0) |
| 16.70 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 3.51 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.46 3.97 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 3.97 ^ housekeeping/_11205_/CLK (DFFRNQ_X2_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.03 clock reconvergence pessimism |
| 0.42 4.45 library removal time |
| 4.45 data required time |
| ----------------------------------------------------------------------------- |
| 4.45 data required time |
| -16.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.25 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11684_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.15 16.70 ^ housekeeping/_11684_/RN (DFFRNQ_X1_7T5P0) |
| 16.70 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.00 3.96 ^ housekeeping/_11684_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.21 clock uncertainty |
| -0.20 4.01 clock reconvergence pessimism |
| 0.42 4.43 library removal time |
| 4.43 data required time |
| ----------------------------------------------------------------------------- |
| 4.43 data required time |
| -16.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.27 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11259_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.15 16.71 ^ housekeeping/_11259_/RN (DFFRNQ_X1_7T5P0) |
| 16.71 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.00 3.96 ^ housekeeping/_11259_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.21 clock uncertainty |
| -0.20 4.01 clock reconvergence pessimism |
| 0.42 4.43 library removal time |
| 4.43 data required time |
| ----------------------------------------------------------------------------- |
| 4.43 data required time |
| -16.71 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.27 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11225_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.15 16.71 ^ housekeeping/_11225_/RN (DFFRNQ_X1_7T5P0) |
| 16.71 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.00 3.96 ^ housekeeping/_11225_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.21 clock uncertainty |
| -0.20 4.01 clock reconvergence pessimism |
| 0.42 4.43 library removal time |
| 4.43 data required time |
| ----------------------------------------------------------------------------- |
| 4.43 data required time |
| -16.71 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.27 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11677_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.74 0.16 16.72 ^ housekeeping/_11677_/RN (DFFRNQ_X1_7T5P0) |
| 16.72 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 3.97 ^ housekeeping/_11677_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.42 4.44 library removal time |
| 4.44 data required time |
| ----------------------------------------------------------------------------- |
| 4.44 data required time |
| -16.72 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11254_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.17 16.72 ^ housekeeping/_11254_/RN (DFFRNQ_X1_7T5P0) |
| 16.72 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 3.97 ^ housekeeping/_11254_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.43 4.44 library removal time |
| 4.44 data required time |
| ----------------------------------------------------------------------------- |
| 4.44 data required time |
| -16.72 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11255_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.17 16.72 ^ housekeeping/_11255_/RN (DFFRNQ_X1_7T5P0) |
| 16.72 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 3.97 ^ housekeeping/_11255_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.43 4.44 library removal time |
| 4.44 data required time |
| ----------------------------------------------------------------------------- |
| 4.44 data required time |
| -16.72 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11681_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.17 16.73 ^ housekeeping/_11681_/RN (DFFRNQ_X1_7T5P0) |
| 16.73 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.02 3.97 ^ housekeeping/_11681_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.43 4.45 library removal time |
| 4.45 data required time |
| ----------------------------------------------------------------------------- |
| 4.45 data required time |
| -16.73 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11678_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.17 16.73 ^ housekeeping/_11678_/RN (DFFRNQ_X1_7T5P0) |
| 16.73 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.02 3.97 ^ housekeeping/_11678_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.43 4.45 library removal time |
| 4.45 data required time |
| ----------------------------------------------------------------------------- |
| 4.45 data required time |
| -16.73 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11679_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.17 16.73 ^ housekeeping/_11679_/RN (DFFRNQ_X1_7T5P0) |
| 16.73 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.02 3.97 ^ housekeeping/_11679_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.43 4.45 library removal time |
| 4.45 data required time |
| ----------------------------------------------------------------------------- |
| 4.45 data required time |
| -16.73 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11680_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.17 16.73 ^ housekeeping/_11680_/RN (DFFRNQ_X1_7T5P0) |
| 16.73 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.02 3.97 ^ housekeeping/_11680_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.43 4.45 library removal time |
| 4.45 data required time |
| ----------------------------------------------------------------------------- |
| 4.45 data required time |
| -16.73 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11676_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.17 16.73 ^ housekeeping/_11676_/RN (DFFRNQ_X1_7T5P0) |
| 16.73 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.02 3.97 ^ housekeeping/_11676_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.43 4.44 library removal time |
| 4.44 data required time |
| ----------------------------------------------------------------------------- |
| 4.44 data required time |
| -16.73 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11675_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.17 16.72 ^ housekeeping/_11675_/RN (DFFRNQ_X1_7T5P0) |
| 16.72 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 3.97 ^ housekeeping/_11675_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.22 clock uncertainty |
| -0.20 4.02 clock reconvergence pessimism |
| 0.43 4.44 library removal time |
| 4.44 data required time |
| ----------------------------------------------------------------------------- |
| 4.44 data required time |
| -16.72 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11260_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.65 0.10 16.66 ^ housekeeping/_11260_/RN (DFFRNQ_X1_7T5P0) |
| 16.66 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 3.48 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.90 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 3.91 ^ housekeeping/_11260_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.16 clock uncertainty |
| -0.20 3.96 clock reconvergence pessimism |
| 0.41 4.37 library removal time |
| 4.37 data required time |
| ----------------------------------------------------------------------------- |
| 4.37 data required time |
| -16.66 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11217_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.69 0.13 16.68 ^ housekeeping/_11217_/RN (DFFRNQ_X1_7T5P0) |
| 16.68 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.02 3.50 ^ housekeeping/clkbuf_3_5__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.92 ^ housekeeping/clkbuf_3_5__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 38 0.18 housekeeping/clknet_3_5__leaf_wb_clk_i (net) |
| 0.23 0.01 3.93 ^ housekeeping/_11217_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.18 clock uncertainty |
| -0.20 3.99 clock reconvergence pessimism |
| 0.42 4.40 library removal time |
| 4.40 data required time |
| ----------------------------------------------------------------------------- |
| 4.40 data required time |
| -16.68 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11682_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.74 0.16 16.72 ^ housekeeping/_11682_/RN (DFFRNQ_X1_7T5P0) |
| 16.72 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.04 3.51 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.44 3.95 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.00 3.96 ^ housekeeping/_11682_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.21 clock uncertainty |
| -0.20 4.01 clock reconvergence pessimism |
| 0.42 4.43 library removal time |
| 4.43 data required time |
| ----------------------------------------------------------------------------- |
| 4.43 data required time |
| -16.72 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.28 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11220_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.70 0.13 16.69 ^ housekeeping/_11220_/RN (DFFRNQ_X1_7T5P0) |
| 16.69 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.02 3.50 ^ housekeeping/clkbuf_3_5__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.92 ^ housekeeping/clkbuf_3_5__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 38 0.18 housekeeping/clknet_3_5__leaf_wb_clk_i (net) |
| 0.23 0.01 3.93 ^ housekeeping/_11220_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.18 clock uncertainty |
| -0.20 3.99 clock reconvergence pessimism |
| 0.42 4.40 library removal time |
| 4.40 data required time |
| ----------------------------------------------------------------------------- |
| 4.40 data required time |
| -16.69 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.29 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11256_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.67 0.11 16.67 ^ housekeeping/_11256_/RN (DFFRNQ_X1_7T5P0) |
| 16.67 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 3.48 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.90 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 3.91 ^ housekeeping/_11256_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.16 clock uncertainty |
| -0.20 3.96 clock reconvergence pessimism |
| 0.41 4.37 library removal time |
| 4.37 data required time |
| ----------------------------------------------------------------------------- |
| 4.37 data required time |
| -16.67 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.29 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11666_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.68 0.12 16.67 ^ housekeeping/_11666_/RN (DFFRNQ_X1_7T5P0) |
| 16.67 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 3.48 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.90 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 3.91 ^ housekeeping/_11666_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.16 clock uncertainty |
| -0.20 3.96 clock reconvergence pessimism |
| 0.41 4.38 library removal time |
| 4.38 data required time |
| ----------------------------------------------------------------------------- |
| 4.38 data required time |
| -16.67 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.30 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11219_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.68 0.12 16.67 ^ housekeeping/_11219_/RN (DFFRNQ_X1_7T5P0) |
| 16.67 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 3.48 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.90 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 3.91 ^ housekeeping/_11219_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.16 clock uncertainty |
| -0.20 3.96 clock reconvergence pessimism |
| 0.41 4.38 library removal time |
| 4.38 data required time |
| ----------------------------------------------------------------------------- |
| 4.38 data required time |
| -16.67 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.30 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11218_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.69 0.12 16.68 ^ housekeeping/_11218_/RN (DFFRNQ_X1_7T5P0) |
| 16.68 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 3.48 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.90 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 3.91 ^ housekeeping/_11218_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.16 clock uncertainty |
| -0.20 3.96 clock reconvergence pessimism |
| 0.42 4.38 library removal time |
| 4.38 data required time |
| ----------------------------------------------------------------------------- |
| 4.38 data required time |
| -16.68 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.30 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11222_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.69 0.13 16.68 ^ housekeeping/_11222_/RN (DFFRNQ_X1_7T5P0) |
| 16.68 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 3.48 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.90 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 3.91 ^ housekeeping/_11222_/CLK (DFFRNQ_X1_7T5P0) |
| 0.25 4.16 clock uncertainty |
| -0.20 3.96 clock reconvergence pessimism |
| 0.42 4.38 library removal time |
| 4.38 data required time |
| ----------------------------------------------------------------------------- |
| 4.38 data required time |
| -16.68 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.31 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11216_ (removal check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.92 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.79 13.29 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.29 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.36 13.65 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.65 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.35 13.99 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 13.99 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.39 14.39 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.39 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.80 15.19 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.19 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.38 0.27 15.46 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.38 0.00 15.46 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.41 15.87 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 15.87 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.24 16.11 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.11 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.45 16.56 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.69 0.13 16.68 ^ housekeeping/_11216_/SETN (DFFSNQ_X1_7T5P0) |
| 16.68 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.64 3.48 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 3.48 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.42 3.90 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 3.91 ^ housekeeping/_11216_/CLK (DFFSNQ_X1_7T5P0) |
| 0.25 4.16 clock uncertainty |
| -0.20 3.96 clock reconvergence pessimism |
| 0.17 4.13 library removal time |
| 4.13 data required time |
| ----------------------------------------------------------------------------- |
| 4.13 data required time |
| -16.68 data arrival time |
| ----------------------------------------------------------------------------- |
| 12.55 slack (MET) |
| |
| |
| Startpoint: soc/_43032_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44478_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_22_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_22_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_22_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_45_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.38 5.86 ^ soc/clkbuf_6_45_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 10 0.15 soc/clknet_6_45_0_core_clk (net) |
| 0.34 0.00 5.86 ^ soc/clkbuf_leaf_418_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 6.14 ^ soc/clkbuf_leaf_418_core_clk/Z (CLKBUF_X16_7T5P0) |
| 9 0.05 soc/clknet_leaf_418_core_clk (net) |
| 0.12 0.00 6.14 ^ soc/_43032_/CLK (DFFQ_X1_7T5P0) |
| 0.23 0.71 6.85 v soc/_43032_/Q (DFFQ_X1_7T5P0) |
| 2 0.02 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[29] (net) |
| 0.23 0.00 6.85 v soc/_34607_/A1 (NAND2_X1_7T5P0) |
| 0.18 0.16 7.01 ^ soc/_34607_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_14586_ (net) |
| 0.18 0.00 7.01 ^ soc/_34609_/B1 (AOI22_X1_7T5P0) |
| 0.17 0.14 7.15 v soc/_34609_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02548_ (net) |
| 0.17 0.00 7.15 v soc/_44478_/D (DFFQ_X1_7T5P0) |
| 7.15 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.75 7.37 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.01 7.38 ^ soc/clkbuf_opt_31_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.42 7.80 ^ soc/clkbuf_opt_31_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.09 soc/clknet_opt_31_0_core_clk (net) |
| 0.17 0.01 7.81 ^ soc/clkbuf_leaf_417_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.32 8.13 ^ soc/clkbuf_leaf_417_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.12 soc/clknet_leaf_417_core_clk (net) |
| 0.17 0.00 8.13 ^ soc/_44478_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.38 clock uncertainty |
| -0.46 7.92 clock reconvergence pessimism |
| 0.08 8.00 library hold time |
| 8.00 data required time |
| ----------------------------------------------------------------------------- |
| 8.00 data required time |
| -7.15 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.85 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43643_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43879_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 3.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 4.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 4.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 4.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 4.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 4.94 ^ soc/clkbuf_5_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.24 ^ soc/clkbuf_5_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_5_0_core_clk (net) |
| 0.19 0.00 5.24 ^ soc/clkbuf_6_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.54 0.49 5.74 ^ soc/clkbuf_6_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.25 soc/clknet_6_10_0_core_clk (net) |
| 0.54 0.01 5.74 ^ soc/clkbuf_leaf_276_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.32 6.06 ^ soc/clkbuf_leaf_276_core_clk/Z (CLKBUF_X16_7T5P0) |
| 8 0.06 soc/clknet_leaf_276_core_clk (net) |
| 0.13 0.00 6.06 ^ soc/_43643_/CLK (DFFQ_X1_7T5P0) |
| 0.17 0.67 6.73 v soc/_43643_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.VexRiscv.lastStagePc[6] (net) |
| 0.17 0.00 6.73 v soc/_22234_/A1 (OAI211_X1_7T5P0) |
| 0.45 0.33 7.07 ^ soc/_22234_/ZN (OAI211_X1_7T5P0) |
| 1 0.01 soc/_04904_ (net) |
| 0.45 0.00 7.07 ^ soc/_22235_/B (OAI21_X1_7T5P0) |
| 0.19 0.14 7.21 v soc/_22235_/ZN (OAI21_X1_7T5P0) |
| 1 0.00 soc/_04905_ (net) |
| 0.19 0.00 7.21 v soc/_22236_/I (CLKBUF_X1_7T5P0) |
| 0.10 0.20 7.40 v soc/_22236_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_00125_ (net) |
| 0.10 0.00 7.40 v soc/_43879_/D (DFFQ_X1_7T5P0) |
| 7.40 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.41 6.17 ^ soc/clkbuf_4_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_4_9_0_core_clk (net) |
| 0.18 0.00 6.17 ^ soc/clkbuf_5_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.35 0.43 6.60 ^ soc/clkbuf_5_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.16 soc/clknet_5_19_0_core_clk (net) |
| 0.35 0.01 6.61 ^ soc/clkbuf_6_38_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.47 0.54 7.15 ^ soc/clkbuf_6_38_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 10 0.21 soc/clknet_6_38_0_core_clk (net) |
| 0.47 0.00 7.15 ^ soc/clkbuf_opt_36_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.10 0.32 7.47 ^ soc/clkbuf_opt_36_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 1 0.03 soc/clknet_opt_36_0_core_clk (net) |
| 0.10 0.00 7.47 ^ soc/clkbuf_opt_36_1_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.30 7.77 ^ soc/clkbuf_opt_36_1_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.12 soc/clknet_opt_36_1_core_clk (net) |
| 0.18 0.01 7.78 ^ soc/clkbuf_leaf_277_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.28 8.07 ^ soc/clkbuf_leaf_277_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_277_core_clk (net) |
| 0.13 0.00 8.07 ^ soc/_43879_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.32 clock uncertainty |
| -0.31 8.01 clock reconvergence pessimism |
| 0.09 8.10 library hold time |
| 8.10 data required time |
| ----------------------------------------------------------------------------- |
| 8.10 data required time |
| -7.40 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.70 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45852_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44479_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_419_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.34 6.29 ^ soc/clkbuf_leaf_419_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_419_core_clk (net) |
| 0.17 0.00 6.29 ^ soc/_45852_/CLK (DFFQ_X1_7T5P0) |
| 0.16 0.67 6.96 v soc/_45852_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.mgmtsoc_vexriscv_i_cmd_payload_data[30] (net) |
| 0.16 0.00 6.96 v soc/_34610_/I (CLKINV_X1_7T5P0) |
| 0.34 0.23 7.19 ^ soc/_34610_/ZN (CLKINV_X1_7T5P0) |
| 1 0.02 soc/_14588_ (net) |
| 0.34 0.00 7.19 ^ soc/_34613_/A1 (AOI22_X1_7T5P0) |
| 0.18 0.14 7.33 v soc/_34613_/ZN (AOI22_X1_7T5P0) |
| 1 0.01 soc/_02549_ (net) |
| 0.18 0.00 7.33 v soc/_44479_/D (DFFQ_X1_7T5P0) |
| 7.33 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.75 7.37 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.01 7.38 ^ soc/clkbuf_opt_31_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.42 7.80 ^ soc/clkbuf_opt_31_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.09 soc/clknet_opt_31_0_core_clk (net) |
| 0.17 0.01 7.81 ^ soc/clkbuf_leaf_417_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.32 8.13 ^ soc/clkbuf_leaf_417_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.12 soc/clknet_leaf_417_core_clk (net) |
| 0.17 0.00 8.13 ^ soc/_44479_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.38 clock uncertainty |
| -0.46 7.92 clock reconvergence pessimism |
| 0.08 8.00 library hold time |
| 8.00 data required time |
| ----------------------------------------------------------------------------- |
| 8.00 data required time |
| -7.33 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.67 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43029_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44475_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_22_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_22_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_22_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_44_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.57 0.51 5.98 ^ soc/clkbuf_6_44_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.27 soc/clknet_6_44_0_core_clk (net) |
| 0.57 0.00 5.98 ^ soc/clkbuf_leaf_431_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.11 0.30 6.29 ^ soc/clkbuf_leaf_431_core_clk/Z (CLKBUF_X16_7T5P0) |
| 5 0.03 soc/clknet_leaf_431_core_clk (net) |
| 0.11 0.00 6.29 ^ soc/_43029_/CLK (DFFQ_X1_7T5P0) |
| 0.19 0.68 6.97 v soc/_43029_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[26] (net) |
| 0.19 0.00 6.97 v soc/_34595_/A1 (NAND2_X1_7T5P0) |
| 0.23 0.19 7.16 ^ soc/_34595_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_14577_ (net) |
| 0.23 0.00 7.16 ^ soc/_34597_/B1 (AOI22_X1_7T5P0) |
| 0.15 0.15 7.31 v soc/_34597_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02545_ (net) |
| 0.15 0.00 7.31 v soc/_44475_/D (DFFQ_X1_7T5P0) |
| 7.31 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.42 6.65 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 6.66 ^ soc/clkbuf_6_33_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.58 0.60 7.26 ^ soc/clkbuf_6_33_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 10 0.27 soc/clknet_6_33_0_core_clk (net) |
| 0.58 0.01 7.26 ^ soc/clkbuf_opt_24_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.40 7.66 ^ soc/clkbuf_opt_24_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.11 soc/clknet_opt_24_0_core_clk (net) |
| 0.18 0.00 7.66 ^ soc/clkbuf_leaf_416_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 7.94 ^ soc/clkbuf_leaf_416_core_clk/Z (CLKBUF_X16_7T5P0) |
| 9 0.06 soc/clknet_leaf_416_core_clk (net) |
| 0.12 0.00 7.94 ^ soc/_44475_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.19 clock uncertainty |
| -0.46 7.74 clock reconvergence pessimism |
| 0.08 7.81 library hold time |
| 7.81 data required time |
| ----------------------------------------------------------------------------- |
| 7.81 data required time |
| -7.31 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.51 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_44952_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44956_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 3.97 ^ soc/clkbuf_3_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.10 0.24 4.21 ^ soc/clkbuf_3_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_0_0_core_clk (net) |
| 0.10 0.00 4.21 ^ soc/clkbuf_3_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.27 4.49 ^ soc/clkbuf_3_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_3_0_1_core_clk (net) |
| 0.18 0.00 4.49 ^ soc/clkbuf_4_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.25 4.73 ^ soc/clkbuf_4_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.03 soc/clknet_4_1_0_core_clk (net) |
| 0.12 0.00 4.74 ^ soc/clkbuf_5_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 5.02 ^ soc/clkbuf_5_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_3_0_core_clk (net) |
| 0.19 0.00 5.02 ^ soc/clkbuf_6_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.57 0.51 5.54 ^ soc/clkbuf_6_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.27 soc/clknet_6_6_0_core_clk (net) |
| 0.57 0.01 5.54 ^ soc/clkbuf_leaf_115_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.35 5.89 ^ soc/clkbuf_leaf_115_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.10 soc/clknet_leaf_115_core_clk (net) |
| 0.17 0.00 5.89 ^ soc/_44952_/CLK (DFFQ_X1_7T5P0) |
| 0.16 0.72 6.61 ^ soc/_44952_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.gpioin1_gpioin1_trigger_d (net) |
| 0.16 0.00 6.61 ^ soc/_36438_/A2 (OAI31_X1_7T5P0) |
| 0.19 0.17 6.78 v soc/_36438_/ZN (OAI31_X1_7T5P0) |
| 1 0.01 soc/_02885_ (net) |
| 0.19 0.00 6.78 v soc/_44956_/D (DFFQ_X1_7T5P0) |
| 6.78 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.32 4.04 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 4.38 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 4.39 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.28 4.67 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 4.67 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.41 5.08 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 5.09 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 5.51 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 5.52 ^ soc/clkbuf_5_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.38 5.90 ^ soc/clkbuf_5_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_5_6_0_core_clk (net) |
| 0.25 0.00 5.90 ^ soc/clkbuf_6_13_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.56 0.57 6.48 ^ soc/clkbuf_6_13_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.27 soc/clknet_6_13_0_core_clk (net) |
| 0.57 0.01 6.49 ^ soc/clkbuf_opt_18_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.39 6.88 ^ soc/clkbuf_opt_18_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.11 soc/clknet_opt_18_0_core_clk (net) |
| 0.18 0.01 6.89 ^ soc/clkbuf_leaf_117_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.31 7.20 ^ soc/clkbuf_leaf_117_core_clk/Z (CLKBUF_X16_7T5P0) |
| 20 0.10 soc/clknet_leaf_117_core_clk (net) |
| 0.16 0.00 7.20 ^ soc/_44956_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.45 clock uncertainty |
| -0.42 7.03 clock reconvergence pessimism |
| 0.07 7.10 library hold time |
| 7.10 data required time |
| ----------------------------------------------------------------------------- |
| 7.10 data required time |
| -6.78 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.33 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43021_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44467_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 6.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 6.29 ^ soc/_43021_/CLK (DFFQ_X1_7T5P0) |
| 0.49 0.88 7.17 v soc/_43021_/Q (DFFQ_X1_7T5P0) |
| 6 0.05 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[18] (net) |
| 0.49 0.00 7.17 v soc/_34563_/A1 (AOI21_X1_7T5P0) |
| 0.36 0.31 7.48 ^ soc/_34563_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_14553_ (net) |
| 0.36 0.00 7.48 ^ soc/_34564_/B2 (AOI22_X1_7T5P0) |
| 0.13 0.14 7.62 v soc/_34564_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02537_ (net) |
| 0.13 0.00 7.62 v soc/_44467_/D (DFFQ_X1_7T5P0) |
| 7.62 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.75 7.37 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.01 7.38 ^ soc/clkbuf_opt_30_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.43 7.81 ^ soc/clkbuf_opt_30_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.10 soc/clknet_opt_30_0_core_clk (net) |
| 0.18 0.01 7.81 ^ soc/clkbuf_leaf_415_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.09 0.26 8.07 ^ soc/clkbuf_leaf_415_core_clk/Z (CLKBUF_X16_7T5P0) |
| 4 0.03 soc/clknet_leaf_415_core_clk (net) |
| 0.09 0.00 8.07 ^ soc/_44467_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.32 clock uncertainty |
| -0.46 7.86 clock reconvergence pessimism |
| 0.08 7.94 library hold time |
| 7.94 data required time |
| ----------------------------------------------------------------------------- |
| 7.94 data required time |
| -7.62 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.32 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45846_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44473_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_419_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.34 6.29 ^ soc/clkbuf_leaf_419_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_419_core_clk (net) |
| 0.17 0.00 6.30 ^ soc/_45846_/CLK (DFFQ_X1_7T5P0) |
| 0.72 1.02 7.32 v soc/_45846_/Q (DFFQ_X1_7T5P0) |
| 6 0.07 soc/core.VexRiscv.when_DebugPlugin_l260_1 (net) |
| 0.72 0.00 7.32 v soc/_34586_/I (CLKINV_X1_7T5P0) |
| 0.32 0.27 7.59 ^ soc/_34586_/ZN (CLKINV_X1_7T5P0) |
| 1 0.01 soc/_14570_ (net) |
| 0.32 0.00 7.59 ^ soc/_34590_/A1 (AOI22_X1_7T5P0) |
| 0.17 0.13 7.73 v soc/_34590_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02543_ (net) |
| 0.17 0.00 7.73 v soc/_44473_/D (DFFQ_X1_7T5P0) |
| 7.73 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.75 7.37 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.01 7.38 ^ soc/clkbuf_opt_28_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.42 7.79 ^ soc/clkbuf_opt_28_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.09 soc/clknet_opt_28_0_core_clk (net) |
| 0.16 0.01 7.80 ^ soc/clkbuf_leaf_413_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 8.08 ^ soc/clkbuf_leaf_413_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.06 soc/clknet_leaf_413_core_clk (net) |
| 0.12 0.00 8.08 ^ soc/_44473_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.33 clock uncertainty |
| -0.46 7.87 clock reconvergence pessimism |
| 0.07 7.94 library hold time |
| 7.94 data required time |
| ----------------------------------------------------------------------------- |
| 7.94 data required time |
| -7.73 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.22 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43026_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44472_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 6.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 6.29 ^ soc/_43026_/CLK (DFFQ_X1_7T5P0) |
| 0.74 1.03 7.32 v soc/_43026_/Q (DFFQ_X1_7T5P0) |
| 6 0.07 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[23] (net) |
| 0.74 0.00 7.32 v soc/_34584_/A1 (AOI21_X1_7T5P0) |
| 0.39 0.38 7.70 ^ soc/_34584_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_14569_ (net) |
| 0.39 0.00 7.70 ^ soc/_34585_/B2 (AOI22_X1_7T5P0) |
| 0.13 0.15 7.85 v soc/_34585_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02542_ (net) |
| 0.13 0.00 7.85 v soc/_44472_/D (DFFQ_X1_7T5P0) |
| 7.85 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.75 7.37 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.01 7.38 ^ soc/clkbuf_opt_28_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.42 7.79 ^ soc/clkbuf_opt_28_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.09 soc/clknet_opt_28_0_core_clk (net) |
| 0.16 0.01 7.80 ^ soc/clkbuf_leaf_413_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 8.08 ^ soc/clkbuf_leaf_413_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.06 soc/clknet_leaf_413_core_clk (net) |
| 0.12 0.00 8.08 ^ soc/_44472_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.33 clock uncertainty |
| -0.46 7.87 clock reconvergence pessimism |
| 0.08 7.95 library hold time |
| 7.95 data required time |
| ----------------------------------------------------------------------------- |
| 7.95 data required time |
| -7.85 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.11 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_44348_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43493_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 3.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 4.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 4.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 4.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 4.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 4.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 5.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 5.20 ^ soc/clkbuf_6_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.37 0.39 5.60 ^ soc/clkbuf_6_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.17 soc/clknet_6_8_0_core_clk (net) |
| 0.37 0.00 5.60 ^ soc/clkbuf_leaf_53_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 5.89 ^ soc/clkbuf_leaf_53_core_clk/Z (CLKBUF_X16_7T5P0) |
| 8 0.05 soc/clknet_leaf_53_core_clk (net) |
| 0.12 0.00 5.89 ^ soc/_44348_/CLK (DFFQ_X1_7T5P0) |
| 1.32 1.36 7.24 v soc/_44348_/Q (DFFQ_X1_7T5P0) |
| 6 0.13 soc/core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] (net) |
| 1.32 0.01 7.25 v soc/_31411_/I1 (MUX2_X2_7T5P0) |
| 0.12 0.58 7.83 v soc/_31411_/Z (MUX2_X2_7T5P0) |
| 1 0.00 soc/_12286_ (net) |
| 0.12 0.00 7.83 v soc/_31412_/I (CLKBUF_X1_7T5P0) |
| 0.11 0.19 8.02 v soc/_31412_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_01652_ (net) |
| 0.11 0.00 8.02 v soc/_43493_/D (DFFQ_X1_7T5P0) |
| 8.02 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.41 6.17 ^ soc/clkbuf_4_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_4_9_0_core_clk (net) |
| 0.18 0.00 6.17 ^ soc/clkbuf_5_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.35 0.43 6.60 ^ soc/clkbuf_5_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.16 soc/clknet_5_19_0_core_clk (net) |
| 0.35 0.01 6.61 ^ soc/clkbuf_6_38_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.47 0.54 7.15 ^ soc/clkbuf_6_38_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 10 0.21 soc/clknet_6_38_0_core_clk (net) |
| 0.47 0.00 7.15 ^ soc/clkbuf_opt_36_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.10 0.32 7.47 ^ soc/clkbuf_opt_36_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 1 0.03 soc/clknet_opt_36_0_core_clk (net) |
| 0.10 0.00 7.47 ^ soc/clkbuf_opt_36_1_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.30 7.77 ^ soc/clkbuf_opt_36_1_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.12 soc/clknet_opt_36_1_core_clk (net) |
| 0.18 0.01 7.78 ^ soc/clkbuf_leaf_277_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.28 8.07 ^ soc/clkbuf_leaf_277_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_277_core_clk (net) |
| 0.13 0.00 8.07 ^ soc/_43493_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.32 clock uncertainty |
| -0.31 8.01 clock reconvergence pessimism |
| 0.09 8.10 library hold time |
| 8.10 data required time |
| ----------------------------------------------------------------------------- |
| 8.10 data required time |
| -8.02 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.08 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_46312_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43415_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_3_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.33 4.55 ^ soc/clkbuf_3_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_3_3_1_core_clk (net) |
| 0.27 0.00 4.56 ^ soc/clkbuf_4_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.88 ^ soc/clkbuf_4_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_6_0_core_clk (net) |
| 0.20 0.00 4.88 ^ soc/clkbuf_5_13_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.29 5.17 ^ soc/clkbuf_5_13_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_13_0_core_clk (net) |
| 0.18 0.00 5.17 ^ soc/clkbuf_6_27_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.69 0.57 5.75 ^ soc/clkbuf_6_27_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.33 soc/clknet_6_27_0_core_clk (net) |
| 0.69 0.01 5.76 ^ soc/clkbuf_leaf_234_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.33 6.09 ^ soc/clkbuf_leaf_234_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.04 soc/clknet_leaf_234_core_clk (net) |
| 0.13 0.00 6.09 ^ soc/_46312_/CLK (DFFQ_X1_7T5P0) |
| 0.23 0.72 6.81 v soc/_46312_/Q (DFFQ_X1_7T5P0) |
| 1 0.02 soc/core.VexRiscv._zz_RegFilePlugin_regFile_port1[25] (net) |
| 0.23 0.00 6.81 v soc/_31205_/I1 (MUX2_X2_7T5P0) |
| 0.13 0.36 7.17 v soc/_31205_/Z (MUX2_X2_7T5P0) |
| 1 0.01 soc/_12158_ (net) |
| 0.13 0.00 7.17 v soc/_31206_/I (CLKBUF_X1_7T5P0) |
| 0.12 0.19 7.36 v soc/_31206_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_01574_ (net) |
| 0.12 0.00 7.36 v soc/_43415_/D (DFFQ_X1_7T5P0) |
| 7.36 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.39 4.45 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 4.45 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.37 4.82 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.02 4.83 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 5.12 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 5.12 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.39 5.51 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 5.52 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.40 5.92 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.00 5.92 ^ soc/clkbuf_5_24_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.42 6.34 ^ soc/clkbuf_5_24_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_24_0_core_clk (net) |
| 0.30 0.01 6.35 ^ soc/clkbuf_6_48_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.61 0.61 6.96 ^ soc/clkbuf_6_48_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.29 soc/clknet_6_48_0_core_clk (net) |
| 0.61 0.01 6.98 ^ soc/clkbuf_leaf_283_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.42 7.40 ^ soc/clkbuf_leaf_283_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.14 soc/clknet_leaf_283_core_clk (net) |
| 0.20 0.00 7.40 ^ soc/_43415_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.65 clock uncertainty |
| -0.31 7.34 clock reconvergence pessimism |
| 0.10 7.44 library hold time |
| 7.44 data required time |
| ----------------------------------------------------------------------------- |
| 7.44 data required time |
| -7.36 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.08 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43024_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44470_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 6.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 6.29 ^ soc/_43024_/CLK (DFFQ_X1_7T5P0) |
| 0.80 1.06 7.35 v soc/_43024_/Q (DFFQ_X1_7T5P0) |
| 6 0.08 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[21] (net) |
| 0.80 0.00 7.36 v soc/_34575_/A1 (NAND2_X1_7T5P0) |
| 0.35 0.33 7.69 ^ soc/_34575_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_14562_ (net) |
| 0.35 0.00 7.69 ^ soc/_34577_/B1 (AOI22_X1_7T5P0) |
| 0.16 0.18 7.87 v soc/_34577_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02540_ (net) |
| 0.16 0.00 7.87 v soc/_44470_/D (DFFQ_X1_7T5P0) |
| 7.87 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.75 7.37 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.01 7.38 ^ soc/clkbuf_opt_28_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.42 7.79 ^ soc/clkbuf_opt_28_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.09 soc/clknet_opt_28_0_core_clk (net) |
| 0.16 0.01 7.80 ^ soc/clkbuf_leaf_413_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 8.08 ^ soc/clkbuf_leaf_413_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.06 soc/clknet_leaf_413_core_clk (net) |
| 0.12 0.00 8.08 ^ soc/_44470_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.33 clock uncertainty |
| -0.46 7.87 clock reconvergence pessimism |
| 0.08 7.95 library hold time |
| 7.95 data required time |
| ----------------------------------------------------------------------------- |
| 7.95 data required time |
| -7.87 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.08 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43019_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44465_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 6.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 6.29 ^ soc/_43019_/CLK (DFFQ_X1_7T5P0) |
| 0.63 0.97 7.26 v soc/_43019_/Q (DFFQ_X1_7T5P0) |
| 6 0.06 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[16] (net) |
| 0.63 0.00 7.26 v soc/_34555_/A1 (AOI21_X1_7T5P0) |
| 0.38 0.35 7.61 ^ soc/_34555_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_14547_ (net) |
| 0.38 0.00 7.61 ^ soc/_34556_/B2 (AOI22_X1_7T5P0) |
| 0.13 0.15 7.76 v soc/_34556_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02535_ (net) |
| 0.13 0.00 7.76 v soc/_44465_/D (DFFQ_X1_7T5P0) |
| 7.76 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.42 6.65 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 6.66 ^ soc/clkbuf_6_33_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.58 0.60 7.26 ^ soc/clkbuf_6_33_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 10 0.27 soc/clknet_6_33_0_core_clk (net) |
| 0.58 0.01 7.26 ^ soc/clkbuf_opt_24_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.40 7.66 ^ soc/clkbuf_opt_24_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.11 soc/clknet_opt_24_0_core_clk (net) |
| 0.18 0.00 7.66 ^ soc/clkbuf_leaf_416_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 7.94 ^ soc/clkbuf_leaf_416_core_clk/Z (CLKBUF_X16_7T5P0) |
| 9 0.06 soc/clknet_leaf_416_core_clk (net) |
| 0.12 0.00 7.94 ^ soc/_44465_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.19 clock uncertainty |
| -0.46 7.74 clock reconvergence pessimism |
| 0.08 7.82 library hold time |
| 7.82 data required time |
| ----------------------------------------------------------------------------- |
| 7.82 data required time |
| -7.76 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.06 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43022_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44468_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 6.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 6.29 ^ soc/_43022_/CLK (DFFQ_X1_7T5P0) |
| 0.82 1.08 7.37 v soc/_43022_/Q (DFFQ_X1_7T5P0) |
| 6 0.08 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[19] (net) |
| 0.82 0.00 7.37 v soc/_34567_/A1 (AOI21_X1_7T5P0) |
| 0.42 0.41 7.78 ^ soc/_34567_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_14556_ (net) |
| 0.42 0.00 7.78 ^ soc/_34568_/B2 (AOI22_X1_7T5P0) |
| 0.12 0.15 7.93 v soc/_34568_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02538_ (net) |
| 0.12 0.00 7.93 v soc/_44468_/D (DFFQ_X1_7T5P0) |
| 7.93 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.75 7.37 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.01 7.38 ^ soc/clkbuf_opt_28_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.42 7.79 ^ soc/clkbuf_opt_28_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.09 soc/clknet_opt_28_0_core_clk (net) |
| 0.16 0.01 7.80 ^ soc/clkbuf_leaf_413_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 8.08 ^ soc/clkbuf_leaf_413_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.06 soc/clknet_leaf_413_core_clk (net) |
| 0.12 0.00 8.08 ^ soc/_44468_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.33 clock uncertainty |
| -0.46 7.87 clock reconvergence pessimism |
| 0.08 7.96 library hold time |
| 7.96 data required time |
| ----------------------------------------------------------------------------- |
| 7.96 data required time |
| -7.93 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.02 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_44495_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_45797_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.35 4.02 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 4.02 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.34 4.36 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.01 4.37 ^ soc/clkbuf_3_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.27 4.64 ^ soc/clkbuf_3_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_7_0_core_clk (net) |
| 0.12 0.00 4.64 ^ soc/clkbuf_3_7_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.33 4.97 ^ soc/clkbuf_3_7_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_3_7_1_core_clk (net) |
| 0.28 0.01 4.98 ^ soc/clkbuf_4_14_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.32 5.30 ^ soc/clkbuf_4_14_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_14_0_core_clk (net) |
| 0.19 0.00 5.30 ^ soc/clkbuf_5_28_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.24 0.32 5.62 ^ soc/clkbuf_5_28_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_28_0_core_clk (net) |
| 0.24 0.00 5.63 ^ soc/clkbuf_6_56_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.76 0.63 6.25 ^ soc/clkbuf_6_56_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.36 soc/clknet_6_56_0_core_clk (net) |
| 0.76 0.01 6.26 ^ soc/clkbuf_leaf_451_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.24 0.42 6.68 ^ soc/clkbuf_leaf_451_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.17 soc/clknet_leaf_451_core_clk (net) |
| 0.24 0.00 6.68 ^ soc/_44495_/CLK (DFFQ_X1_7T5P0) |
| 0.17 0.69 7.37 v soc/_44495_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.VexRiscv.DebugPlugin_busReadDataReg[16] (net) |
| 0.17 0.00 7.37 v soc/_45797_/D (DFFQ_X1_7T5P0) |
| 7.37 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.39 4.45 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 4.45 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.37 4.82 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.02 4.83 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 5.12 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 5.12 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.39 5.51 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 5.52 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.40 5.92 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.01 5.93 ^ soc/clkbuf_5_25_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.29 ^ soc/clkbuf_5_25_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_25_0_core_clk (net) |
| 0.23 0.01 6.30 ^ soc/clkbuf_6_50_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.80 7.10 ^ soc/clkbuf_6_50_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.46 soc/clknet_6_50_0_core_clk (net) |
| 0.95 0.03 7.13 ^ soc/clkbuf_leaf_452_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.40 7.53 ^ soc/clkbuf_leaf_452_core_clk/Z (CLKBUF_X16_7T5P0) |
| 5 0.05 soc/clknet_leaf_452_core_clk (net) |
| 0.13 0.00 7.53 ^ soc/_45797_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.78 clock uncertainty |
| -0.46 7.32 clock reconvergence pessimism |
| 0.07 7.39 library hold time |
| 7.39 data required time |
| ----------------------------------------------------------------------------- |
| 7.39 data required time |
| -7.37 data arrival time |
| ----------------------------------------------------------------------------- |
| -0.02 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43020_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44466_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 6.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 6.29 ^ soc/_43020_/CLK (DFFQ_X1_7T5P0) |
| 0.95 1.15 7.44 v soc/_43020_/Q (DFFQ_X1_7T5P0) |
| 8 0.10 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[17] (net) |
| 0.95 0.00 7.45 v soc/_34558_/A1 (NAND2_X1_7T5P0) |
| 0.33 0.32 7.77 ^ soc/_34558_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_14549_ (net) |
| 0.33 0.00 7.77 ^ soc/_34560_/B1 (AOI22_X1_7T5P0) |
| 0.17 0.16 7.93 v soc/_34560_/ZN (AOI22_X1_7T5P0) |
| 1 0.00 soc/_02536_ (net) |
| 0.17 0.00 7.93 v soc/_44466_/D (DFFQ_X1_7T5P0) |
| 7.93 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.75 7.37 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.01 7.38 ^ soc/clkbuf_opt_30_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.43 7.81 ^ soc/clkbuf_opt_30_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.10 soc/clknet_opt_30_0_core_clk (net) |
| 0.18 0.01 7.81 ^ soc/clkbuf_leaf_415_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.09 0.26 8.07 ^ soc/clkbuf_leaf_415_core_clk/Z (CLKBUF_X16_7T5P0) |
| 4 0.03 soc/clknet_leaf_415_core_clk (net) |
| 0.09 0.00 8.07 ^ soc/_44466_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.32 clock uncertainty |
| -0.46 7.86 clock reconvergence pessimism |
| 0.07 7.93 library hold time |
| 7.93 data required time |
| ----------------------------------------------------------------------------- |
| 7.93 data required time |
| -7.93 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.00 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_44909_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44951_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 3.97 ^ soc/clkbuf_3_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.10 0.24 4.21 ^ soc/clkbuf_3_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_0_0_core_clk (net) |
| 0.10 0.00 4.21 ^ soc/clkbuf_3_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.27 4.49 ^ soc/clkbuf_3_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_3_0_1_core_clk (net) |
| 0.18 0.00 4.49 ^ soc/clkbuf_4_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.25 4.73 ^ soc/clkbuf_4_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.03 soc/clknet_4_1_0_core_clk (net) |
| 0.12 0.00 4.74 ^ soc/clkbuf_5_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 5.02 ^ soc/clkbuf_5_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_3_0_core_clk (net) |
| 0.19 0.00 5.02 ^ soc/clkbuf_6_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.71 0.59 5.61 ^ soc/clkbuf_6_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.34 soc/clknet_6_7_0_core_clk (net) |
| 0.72 0.01 5.63 ^ soc/clkbuf_leaf_116_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.33 5.96 ^ soc/clkbuf_leaf_116_core_clk/Z (CLKBUF_X16_7T5P0) |
| 5 0.04 soc/clknet_leaf_116_core_clk (net) |
| 0.12 0.00 5.96 ^ soc/_44909_/CLK (DFFQ_X1_7T5P0) |
| 0.15 0.70 6.66 ^ soc/_44909_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.gpioin2_pending_re (net) |
| 0.15 0.00 6.66 ^ soc/_36420_/A2 (NAND2_X1_7T5P0) |
| 0.13 0.11 6.77 v soc/_36420_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_16067_ (net) |
| 0.13 0.00 6.77 v soc/_36421_/A3 (NAND3_X1_7T5P0) |
| 0.25 0.22 6.99 ^ soc/_36421_/ZN (NAND3_X1_7T5P0) |
| 1 0.01 soc/_16068_ (net) |
| 0.25 0.00 6.99 ^ soc/_36422_/B (OAI31_X1_7T5P0) |
| 0.22 0.17 7.16 v soc/_36422_/ZN (OAI31_X1_7T5P0) |
| 1 0.01 soc/_02880_ (net) |
| 0.22 0.00 7.16 v soc/_44951_/D (DFFQ_X1_7T5P0) |
| 7.16 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.32 4.04 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 4.38 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 4.39 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.28 4.67 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 4.67 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.41 5.08 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 5.09 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 5.51 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 5.52 ^ soc/clkbuf_5_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.38 5.90 ^ soc/clkbuf_5_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_5_6_0_core_clk (net) |
| 0.25 0.00 5.90 ^ soc/clkbuf_6_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.55 0.56 6.47 ^ soc/clkbuf_6_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.26 soc/clknet_6_12_0_core_clk (net) |
| 0.55 0.01 6.48 ^ soc/clkbuf_opt_17_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.39 6.87 ^ soc/clkbuf_opt_17_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.11 soc/clknet_opt_17_0_core_clk (net) |
| 0.18 0.01 6.87 ^ soc/clkbuf_leaf_102_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.19 0.33 7.20 ^ soc/clkbuf_leaf_102_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.14 soc/clknet_leaf_102_core_clk (net) |
| 0.19 0.01 7.21 ^ soc/_44951_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.46 clock uncertainty |
| -0.42 7.04 clock reconvergence pessimism |
| 0.07 7.11 library hold time |
| 7.11 data required time |
| ----------------------------------------------------------------------------- |
| 7.11 data required time |
| -7.16 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.05 slack (MET) |
| |
| |
| Startpoint: soc/_45815_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_45813_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 3.97 ^ soc/clkbuf_3_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.10 0.24 4.21 ^ soc/clkbuf_3_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_0_0_core_clk (net) |
| 0.10 0.00 4.21 ^ soc/clkbuf_3_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.27 4.49 ^ soc/clkbuf_3_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_3_0_1_core_clk (net) |
| 0.18 0.00 4.49 ^ soc/clkbuf_4_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.25 4.73 ^ soc/clkbuf_4_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.03 soc/clknet_4_1_0_core_clk (net) |
| 0.12 0.00 4.74 ^ soc/clkbuf_5_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 5.02 ^ soc/clkbuf_5_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_3_0_core_clk (net) |
| 0.19 0.00 5.02 ^ soc/clkbuf_6_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.57 0.51 5.54 ^ soc/clkbuf_6_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.27 soc/clknet_6_6_0_core_clk (net) |
| 0.57 0.00 5.54 ^ soc/clkbuf_leaf_91_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.11 0.30 5.84 ^ soc/clkbuf_leaf_91_core_clk/Z (CLKBUF_X16_7T5P0) |
| 6 0.03 soc/clknet_leaf_91_core_clk (net) |
| 0.11 0.00 5.84 ^ soc/_45815_/CLK (DFFQ_X1_7T5P0) |
| 0.29 0.75 6.59 v soc/_45815_/Q (DFFQ_X1_7T5P0) |
| 4 0.03 soc/core.mgmtsoc_vexriscv_transfer_complete (net) |
| 0.29 0.00 6.59 v soc/_39699_/A1 (AOI22_X1_7T5P0) |
| 0.26 0.22 6.81 ^ soc/_39699_/ZN (AOI22_X1_7T5P0) |
| 1 0.01 soc/_18548_ (net) |
| 0.26 0.00 6.81 ^ soc/_39700_/A2 (NOR2_X1_7T5P0) |
| 0.19 0.15 6.96 v soc/_39700_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 soc/_18549_ (net) |
| 0.19 0.00 6.96 v soc/_39701_/I (CLKBUF_X1_7T5P0) |
| 0.11 0.20 7.17 v soc/_39701_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_03678_ (net) |
| 0.11 0.00 7.17 v soc/_45813_/D (DFFQ_X1_7T5P0) |
| 7.17 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.32 4.04 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 4.38 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 4.39 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.28 4.67 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 4.67 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.41 5.08 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 5.09 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 5.51 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 5.52 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.35 5.87 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 5.87 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.63 6.50 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.01 6.51 ^ soc/clkbuf_opt_20_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.39 6.90 ^ soc/clkbuf_opt_20_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.09 soc/clknet_opt_20_0_core_clk (net) |
| 0.16 0.00 6.91 ^ soc/clkbuf_leaf_88_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.11 0.26 7.17 ^ soc/clkbuf_leaf_88_core_clk/Z (CLKBUF_X16_7T5P0) |
| 6 0.04 soc/clknet_leaf_88_core_clk (net) |
| 0.11 0.00 7.17 ^ soc/_45813_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.42 clock uncertainty |
| -0.42 7.01 clock reconvergence pessimism |
| 0.09 7.09 library hold time |
| 7.09 data required time |
| ----------------------------------------------------------------------------- |
| 7.09 data required time |
| -7.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.07 slack (MET) |
| |
| |
| Startpoint: soc/_44626_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44625_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 5.86 ^ soc/clkbuf_leaf_159_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.35 6.21 ^ soc/clkbuf_leaf_159_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.05 soc/clknet_leaf_159_core_clk (net) |
| 0.13 0.00 6.22 ^ soc/_44626_/CLK (DFFQ_X1_7T5P0) |
| 0.11 0.62 6.83 v soc/_44626_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl44_regs0 (net) |
| 0.11 0.00 6.83 v soc/_44625_/D (DFFQ_X1_7T5P0) |
| 6.83 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 6.47 ^ soc/clkbuf_leaf_158_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.42 6.89 ^ soc/clkbuf_leaf_158_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_158_core_clk (net) |
| 0.18 0.00 6.89 ^ soc/_44625_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.14 clock uncertainty |
| -0.55 6.60 clock reconvergence pessimism |
| 0.10 6.69 library hold time |
| 6.69 data required time |
| ----------------------------------------------------------------------------- |
| 6.69 data required time |
| -6.83 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.14 slack (MET) |
| |
| |
| Startpoint: soc/_44624_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44623_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 5.86 ^ soc/clkbuf_leaf_159_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.35 6.21 ^ soc/clkbuf_leaf_159_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.05 soc/clknet_leaf_159_core_clk (net) |
| 0.13 0.00 6.22 ^ soc/_44624_/CLK (DFFQ_X1_7T5P0) |
| 0.12 0.63 6.85 v soc/_44624_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.multiregimpl45_regs0 (net) |
| 0.12 0.00 6.85 v soc/_44623_/D (DFFQ_X1_7T5P0) |
| 6.85 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 6.47 ^ soc/clkbuf_leaf_158_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.42 6.89 ^ soc/clkbuf_leaf_158_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_158_core_clk (net) |
| 0.18 0.00 6.89 ^ soc/_44623_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.14 clock uncertainty |
| -0.55 6.60 clock reconvergence pessimism |
| 0.09 6.69 library hold time |
| 6.69 data required time |
| ----------------------------------------------------------------------------- |
| 6.69 data required time |
| -6.85 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.15 slack (MET) |
| |
| |
| Startpoint: soc/_44710_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44709_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 3.97 ^ soc/clkbuf_3_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.10 0.24 4.21 ^ soc/clkbuf_3_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_0_0_core_clk (net) |
| 0.10 0.00 4.21 ^ soc/clkbuf_3_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.27 4.49 ^ soc/clkbuf_3_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_3_0_1_core_clk (net) |
| 0.18 0.00 4.49 ^ soc/clkbuf_4_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.25 4.74 ^ soc/clkbuf_4_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.03 soc/clknet_4_0_0_core_clk (net) |
| 0.13 0.00 4.74 ^ soc/clkbuf_5_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.21 0.29 5.03 ^ soc/clkbuf_5_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.08 soc/clknet_5_0_0_core_clk (net) |
| 0.21 0.00 5.04 ^ soc/clkbuf_6_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.62 0.54 5.58 ^ soc/clkbuf_6_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.29 soc/clknet_6_0_0_core_clk (net) |
| 0.62 0.00 5.59 ^ soc/clkbuf_opt_3_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.32 5.91 ^ soc/clkbuf_opt_3_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.04 soc/clknet_opt_3_0_core_clk (net) |
| 0.12 0.00 5.91 ^ soc/clkbuf_leaf_531_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.24 6.15 ^ soc/clkbuf_leaf_531_core_clk/Z (CLKBUF_X16_7T5P0) |
| 14 0.06 soc/clknet_leaf_531_core_clk (net) |
| 0.12 0.00 6.15 ^ soc/_44710_/CLK (DFFQ_X1_7T5P0) |
| 0.24 0.72 6.87 v soc/_44710_/Q (DFFQ_X1_7T5P0) |
| 2 0.02 soc/core.multiregimpl2_regs0 (net) |
| 0.24 0.00 6.87 v soc/_44709_/D (DFFQ_X1_7T5P0) |
| 6.87 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.32 4.04 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 4.38 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 4.39 ^ soc/clkbuf_3_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.10 0.27 4.66 ^ soc/clkbuf_3_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_0_0_core_clk (net) |
| 0.10 0.00 4.66 ^ soc/clkbuf_3_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.30 4.96 ^ soc/clkbuf_3_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_3_0_1_core_clk (net) |
| 0.18 0.00 4.96 ^ soc/clkbuf_4_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.28 5.24 ^ soc/clkbuf_4_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.03 soc/clknet_4_0_0_core_clk (net) |
| 0.13 0.00 5.24 ^ soc/clkbuf_5_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.21 0.33 5.56 ^ soc/clkbuf_5_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.08 soc/clknet_5_0_0_core_clk (net) |
| 0.21 0.00 5.57 ^ soc/clkbuf_6_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.62 0.60 6.17 ^ soc/clkbuf_6_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.29 soc/clknet_6_0_0_core_clk (net) |
| 0.62 0.01 6.18 ^ soc/clkbuf_opt_1_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.11 0.34 6.52 ^ soc/clkbuf_opt_1_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 1 0.02 soc/clknet_opt_1_0_core_clk (net) |
| 0.11 0.00 6.52 ^ soc/clkbuf_opt_1_1_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.11 0.25 6.77 ^ soc/clkbuf_opt_1_1_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.04 soc/clknet_opt_1_1_core_clk (net) |
| 0.11 0.00 6.77 ^ soc/clkbuf_leaf_528_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.08 0.23 7.00 ^ soc/clkbuf_leaf_528_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.01 soc/clknet_leaf_528_core_clk (net) |
| 0.08 0.00 7.00 ^ soc/_44709_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.25 clock uncertainty |
| -0.59 6.66 clock reconvergence pessimism |
| 0.04 6.71 library hold time |
| 6.71 data required time |
| ----------------------------------------------------------------------------- |
| 6.71 data required time |
| -6.87 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.16 slack (MET) |
| |
| |
| Startpoint: soc/_45846_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44435_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_419_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.34 6.29 ^ soc/clkbuf_leaf_419_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_419_core_clk (net) |
| 0.17 0.00 6.30 ^ soc/_45846_/CLK (DFFQ_X1_7T5P0) |
| 1.20 1.30 7.59 ^ soc/_45846_/Q (DFFQ_X1_7T5P0) |
| 6 0.07 soc/core.VexRiscv.when_DebugPlugin_l260_1 (net) |
| 1.20 0.00 7.59 ^ soc/_34394_/A1 (AOI211_X1_7T5P0) |
| 0.25 0.19 7.78 v soc/_34394_/ZN (AOI211_X1_7T5P0) |
| 1 0.01 soc/_14416_ (net) |
| 0.25 0.00 7.78 v soc/_34395_/I (CLKBUF_X1_7T5P0) |
| 0.10 0.21 7.99 v soc/_34395_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02505_ (net) |
| 0.10 0.00 7.99 v soc/_44435_/D (DFFQ_X1_7T5P0) |
| 7.99 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.42 6.65 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 6.66 ^ soc/clkbuf_6_33_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.58 0.60 7.26 ^ soc/clkbuf_6_33_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 10 0.27 soc/clknet_6_33_0_core_clk (net) |
| 0.58 0.01 7.26 ^ soc/clkbuf_opt_24_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.40 7.66 ^ soc/clkbuf_opt_24_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.11 soc/clknet_opt_24_0_core_clk (net) |
| 0.18 0.00 7.66 ^ soc/clkbuf_leaf_416_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 7.94 ^ soc/clkbuf_leaf_416_core_clk/Z (CLKBUF_X16_7T5P0) |
| 9 0.06 soc/clknet_leaf_416_core_clk (net) |
| 0.12 0.00 7.95 ^ soc/_44435_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.20 clock uncertainty |
| -0.46 7.74 clock reconvergence pessimism |
| 0.09 7.83 library hold time |
| 7.83 data required time |
| ----------------------------------------------------------------------------- |
| 7.83 data required time |
| -7.99 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.17 slack (MET) |
| |
| |
| Startpoint: soc/_44702_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44701_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.03 5.86 ^ soc/clkbuf_leaf_152_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.10 0.32 6.19 ^ soc/clkbuf_leaf_152_core_clk/Z (CLKBUF_X16_7T5P0) |
| 3 0.02 soc/clknet_leaf_152_core_clk (net) |
| 0.10 0.00 6.19 ^ soc/_44702_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.61 6.79 v soc/_44702_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl6_regs0 (net) |
| 0.10 0.00 6.79 v soc/_44701_/D (DFFQ_X1_7T5P0) |
| 6.79 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.03 6.48 ^ soc/clkbuf_leaf_153_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.14 0.39 6.87 ^ soc/clkbuf_leaf_153_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.06 soc/clknet_leaf_153_core_clk (net) |
| 0.14 0.00 6.87 ^ soc/_44701_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.12 clock uncertainty |
| -0.61 6.51 clock reconvergence pessimism |
| 0.09 6.60 library hold time |
| 6.60 data required time |
| ----------------------------------------------------------------------------- |
| 6.60 data required time |
| -6.79 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.20 slack (MET) |
| |
| |
| Startpoint: soc/_44610_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44609_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.01 5.86 ^ soc/clkbuf_leaf_160_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.37 6.23 ^ soc/clkbuf_leaf_160_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.08 soc/clknet_leaf_160_core_clk (net) |
| 0.16 0.00 6.23 ^ soc/_44610_/CLK (DFFQ_X1_7T5P0) |
| 0.11 0.62 6.85 v soc/_44610_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl52_regs0 (net) |
| 0.11 0.00 6.85 v soc/_44609_/D (DFFQ_X1_7T5P0) |
| 6.85 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_170_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.19 0.44 6.92 ^ soc/clkbuf_leaf_170_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.12 soc/clknet_leaf_170_core_clk (net) |
| 0.19 0.00 6.92 ^ soc/_44609_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.17 clock uncertainty |
| -0.62 6.56 clock reconvergence pessimism |
| 0.10 6.66 library hold time |
| 6.66 data required time |
| ----------------------------------------------------------------------------- |
| 6.66 data required time |
| -6.85 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.20 slack (MET) |
| |
| |
| Startpoint: soc/_44957_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44961_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.31 4.88 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 4.89 ^ soc/clkbuf_5_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.30 5.19 ^ soc/clkbuf_5_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.08 soc/clknet_5_8_0_core_clk (net) |
| 0.20 0.00 5.19 ^ soc/clkbuf_6_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.79 0.64 5.83 ^ soc/clkbuf_6_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.38 soc/clknet_6_16_0_core_clk (net) |
| 0.79 0.01 5.84 ^ soc/clkbuf_leaf_121_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.37 6.21 ^ soc/clkbuf_leaf_121_core_clk/Z (CLKBUF_X16_7T5P0) |
| 13 0.09 soc/clknet_leaf_121_core_clk (net) |
| 0.17 0.00 6.21 ^ soc/_44957_/CLK (DFFQ_X1_7T5P0) |
| 0.17 0.72 6.93 ^ soc/_44957_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.gpioin0_gpioin0_trigger_d (net) |
| 0.17 0.00 6.93 ^ soc/_36454_/A2 (OAI31_X1_7T5P0) |
| 0.15 0.13 7.07 v soc/_36454_/ZN (OAI31_X1_7T5P0) |
| 1 0.00 soc/_02890_ (net) |
| 0.15 0.00 7.07 v soc/_44961_/D (DFFQ_X1_7T5P0) |
| 7.07 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.32 4.04 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 4.38 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 4.39 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.28 4.67 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 4.67 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.41 5.08 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 5.09 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 5.51 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 5.52 ^ soc/clkbuf_5_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.38 5.90 ^ soc/clkbuf_5_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_5_6_0_core_clk (net) |
| 0.25 0.00 5.90 ^ soc/clkbuf_6_13_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.56 0.57 6.48 ^ soc/clkbuf_6_13_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.27 soc/clknet_6_13_0_core_clk (net) |
| 0.57 0.01 6.49 ^ soc/clkbuf_leaf_119_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.39 6.89 ^ soc/clkbuf_leaf_119_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.11 soc/clknet_leaf_119_core_clk (net) |
| 0.17 0.00 6.89 ^ soc/_44961_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.14 clock uncertainty |
| -0.35 6.78 clock reconvergence pessimism |
| 0.09 6.87 library hold time |
| 6.87 data required time |
| ----------------------------------------------------------------------------- |
| 6.87 data required time |
| -7.07 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.20 slack (MET) |
| |
| |
| Startpoint: soc/_44660_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44659_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 5.85 ^ soc/clkbuf_leaf_158_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.38 6.24 ^ soc/clkbuf_leaf_158_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_158_core_clk (net) |
| 0.18 0.00 6.24 ^ soc/_44660_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.62 6.86 v soc/_44660_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl27_regs0 (net) |
| 0.10 0.00 6.86 v soc/_44659_/D (DFFQ_X1_7T5P0) |
| 6.86 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_163_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.38 6.86 ^ soc/clkbuf_leaf_163_core_clk/Z (CLKBUF_X16_7T5P0) |
| 7 0.04 soc/clknet_leaf_163_core_clk (net) |
| 0.13 0.00 6.86 ^ soc/_44659_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.11 clock uncertainty |
| -0.55 6.57 clock reconvergence pessimism |
| 0.09 6.66 library hold time |
| 6.66 data required time |
| ----------------------------------------------------------------------------- |
| 6.66 data required time |
| -6.86 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.20 slack (MET) |
| |
| |
| Startpoint: soc/_44670_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44669_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 5.86 ^ soc/clkbuf_leaf_156_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.36 6.22 ^ soc/clkbuf_leaf_156_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.07 soc/clknet_leaf_156_core_clk (net) |
| 0.15 0.00 6.22 ^ soc/_44670_/CLK (DFFQ_X1_7T5P0) |
| 0.11 0.62 6.84 v soc/_44670_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl22_regs0 (net) |
| 0.11 0.00 6.84 v soc/_44669_/D (DFFQ_X1_7T5P0) |
| 6.84 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 6.47 ^ soc/clkbuf_leaf_157_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.43 6.90 ^ soc/clkbuf_leaf_157_core_clk/Z (CLKBUF_X16_7T5P0) |
| 36 0.11 soc/clknet_leaf_157_core_clk (net) |
| 0.18 0.00 6.90 ^ soc/_44669_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.15 clock uncertainty |
| -0.61 6.54 clock reconvergence pessimism |
| 0.10 6.64 library hold time |
| 6.64 data required time |
| ----------------------------------------------------------------------------- |
| 6.64 data required time |
| -6.84 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.20 slack (MET) |
| |
| |
| Startpoint: soc/_44499_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_45801_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.35 4.02 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 4.02 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.34 4.36 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.01 4.37 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.26 4.63 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 4.64 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.35 4.98 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 4.99 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 5.36 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.01 5.36 ^ soc/clkbuf_5_25_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.33 5.69 ^ soc/clkbuf_5_25_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_25_0_core_clk (net) |
| 0.23 0.00 5.70 ^ soc/clkbuf_6_51_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.65 6.35 ^ soc/clkbuf_6_51_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.39 soc/clknet_6_51_0_core_clk (net) |
| 0.81 0.01 6.36 ^ soc/clkbuf_leaf_295_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.25 0.43 6.78 ^ soc/clkbuf_leaf_295_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.19 soc/clknet_leaf_295_core_clk (net) |
| 0.25 0.01 6.79 ^ soc/_44499_/CLK (DFFQ_X1_7T5P0) |
| 0.15 0.67 7.46 v soc/_44499_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.VexRiscv.DebugPlugin_busReadDataReg[20] (net) |
| 0.15 0.00 7.46 v soc/_45801_/D (DFFQ_X1_7T5P0) |
| 7.46 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.39 4.45 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 4.45 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.37 4.82 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.02 4.83 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 5.12 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 5.12 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.39 5.51 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 5.52 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.40 5.92 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.01 5.93 ^ soc/clkbuf_5_25_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.29 ^ soc/clkbuf_5_25_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_25_0_core_clk (net) |
| 0.23 0.01 6.30 ^ soc/clkbuf_6_50_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.80 7.10 ^ soc/clkbuf_6_50_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.46 soc/clknet_6_50_0_core_clk (net) |
| 0.95 0.03 7.13 ^ soc/clkbuf_leaf_452_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.40 7.53 ^ soc/clkbuf_leaf_452_core_clk/Z (CLKBUF_X16_7T5P0) |
| 5 0.05 soc/clknet_leaf_452_core_clk (net) |
| 0.13 0.00 7.53 ^ soc/_45801_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.78 clock uncertainty |
| -0.60 7.18 clock reconvergence pessimism |
| 0.08 7.26 library hold time |
| 7.26 data required time |
| ----------------------------------------------------------------------------- |
| 7.26 data required time |
| -7.46 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.21 slack (MET) |
| |
| |
| Startpoint: soc/_44608_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44607_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.01 5.86 ^ soc/clkbuf_leaf_160_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.37 6.23 ^ soc/clkbuf_leaf_160_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.08 soc/clknet_leaf_160_core_clk (net) |
| 0.16 0.00 6.23 ^ soc/_44608_/CLK (DFFQ_X1_7T5P0) |
| 0.12 0.63 6.86 v soc/_44608_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.multiregimpl53_regs0 (net) |
| 0.12 0.00 6.86 v soc/_44607_/D (DFFQ_X1_7T5P0) |
| 6.86 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_170_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.19 0.44 6.92 ^ soc/clkbuf_leaf_170_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.12 soc/clknet_leaf_170_core_clk (net) |
| 0.19 0.01 6.92 ^ soc/_44607_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.17 clock uncertainty |
| -0.62 6.56 clock reconvergence pessimism |
| 0.10 6.66 library hold time |
| 6.66 data required time |
| ----------------------------------------------------------------------------- |
| 6.66 data required time |
| -6.86 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.21 slack (MET) |
| |
| |
| Startpoint: soc/_44648_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44647_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 5.85 ^ soc/clkbuf_leaf_158_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.38 6.24 ^ soc/clkbuf_leaf_158_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_158_core_clk (net) |
| 0.18 0.00 6.24 ^ soc/_44648_/CLK (DFFQ_X1_7T5P0) |
| 0.12 0.63 6.87 v soc/_44648_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.multiregimpl33_regs0 (net) |
| 0.12 0.00 6.87 v soc/_44647_/D (DFFQ_X1_7T5P0) |
| 6.87 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_163_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.38 6.86 ^ soc/clkbuf_leaf_163_core_clk/Z (CLKBUF_X16_7T5P0) |
| 7 0.04 soc/clknet_leaf_163_core_clk (net) |
| 0.13 0.00 6.86 ^ soc/_44647_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.11 clock uncertainty |
| -0.55 6.57 clock reconvergence pessimism |
| 0.09 6.65 library hold time |
| 6.65 data required time |
| ----------------------------------------------------------------------------- |
| 6.65 data required time |
| -6.87 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.22 slack (MET) |
| |
| |
| Startpoint: soc/_44692_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44691_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.03 5.86 ^ soc/clkbuf_leaf_155_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.14 0.35 6.21 ^ soc/clkbuf_leaf_155_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.05 soc/clknet_leaf_155_core_clk (net) |
| 0.14 0.00 6.21 ^ soc/_44692_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.61 6.83 v soc/_44692_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl11_regs0 (net) |
| 0.10 0.00 6.83 v soc/_44691_/D (DFFQ_X1_7T5P0) |
| 6.83 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.03 6.48 ^ soc/clkbuf_leaf_153_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.14 0.39 6.87 ^ soc/clkbuf_leaf_153_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.06 soc/clknet_leaf_153_core_clk (net) |
| 0.14 0.00 6.87 ^ soc/_44691_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.12 clock uncertainty |
| -0.61 6.51 clock reconvergence pessimism |
| 0.09 6.60 library hold time |
| 6.60 data required time |
| ----------------------------------------------------------------------------- |
| 6.60 data required time |
| -6.83 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.23 slack (MET) |
| |
| |
| Startpoint: soc/_44640_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44639_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 5.86 ^ soc/clkbuf_leaf_159_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.35 6.21 ^ soc/clkbuf_leaf_159_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.05 soc/clknet_leaf_159_core_clk (net) |
| 0.13 0.00 6.22 ^ soc/_44640_/CLK (DFFQ_X1_7T5P0) |
| 0.12 0.63 6.84 v soc/_44640_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.multiregimpl37_regs0 (net) |
| 0.12 0.00 6.84 v soc/_44639_/D (DFFQ_X1_7T5P0) |
| 6.84 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_160_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.41 6.89 ^ soc/clkbuf_leaf_160_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.08 soc/clknet_leaf_160_core_clk (net) |
| 0.16 0.00 6.89 ^ soc/_44639_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.14 clock uncertainty |
| -0.62 6.52 clock reconvergence pessimism |
| 0.09 6.61 library hold time |
| 6.61 data required time |
| ----------------------------------------------------------------------------- |
| 6.61 data required time |
| -6.84 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.23 slack (MET) |
| |
| |
| Startpoint: soc/_44359_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43504_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 3.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 4.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 4.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 4.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 4.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 4.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 5.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 5.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 5.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 5.64 ^ soc/clkbuf_leaf_61_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 5.95 ^ soc/clkbuf_leaf_61_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_61_core_clk (net) |
| 0.13 0.00 5.95 ^ soc/_44359_/CLK (DFFQ_X1_7T5P0) |
| 0.39 0.82 6.77 v soc/_44359_/Q (DFFQ_X1_7T5P0) |
| 3 0.04 soc/core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] (net) |
| 0.39 0.00 6.77 v soc/_31435_/I1 (MUX2_X2_7T5P0) |
| 0.12 0.39 7.16 v soc/_31435_/Z (MUX2_X2_7T5P0) |
| 1 0.01 soc/_12299_ (net) |
| 0.12 0.00 7.16 v soc/_31436_/I (CLKBUF_X1_7T5P0) |
| 0.10 0.18 7.34 v soc/_31436_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_01663_ (net) |
| 0.10 0.00 7.34 v soc/_43504_/D (DFFQ_X1_7T5P0) |
| 7.34 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 4.67 ^ soc/clkbuf_3_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_3_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.36 5.03 ^ soc/clkbuf_3_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_3_3_1_core_clk (net) |
| 0.27 0.00 5.04 ^ soc/clkbuf_4_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.35 5.39 ^ soc/clkbuf_4_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_6_0_core_clk (net) |
| 0.20 0.00 5.39 ^ soc/clkbuf_5_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.39 5.78 ^ soc/clkbuf_5_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_5_12_0_core_clk (net) |
| 0.28 0.00 5.78 ^ soc/clkbuf_6_24_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.98 0.83 6.61 ^ soc/clkbuf_6_24_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.47 soc/clknet_6_24_0_core_clk (net) |
| 0.98 0.00 6.62 ^ soc/clkbuf_leaf_253_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.22 0.48 7.09 ^ soc/clkbuf_leaf_253_core_clk/Z (CLKBUF_X16_7T5P0) |
| 20 0.15 soc/clknet_leaf_253_core_clk (net) |
| 0.22 0.01 7.10 ^ soc/_43504_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.35 clock uncertainty |
| -0.35 6.99 clock reconvergence pessimism |
| 0.11 7.10 library hold time |
| 7.10 data required time |
| ----------------------------------------------------------------------------- |
| 7.10 data required time |
| -7.34 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.23 slack (MET) |
| |
| |
| Startpoint: soc/_43017_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44463_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_419_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.34 6.29 ^ soc/clkbuf_leaf_419_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_419_core_clk (net) |
| 0.17 0.00 6.30 ^ soc/_43017_/CLK (DFFQ_X1_7T5P0) |
| 0.25 0.77 7.06 ^ soc/_43017_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[14] (net) |
| 0.25 0.00 7.06 ^ soc/_34546_/A1 (AOI21_X1_7T5P0) |
| 0.73 0.47 7.54 v soc/_34546_/ZN (AOI21_X1_7T5P0) |
| 2 0.05 soc/_14540_ (net) |
| 0.73 0.00 7.54 v soc/_34547_/B2 (AOI22_X1_7T5P0) |
| 0.35 0.43 7.97 ^ soc/_34547_/ZN (AOI22_X1_7T5P0) |
| 1 0.01 soc/_02533_ (net) |
| 0.35 0.00 7.97 ^ soc/_44463_/D (DFFQ_X1_7T5P0) |
| 7.97 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.58 7.19 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 7.20 ^ soc/clkbuf_opt_27_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.37 7.58 ^ soc/clkbuf_opt_27_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_27_0_core_clk (net) |
| 0.15 0.00 7.58 ^ soc/clkbuf_leaf_433_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.31 7.89 ^ soc/clkbuf_leaf_433_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.11 soc/clknet_leaf_433_core_clk (net) |
| 0.17 0.00 7.89 ^ soc/_44463_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.14 clock uncertainty |
| -0.46 7.68 clock reconvergence pessimism |
| 0.05 7.73 library hold time |
| 7.73 data required time |
| ----------------------------------------------------------------------------- |
| 7.73 data required time |
| -7.97 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.24 slack (MET) |
| |
| |
| Startpoint: soc/_45848_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44014_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 5.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 5.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 5.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 5.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 5.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 5.95 ^ soc/clkbuf_leaf_419_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.34 6.29 ^ soc/clkbuf_leaf_419_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_419_core_clk (net) |
| 0.17 0.00 6.30 ^ soc/_45848_/CLK (DFFQ_X1_7T5P0) |
| 1.03 1.20 7.50 ^ soc/_45848_/Q (DFFQ_X1_7T5P0) |
| 6 0.06 soc/core.VexRiscv.when_DebugPlugin_l264_1 (net) |
| 1.03 0.00 7.50 ^ soc/_32773_/A1 (AOI211_X1_7T5P0) |
| 0.33 0.27 7.78 v soc/_32773_/ZN (AOI211_X1_7T5P0) |
| 1 0.01 soc/_13216_ (net) |
| 0.33 0.00 7.78 v soc/_32774_/I (CLKBUF_X1_7T5P0) |
| 0.12 0.24 8.02 v soc/_32774_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02084_ (net) |
| 0.12 0.00 8.02 v soc/_44014_/D (DFFQ_X1_7T5P0) |
| 8.02 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.37 6.61 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 6.61 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.58 7.19 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 7.20 ^ soc/clkbuf_opt_27_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.37 7.58 ^ soc/clkbuf_opt_27_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_27_0_core_clk (net) |
| 0.15 0.00 7.58 ^ soc/clkbuf_leaf_433_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.31 7.89 ^ soc/clkbuf_leaf_433_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.11 soc/clknet_leaf_433_core_clk (net) |
| 0.17 0.00 7.89 ^ soc/_44014_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.14 clock uncertainty |
| -0.46 7.68 clock reconvergence pessimism |
| 0.09 7.77 library hold time |
| 7.77 data required time |
| ----------------------------------------------------------------------------- |
| 7.77 data required time |
| -8.02 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.24 slack (MET) |
| |
| |
| Startpoint: soc/_44590_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44589_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.32 5.22 ^ soc/clkbuf_5_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_11_0_core_clk (net) |
| 0.23 0.00 5.22 ^ soc/clkbuf_6_22_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.72 0.60 5.81 ^ soc/clkbuf_6_22_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.34 soc/clknet_6_22_0_core_clk (net) |
| 0.72 0.03 5.84 ^ soc/clkbuf_leaf_171_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.14 0.35 6.19 ^ soc/clkbuf_leaf_171_core_clk/Z (CLKBUF_X16_7T5P0) |
| 13 0.07 soc/clknet_leaf_171_core_clk (net) |
| 0.14 0.00 6.19 ^ soc/_44590_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.62 6.80 v soc/_44590_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl62_regs0 (net) |
| 0.10 0.00 6.80 v soc/_44589_/D (DFFQ_X1_7T5P0) |
| 6.80 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.35 5.76 ^ soc/clkbuf_5_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_11_0_core_clk (net) |
| 0.23 0.00 5.77 ^ soc/clkbuf_6_22_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.72 0.66 6.43 ^ soc/clkbuf_6_22_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.34 soc/clknet_6_22_0_core_clk (net) |
| 0.72 0.01 6.43 ^ soc/clkbuf_leaf_173_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.39 6.82 ^ soc/clkbuf_leaf_173_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.08 soc/clknet_leaf_173_core_clk (net) |
| 0.15 0.00 6.82 ^ soc/_44589_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.07 clock uncertainty |
| -0.61 6.46 clock reconvergence pessimism |
| 0.09 6.56 library hold time |
| 6.56 data required time |
| ----------------------------------------------------------------------------- |
| 6.56 data required time |
| -6.80 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.25 slack (MET) |
| |
| |
| Startpoint: soc/_44684_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44683_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.03 5.86 ^ soc/clkbuf_leaf_155_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.14 0.35 6.21 ^ soc/clkbuf_leaf_155_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.05 soc/clknet_leaf_155_core_clk (net) |
| 0.14 0.00 6.21 ^ soc/_44684_/CLK (DFFQ_X1_7T5P0) |
| 0.12 0.63 6.85 v soc/_44684_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.multiregimpl15_regs0 (net) |
| 0.12 0.00 6.85 v soc/_44683_/D (DFFQ_X1_7T5P0) |
| 6.85 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.03 6.48 ^ soc/clkbuf_leaf_153_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.14 0.39 6.87 ^ soc/clkbuf_leaf_153_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.06 soc/clknet_leaf_153_core_clk (net) |
| 0.14 0.00 6.87 ^ soc/_44683_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.12 clock uncertainty |
| -0.61 6.51 clock reconvergence pessimism |
| 0.09 6.59 library hold time |
| 6.59 data required time |
| ----------------------------------------------------------------------------- |
| 6.59 data required time |
| -6.85 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.25 slack (MET) |
| |
| |
| Startpoint: soc/_44708_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44707_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 5.86 ^ soc/clkbuf_leaf_156_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.36 6.22 ^ soc/clkbuf_leaf_156_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.07 soc/clknet_leaf_156_core_clk (net) |
| 0.15 0.00 6.22 ^ soc/_44708_/CLK (DFFQ_X1_7T5P0) |
| 0.11 0.62 6.85 v soc/_44708_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl3_regs0 (net) |
| 0.11 0.00 6.85 v soc/_44707_/D (DFFQ_X1_7T5P0) |
| 6.85 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.03 6.48 ^ soc/clkbuf_leaf_155_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.14 0.39 6.87 ^ soc/clkbuf_leaf_155_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.05 soc/clknet_leaf_155_core_clk (net) |
| 0.14 0.00 6.87 ^ soc/_44707_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.12 clock uncertainty |
| -0.61 6.50 clock reconvergence pessimism |
| 0.09 6.59 library hold time |
| 6.59 data required time |
| ----------------------------------------------------------------------------- |
| 6.59 data required time |
| -6.85 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.25 slack (MET) |
| |
| |
| Startpoint: soc/_43596_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43606_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 4.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 5.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 5.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 5.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 5.64 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.38 6.02 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 6.02 ^ soc/clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 6.61 ^ soc/clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.32 soc/clknet_6_32_0_core_clk (net) |
| 0.68 0.01 6.63 ^ soc/clkbuf_leaf_439_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.36 6.99 ^ soc/clkbuf_leaf_439_core_clk/Z (CLKBUF_X16_7T5P0) |
| 14 0.09 soc/clknet_leaf_439_core_clk (net) |
| 0.16 0.00 6.99 ^ soc/_43596_/CLK (DFFQ_X1_7T5P0) |
| 0.17 0.67 7.66 v soc/_43596_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.VexRiscv.execute_to_memory_INSTRUCTION[29] (net) |
| 0.17 0.00 7.66 v soc/_43606_/D (DFFQ_X1_7T5P0) |
| 7.66 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.42 6.65 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 6.66 ^ soc/clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.65 7.31 ^ soc/clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.32 soc/clknet_6_32_0_core_clk (net) |
| 0.68 0.01 7.32 ^ soc/clkbuf_leaf_440_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.21 0.44 7.76 ^ soc/clkbuf_leaf_440_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.15 soc/clknet_leaf_440_core_clk (net) |
| 0.21 0.00 7.76 ^ soc/_43606_/CLK (DFFQ_X1_7T5P0) |
| 0.25 8.01 clock uncertainty |
| -0.70 7.32 clock reconvergence pessimism |
| 0.09 7.41 library hold time |
| 7.41 data required time |
| ----------------------------------------------------------------------------- |
| 7.41 data required time |
| -7.66 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.26 slack (MET) |
| |
| |
| Startpoint: soc/_44656_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44655_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 5.86 ^ soc/clkbuf_leaf_157_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.39 6.24 ^ soc/clkbuf_leaf_157_core_clk/Z (CLKBUF_X16_7T5P0) |
| 36 0.11 soc/clknet_leaf_157_core_clk (net) |
| 0.18 0.00 6.25 ^ soc/_44656_/CLK (DFFQ_X1_7T5P0) |
| 0.12 0.64 6.88 v soc/_44656_/Q (DFFQ_X1_7T5P0) |
| 1 0.01 soc/core.multiregimpl29_regs0 (net) |
| 0.12 0.00 6.88 v soc/_44655_/D (DFFQ_X1_7T5P0) |
| 6.88 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 6.47 ^ soc/clkbuf_leaf_158_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.42 6.89 ^ soc/clkbuf_leaf_158_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_158_core_clk (net) |
| 0.18 0.00 6.89 ^ soc/_44655_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.14 clock uncertainty |
| -0.61 6.53 clock reconvergence pessimism |
| 0.10 6.63 library hold time |
| 6.63 data required time |
| ----------------------------------------------------------------------------- |
| 6.63 data required time |
| -6.88 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.26 slack (MET) |
| |
| |
| Startpoint: soc/_45394_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42992_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 3.97 ^ soc/clkbuf_3_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.10 0.24 4.21 ^ soc/clkbuf_3_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_0_0_core_clk (net) |
| 0.10 0.00 4.21 ^ soc/clkbuf_3_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.27 4.49 ^ soc/clkbuf_3_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_3_0_1_core_clk (net) |
| 0.18 0.00 4.49 ^ soc/clkbuf_4_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.25 4.73 ^ soc/clkbuf_4_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.03 soc/clknet_4_1_0_core_clk (net) |
| 0.12 0.00 4.74 ^ soc/clkbuf_5_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 5.02 ^ soc/clkbuf_5_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_3_0_core_clk (net) |
| 0.19 0.00 5.02 ^ soc/clkbuf_6_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.57 0.51 5.54 ^ soc/clkbuf_6_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.27 soc/clknet_6_6_0_core_clk (net) |
| 0.57 0.01 5.54 ^ soc/clkbuf_leaf_115_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.35 5.89 ^ soc/clkbuf_leaf_115_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.10 soc/clknet_leaf_115_core_clk (net) |
| 0.17 0.00 5.90 ^ soc/_45394_/CLK (DFFQ_X1_7T5P0) |
| 0.18 0.68 6.58 v soc/_45394_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.spi_master_cs_storage[8] (net) |
| 0.18 0.00 6.58 v soc/_28633_/A1 (AOI22_X1_7T5P0) |
| 0.25 0.19 6.77 ^ soc/_28633_/ZN (AOI22_X1_7T5P0) |
| 1 0.01 soc/_09975_ (net) |
| 0.25 0.00 6.77 ^ soc/_28635_/A2 (AOI21_X1_7T5P0) |
| 0.17 0.14 6.90 v soc/_28635_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_09977_ (net) |
| 0.17 0.00 6.90 v soc/_28636_/I (CLKBUF_X1_7T5P0) |
| 0.13 0.22 7.12 v soc/_28636_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_01185_ (net) |
| 0.13 0.00 7.12 v soc/_42992_/D (DFFQ_X1_7T5P0) |
| 7.12 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.33 5.74 ^ soc/clkbuf_5_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.08 soc/clknet_5_8_0_core_clk (net) |
| 0.20 0.00 5.74 ^ soc/clkbuf_6_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.79 0.70 6.44 ^ soc/clkbuf_6_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.38 soc/clknet_6_16_0_core_clk (net) |
| 0.79 0.01 6.45 ^ soc/clkbuf_leaf_113_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.42 6.87 ^ soc/clkbuf_leaf_113_core_clk/Z (CLKBUF_X16_7T5P0) |
| 20 0.10 soc/clknet_leaf_113_core_clk (net) |
| 0.17 0.00 6.87 ^ soc/_42992_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.12 clock uncertainty |
| -0.35 6.77 clock reconvergence pessimism |
| 0.09 6.86 library hold time |
| 6.86 data required time |
| ----------------------------------------------------------------------------- |
| 6.86 data required time |
| -7.12 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.26 slack (MET) |
| |
| |
| Startpoint: soc/_44644_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44643_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 5.86 ^ soc/clkbuf_leaf_157_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.39 6.24 ^ soc/clkbuf_leaf_157_core_clk/Z (CLKBUF_X16_7T5P0) |
| 36 0.11 soc/clknet_leaf_157_core_clk (net) |
| 0.18 0.00 6.25 ^ soc/_44644_/CLK (DFFQ_X1_7T5P0) |
| 0.09 0.62 6.86 v soc/_44644_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl35_regs0 (net) |
| 0.09 0.00 6.86 v soc/_44643_/D (DFFQ_X1_7T5P0) |
| 6.86 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 6.47 ^ soc/clkbuf_leaf_157_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.43 6.90 ^ soc/clkbuf_leaf_157_core_clk/Z (CLKBUF_X16_7T5P0) |
| 36 0.11 soc/clknet_leaf_157_core_clk (net) |
| 0.18 0.00 6.90 ^ soc/_44643_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.15 clock uncertainty |
| -0.66 6.50 clock reconvergence pessimism |
| 0.10 6.60 library hold time |
| 6.60 data required time |
| ----------------------------------------------------------------------------- |
| 6.60 data required time |
| -6.86 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.26 slack (MET) |
| |
| |
| Startpoint: soc/_44620_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44619_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 5.86 ^ soc/clkbuf_leaf_159_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.35 6.21 ^ soc/clkbuf_leaf_159_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.05 soc/clknet_leaf_159_core_clk (net) |
| 0.13 0.00 6.22 ^ soc/_44620_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.61 6.82 v soc/_44620_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl47_regs0 (net) |
| 0.10 0.00 6.82 v soc/_44619_/D (DFFQ_X1_7T5P0) |
| 6.82 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_159_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 6.87 ^ soc/clkbuf_leaf_159_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.05 soc/clknet_leaf_159_core_clk (net) |
| 0.13 0.00 6.87 ^ soc/_44619_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.12 clock uncertainty |
| -0.65 6.47 clock reconvergence pessimism |
| 0.09 6.56 library hold time |
| 6.56 data required time |
| ----------------------------------------------------------------------------- |
| 6.56 data required time |
| -6.82 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.26 slack (MET) |
| |
| |
| Startpoint: soc/_44604_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44603_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.01 5.86 ^ soc/clkbuf_leaf_170_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.19 0.40 6.26 ^ soc/clkbuf_leaf_170_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.12 soc/clknet_leaf_170_core_clk (net) |
| 0.19 0.00 6.26 ^ soc/_44604_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.62 6.88 v soc/_44604_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl55_regs0 (net) |
| 0.10 0.00 6.88 v soc/_44603_/D (DFFQ_X1_7T5P0) |
| 6.88 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_170_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.19 0.44 6.92 ^ soc/clkbuf_leaf_170_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.12 soc/clknet_leaf_170_core_clk (net) |
| 0.19 0.00 6.92 ^ soc/_44603_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.17 clock uncertainty |
| -0.66 6.51 clock reconvergence pessimism |
| 0.10 6.62 library hold time |
| 6.62 data required time |
| ----------------------------------------------------------------------------- |
| 6.62 data required time |
| -6.88 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.27 slack (MET) |
| |
| |
| Startpoint: soc/_44618_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44617_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.01 5.86 ^ soc/clkbuf_leaf_160_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.37 6.23 ^ soc/clkbuf_leaf_160_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.08 soc/clknet_leaf_160_core_clk (net) |
| 0.16 0.00 6.23 ^ soc/_44618_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.61 6.84 v soc/_44618_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl48_regs0 (net) |
| 0.10 0.00 6.84 v soc/_44617_/D (DFFQ_X1_7T5P0) |
| 6.84 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_160_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.41 6.89 ^ soc/clkbuf_leaf_160_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.08 soc/clknet_leaf_160_core_clk (net) |
| 0.16 0.00 6.89 ^ soc/_44617_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.14 clock uncertainty |
| -0.66 6.48 clock reconvergence pessimism |
| 0.10 6.58 library hold time |
| 6.58 data required time |
| ----------------------------------------------------------------------------- |
| 6.58 data required time |
| -6.84 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.27 slack (MET) |
| |
| |
| Startpoint: soc/_44632_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44631_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.01 5.86 ^ soc/clkbuf_leaf_160_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.37 6.23 ^ soc/clkbuf_leaf_160_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.08 soc/clknet_leaf_160_core_clk (net) |
| 0.16 0.00 6.23 ^ soc/_44632_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.61 6.84 v soc/_44632_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl41_regs0 (net) |
| 0.10 0.00 6.84 v soc/_44631_/D (DFFQ_X1_7T5P0) |
| 6.84 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_160_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.41 6.89 ^ soc/clkbuf_leaf_160_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.08 soc/clknet_leaf_160_core_clk (net) |
| 0.16 0.00 6.89 ^ soc/_44631_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.14 clock uncertainty |
| -0.66 6.48 clock reconvergence pessimism |
| 0.10 6.58 library hold time |
| 6.58 data required time |
| ----------------------------------------------------------------------------- |
| 6.58 data required time |
| -6.84 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.27 slack (MET) |
| |
| |
| Startpoint: soc/_44508_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_45810_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.35 4.02 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 4.02 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.34 4.36 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.01 4.37 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.26 4.63 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 4.64 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.35 4.98 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 4.99 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 5.36 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.00 5.36 ^ soc/clkbuf_5_24_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.38 5.74 ^ soc/clkbuf_5_24_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_24_0_core_clk (net) |
| 0.30 0.01 5.74 ^ soc/clkbuf_6_48_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.61 0.56 6.30 ^ soc/clkbuf_6_48_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.29 soc/clknet_6_48_0_core_clk (net) |
| 0.61 0.01 6.31 ^ soc/clkbuf_leaf_285_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.22 0.39 6.70 ^ soc/clkbuf_leaf_285_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.16 soc/clknet_leaf_285_core_clk (net) |
| 0.22 0.00 6.70 ^ soc/_44508_/CLK (DFFQ_X1_7T5P0) |
| 0.16 0.68 7.38 v soc/_44508_/Q (DFFQ_X1_7T5P0) |
| 2 0.01 soc/core.VexRiscv.DebugPlugin_busReadDataReg[29] (net) |
| 0.16 0.00 7.38 v soc/_45810_/D (DFFQ_X1_7T5P0) |
| 7.38 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.39 4.45 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 4.45 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.37 4.82 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.02 4.83 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 5.12 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 5.12 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.39 5.51 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 5.52 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.40 5.92 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.00 5.92 ^ soc/clkbuf_5_24_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.42 6.34 ^ soc/clkbuf_5_24_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_24_0_core_clk (net) |
| 0.30 0.01 6.35 ^ soc/clkbuf_6_48_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.61 0.61 6.96 ^ soc/clkbuf_6_48_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.29 soc/clknet_6_48_0_core_clk (net) |
| 0.61 0.00 6.97 ^ soc/clkbuf_leaf_286_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.26 0.46 7.42 ^ soc/clkbuf_leaf_286_core_clk/Z (CLKBUF_X16_7T5P0) |
| 20 0.20 soc/clknet_leaf_286_core_clk (net) |
| 0.26 0.00 7.43 ^ soc/_45810_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.68 clock uncertainty |
| -0.66 7.01 clock reconvergence pessimism |
| 0.10 7.11 library hold time |
| 7.11 data required time |
| ----------------------------------------------------------------------------- |
| 7.11 data required time |
| -7.38 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.27 slack (MET) |
| |
| |
| Startpoint: soc/_44668_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44667_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.64 5.84 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 5.86 ^ soc/clkbuf_leaf_157_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.39 6.24 ^ soc/clkbuf_leaf_157_core_clk/Z (CLKBUF_X16_7T5P0) |
| 36 0.11 soc/clknet_leaf_157_core_clk (net) |
| 0.18 0.00 6.25 ^ soc/_44668_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.62 6.86 v soc/_44668_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl23_regs0 (net) |
| 0.10 0.00 6.86 v soc/_44667_/D (DFFQ_X1_7T5P0) |
| 6.86 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.71 6.45 ^ soc/clkbuf_6_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 26 0.39 soc/clknet_6_20_0_core_clk (net) |
| 0.81 0.02 6.47 ^ soc/clkbuf_leaf_157_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.43 6.90 ^ soc/clkbuf_leaf_157_core_clk/Z (CLKBUF_X16_7T5P0) |
| 36 0.11 soc/clknet_leaf_157_core_clk (net) |
| 0.18 0.00 6.90 ^ soc/_44667_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.15 clock uncertainty |
| -0.66 6.50 clock reconvergence pessimism |
| 0.10 6.60 library hold time |
| 6.60 data required time |
| ----------------------------------------------------------------------------- |
| 6.60 data required time |
| -6.86 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.27 slack (MET) |
| |
| |
| Startpoint: soc/_44638_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44637_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 3.65 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 3.65 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.31 3.97 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 3.97 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 4.22 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.22 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.34 4.56 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 4.57 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 4.89 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 4.90 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 5.19 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.20 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.65 5.85 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 5.86 ^ soc/clkbuf_leaf_159_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.35 6.21 ^ soc/clkbuf_leaf_159_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.05 soc/clknet_leaf_159_core_clk (net) |
| 0.13 0.00 6.21 ^ soc/_44638_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.61 6.82 v soc/_44638_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl38_regs0 (net) |
| 0.10 0.00 6.82 v soc/_44637_/D (DFFQ_X1_7T5P0) |
| 6.82 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.36 5.41 ^ soc/clkbuf_4_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_5_0_core_clk (net) |
| 0.20 0.00 5.41 ^ soc/clkbuf_5_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 5.74 ^ soc/clkbuf_5_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_10_0_core_clk (net) |
| 0.19 0.00 5.74 ^ soc/clkbuf_6_21_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.83 0.72 6.46 ^ soc/clkbuf_6_21_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 24 0.40 soc/clknet_6_21_0_core_clk (net) |
| 0.83 0.02 6.48 ^ soc/clkbuf_leaf_159_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 6.87 ^ soc/clkbuf_leaf_159_core_clk/Z (CLKBUF_X16_7T5P0) |
| 11 0.05 soc/clknet_leaf_159_core_clk (net) |
| 0.13 0.00 6.87 ^ soc/_44637_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.12 clock uncertainty |
| -0.65 6.46 clock reconvergence pessimism |
| 0.09 6.56 library hold time |
| 6.56 data required time |
| ----------------------------------------------------------------------------- |
| 6.56 data required time |
| -6.82 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.27 slack (MET) |
| |
| |
| Startpoint: soc/_46495_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_46496_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 3.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 3.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 4.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 4.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 4.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 4.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 4.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 4.92 ^ soc/clkbuf_4_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.17 0.28 5.20 ^ soc/clkbuf_4_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_4_10_0_core_clk (net) |
| 0.17 0.00 5.21 ^ soc/clkbuf_5_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.17 0.28 5.48 ^ soc/clkbuf_5_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_20_0_core_clk (net) |
| 0.17 0.00 5.49 ^ soc/clkbuf_6_41_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.42 0.43 5.92 ^ soc/clkbuf_6_41_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.19 soc/clknet_6_41_0_core_clk (net) |
| 0.42 0.00 5.92 ^ soc/clkbuf_leaf_510_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.11 0.28 6.20 ^ soc/clkbuf_leaf_510_core_clk/Z (CLKBUF_X16_7T5P0) |
| 8 0.03 soc/clknet_leaf_510_core_clk (net) |
| 0.11 0.00 6.20 ^ soc/_46495_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.60 6.81 v soc/_46495_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl135_regs0 (net) |
| 0.10 0.00 6.81 v soc/_46496_/D (DFFQ_X1_7T5P0) |
| 6.81 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 4.83 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.29 5.12 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 5.12 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.31 5.43 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.01 5.44 ^ soc/clkbuf_4_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.17 0.31 5.75 ^ soc/clkbuf_4_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_4_10_0_core_clk (net) |
| 0.17 0.00 5.75 ^ soc/clkbuf_5_20_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.17 0.31 6.06 ^ soc/clkbuf_5_20_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_20_0_core_clk (net) |
| 0.17 0.00 6.07 ^ soc/clkbuf_6_41_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.42 0.47 6.54 ^ soc/clkbuf_6_41_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.19 soc/clknet_6_41_0_core_clk (net) |
| 0.42 0.00 6.54 ^ soc/clkbuf_leaf_510_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.11 0.31 6.85 ^ soc/clkbuf_leaf_510_core_clk/Z (CLKBUF_X16_7T5P0) |
| 8 0.03 soc/clknet_leaf_510_core_clk (net) |
| 0.11 0.00 6.85 ^ soc/_46496_/CLK (DFFQ_X1_7T5P0) |
| 0.25 7.10 clock uncertainty |
| -0.65 6.45 clock reconvergence pessimism |
| 0.09 6.54 library hold time |
| 6.54 data required time |
| ----------------------------------------------------------------------------- |
| 6.54 data required time |
| -6.81 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.27 slack (MET) |
| |
| |
| Startpoint: soc/_44436_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44711_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 0.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 0.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 1.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 1.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 1.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 1.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 2.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 2.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 2.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 3.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 3.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 3.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 3.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 3.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 3.97 ^ soc/clkbuf_3_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.10 0.24 4.21 ^ soc/clkbuf_3_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_0_0_core_clk (net) |
| 0.10 0.00 4.21 ^ soc/clkbuf_3_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.27 4.49 ^ soc/clkbuf_3_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_3_0_1_core_clk (net) |
| 0.18 0.00 4.49 ^ soc/clkbuf_4_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.25 4.74 ^ soc/clkbuf_4_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.03 soc/clknet_4_0_0_core_clk (net) |
| 0.13 0.00 4.74 ^ soc/clkbuf_5_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.21 0.29 5.03 ^ soc/clkbuf_5_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.08 soc/clknet_5_0_0_core_clk (net) |
| 0.21 0.00 5.04 ^ soc/clkbuf_6_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.62 0.54 5.58 ^ soc/clkbuf_6_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.29 soc/clknet_6_1_0_core_clk (net) |
| 0.62 0.01 5.59 ^ soc/clkbuf_leaf_18_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.35 5.94 ^ soc/clkbuf_leaf_18_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.09 soc/clknet_leaf_18_core_clk (net) |
| 0.16 0.00 5.94 ^ soc/_44436_/CLK (DFFQ_X1_7T5P0) |
| 0.10 0.61 6.55 v soc/_44436_/Q (DFFQ_X1_7T5P0) |
| 1 0.00 soc/core.multiregimpl1_regs0 (net) |
| 0.10 0.00 6.55 v soc/_44711_/D (DFFQ_X1_7T5P0) |
| 6.55 data arrival time |
| |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.32 4.04 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 4.38 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.01 4.39 ^ soc/clkbuf_3_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.10 0.27 4.66 ^ soc/clkbuf_3_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_0_0_core_clk (net) |
| 0.10 0.00 4.66 ^ soc/clkbuf_3_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.30 4.96 ^ soc/clkbuf_3_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_3_0_1_core_clk (net) |
| 0.18 0.00 4.96 ^ soc/clkbuf_4_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.28 5.24 ^ soc/clkbuf_4_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.03 soc/clknet_4_0_0_core_clk (net) |
| 0.13 0.00 5.24 ^ soc/clkbuf_5_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.21 0.33 5.56 ^ soc/clkbuf_5_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.08 soc/clknet_5_0_0_core_clk (net) |
| 0.21 0.00 5.57 ^ soc/clkbuf_6_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.62 0.60 6.17 ^ soc/clkbuf_6_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.29 soc/clknet_6_1_0_core_clk (net) |
| 0.62 0.01 6.18 ^ soc/clkbuf_leaf_18_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.39 6.56 ^ soc/clkbuf_leaf_18_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.09 soc/clknet_leaf_18_core_clk (net) |
| 0.16 0.00 6.57 ^ soc/_44711_/CLK (DFFQ_X1_7T5P0) |
| 0.25 6.82 clock uncertainty |
| -0.63 6.19 clock reconvergence pessimism |
| 0.10 6.29 library hold time |
| 6.29 data required time |
| ----------------------------------------------------------------------------- |
| 6.29 data required time |
| -6.55 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.27 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11216_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.69 0.14 17.12 ^ housekeeping/_11216_/SETN (DFFSNQ_X1_7T5P0) |
| 17.12 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 28.15 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.53 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 28.54 ^ housekeeping/_11216_/CLK (DFFSNQ_X1_7T5P0) |
| -0.25 28.29 clock uncertainty |
| 0.20 28.49 clock reconvergence pessimism |
| -0.04 28.45 library recovery time |
| 28.45 data required time |
| ----------------------------------------------------------------------------- |
| 28.45 data required time |
| -17.12 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.32 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11678_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.19 17.17 ^ housekeeping/_11678_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.02 28.59 ^ housekeeping/_11678_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.52 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11679_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.19 17.17 ^ housekeeping/_11679_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.02 28.59 ^ housekeeping/_11679_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.52 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11681_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.19 17.17 ^ housekeeping/_11681_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.02 28.59 ^ housekeeping/_11681_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.52 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11680_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.19 17.17 ^ housekeeping/_11680_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 28.59 ^ housekeeping/_11680_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.52 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11676_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.19 17.17 ^ housekeeping/_11676_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 28.59 ^ housekeeping/_11676_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.53 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11675_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.18 17.17 ^ housekeeping/_11675_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 28.59 ^ housekeeping/_11675_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.53 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11254_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.18 17.17 ^ housekeeping/_11254_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 28.59 ^ housekeeping/_11254_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.53 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11255_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.75 0.18 17.17 ^ housekeeping/_11255_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 28.59 ^ housekeeping/_11255_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.53 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11682_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.74 0.18 17.16 ^ housekeeping/_11682_/RN (DFFRNQ_X1_7T5P0) |
| 17.16 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.00 28.58 ^ housekeeping/_11682_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.33 clock uncertainty |
| 0.20 28.53 clock reconvergence pessimism |
| 0.16 28.69 library recovery time |
| 28.69 data required time |
| ----------------------------------------------------------------------------- |
| 28.69 data required time |
| -17.16 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.53 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11677_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.74 0.18 17.17 ^ housekeeping/_11677_/RN (DFFRNQ_X1_7T5P0) |
| 17.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.01 28.59 ^ housekeeping/_11677_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.34 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.16 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.53 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11222_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.69 0.14 17.12 ^ housekeeping/_11222_/RN (DFFRNQ_X1_7T5P0) |
| 17.12 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 28.15 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.53 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 28.54 ^ housekeeping/_11222_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.29 clock uncertainty |
| 0.20 28.49 clock reconvergence pessimism |
| 0.17 28.65 library recovery time |
| 28.65 data required time |
| ----------------------------------------------------------------------------- |
| 28.65 data required time |
| -17.12 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.53 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11218_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.69 0.14 17.12 ^ housekeeping/_11218_/RN (DFFRNQ_X1_7T5P0) |
| 17.12 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 28.15 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.53 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 28.54 ^ housekeeping/_11218_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.29 clock uncertainty |
| 0.20 28.49 clock reconvergence pessimism |
| 0.17 28.65 library recovery time |
| 28.65 data required time |
| ----------------------------------------------------------------------------- |
| 28.65 data required time |
| -17.12 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.53 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11220_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.70 0.15 17.13 ^ housekeeping/_11220_/RN (DFFRNQ_X1_7T5P0) |
| 17.13 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.02 28.17 ^ housekeeping/clkbuf_3_5__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.55 ^ housekeeping/clkbuf_3_5__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 38 0.18 housekeeping/clknet_3_5__leaf_wb_clk_i (net) |
| 0.23 0.01 28.56 ^ housekeeping/_11220_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.31 clock uncertainty |
| 0.20 28.51 clock reconvergence pessimism |
| 0.17 28.67 library recovery time |
| 28.67 data required time |
| ----------------------------------------------------------------------------- |
| 28.67 data required time |
| -17.13 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.54 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11225_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.17 17.15 ^ housekeeping/_11225_/RN (DFFRNQ_X1_7T5P0) |
| 17.15 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.00 28.58 ^ housekeeping/_11225_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.33 clock uncertainty |
| 0.20 28.53 clock reconvergence pessimism |
| 0.16 28.69 library recovery time |
| 28.69 data required time |
| ----------------------------------------------------------------------------- |
| 28.69 data required time |
| -17.15 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.54 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11219_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.68 0.13 17.11 ^ housekeeping/_11219_/RN (DFFRNQ_X1_7T5P0) |
| 17.11 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 28.15 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.53 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.00 28.54 ^ housekeeping/_11219_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.29 clock uncertainty |
| 0.20 28.49 clock reconvergence pessimism |
| 0.17 28.66 library recovery time |
| 28.66 data required time |
| ----------------------------------------------------------------------------- |
| 28.66 data required time |
| -17.11 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.55 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11666_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.68 0.13 17.11 ^ housekeeping/_11666_/RN (DFFRNQ_X1_7T5P0) |
| 17.11 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 28.15 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.53 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.01 28.54 ^ housekeeping/_11666_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.29 clock uncertainty |
| 0.20 28.49 clock reconvergence pessimism |
| 0.17 28.66 library recovery time |
| 28.66 data required time |
| ----------------------------------------------------------------------------- |
| 28.66 data required time |
| -17.11 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.55 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11259_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.16 17.15 ^ housekeeping/_11259_/RN (DFFRNQ_X1_7T5P0) |
| 17.15 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.00 28.58 ^ housekeeping/_11259_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.33 clock uncertainty |
| 0.20 28.53 clock reconvergence pessimism |
| 0.17 28.69 library recovery time |
| 28.69 data required time |
| ----------------------------------------------------------------------------- |
| 28.69 data required time |
| -17.15 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.55 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11684_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.16 17.15 ^ housekeeping/_11684_/RN (DFFRNQ_X1_7T5P0) |
| 17.15 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.18 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.26 0.40 28.58 ^ housekeeping/clkbuf_3_7__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 28 0.21 housekeeping/clknet_3_7__leaf_wb_clk_i (net) |
| 0.26 0.00 28.58 ^ housekeeping/_11684_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.33 clock uncertainty |
| 0.20 28.53 clock reconvergence pessimism |
| 0.17 28.70 library recovery time |
| 28.70 data required time |
| ----------------------------------------------------------------------------- |
| 28.70 data required time |
| -17.15 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.55 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11205_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.71 0.16 17.14 ^ housekeeping/_11205_/RN (DFFRNQ_X2_7T5P0) |
| 17.14 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.17 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.42 28.59 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 28.60 ^ housekeeping/_11205_/CLK (DFFRNQ_X2_7T5P0) |
| -0.25 28.35 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.15 28.69 library recovery time |
| 28.69 data required time |
| ----------------------------------------------------------------------------- |
| 28.69 data required time |
| -17.14 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.55 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11217_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.69 0.14 17.12 ^ housekeeping/_11217_/RN (DFFRNQ_X1_7T5P0) |
| 17.12 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.02 28.17 ^ housekeeping/clkbuf_3_5__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.55 ^ housekeeping/clkbuf_3_5__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 38 0.18 housekeeping/clknet_3_5__leaf_wb_clk_i (net) |
| 0.23 0.01 28.56 ^ housekeeping/_11217_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.31 clock uncertainty |
| 0.20 28.51 clock reconvergence pessimism |
| 0.17 28.68 library recovery time |
| 28.68 data required time |
| ----------------------------------------------------------------------------- |
| 28.68 data required time |
| -17.12 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.55 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11256_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.67 0.12 17.10 ^ housekeeping/_11256_/RN (DFFRNQ_X1_7T5P0) |
| 17.10 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 28.15 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.53 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.00 28.54 ^ housekeeping/_11256_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.29 clock uncertainty |
| 0.20 28.49 clock reconvergence pessimism |
| 0.17 28.66 library recovery time |
| 28.66 data required time |
| ----------------------------------------------------------------------------- |
| 28.66 data required time |
| -17.10 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.56 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11260_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.65 0.11 17.09 ^ housekeeping/_11260_/RN (DFFRNQ_X1_7T5P0) |
| 17.09 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.49 0.00 28.15 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.23 0.38 28.53 ^ housekeeping/clkbuf_3_4__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 26 0.18 housekeeping/clknet_3_4__leaf_wb_clk_i (net) |
| 0.23 0.00 28.54 ^ housekeeping/_11260_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.29 clock uncertainty |
| 0.20 28.49 clock reconvergence pessimism |
| 0.18 28.66 library recovery time |
| 28.66 data required time |
| ----------------------------------------------------------------------------- |
| 28.66 data required time |
| -17.09 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.57 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11223_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.16 17.15 ^ housekeeping/_11223_/RN (DFFRNQ_X1_7T5P0) |
| 17.15 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.17 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.42 28.59 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 28.60 ^ housekeeping/_11223_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.35 clock uncertainty |
| 0.20 28.55 clock reconvergence pessimism |
| 0.17 28.72 library recovery time |
| 28.72 data required time |
| ----------------------------------------------------------------------------- |
| 28.72 data required time |
| -17.15 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.57 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11258_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.72 0.16 17.14 ^ housekeeping/_11258_/RN (DFFRNQ_X1_7T5P0) |
| 17.14 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.17 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.42 28.59 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 28.60 ^ housekeeping/_11258_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.35 clock uncertainty |
| 0.20 28.55 clock reconvergence pessimism |
| 0.17 28.72 library recovery time |
| 28.72 data required time |
| ----------------------------------------------------------------------------- |
| 28.72 data required time |
| -17.14 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.57 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11257_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.71 0.16 17.14 ^ housekeeping/_11257_/RN (DFFRNQ_X1_7T5P0) |
| 17.14 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.17 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.42 28.59 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 28.60 ^ housekeeping/_11257_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.35 clock uncertainty |
| 0.20 28.55 clock reconvergence pessimism |
| 0.17 28.72 library recovery time |
| 28.72 data required time |
| ----------------------------------------------------------------------------- |
| 28.72 data required time |
| -17.14 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.58 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11683_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.71 0.16 17.14 ^ housekeeping/_11683_/RN (DFFRNQ_X1_7T5P0) |
| 17.14 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.17 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.42 28.59 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 28.60 ^ housekeeping/_11683_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.35 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.17 28.72 library recovery time |
| 28.72 data required time |
| ----------------------------------------------------------------------------- |
| 28.72 data required time |
| -17.14 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.58 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11224_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.71 0.15 17.14 ^ housekeeping/_11224_/RN (DFFRNQ_X1_7T5P0) |
| 17.14 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.17 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.42 28.59 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 28.60 ^ housekeeping/_11224_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.35 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.18 28.72 library recovery time |
| 28.72 data required time |
| ----------------------------------------------------------------------------- |
| 28.72 data required time |
| -17.14 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.58 slack (MET) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: housekeeping/_11221_ (recovery check against rising-edge clock clock) |
| Path Group: **async_default** |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 12.50 12.50 clock clock (fall edge) |
| 0.00 12.50 clock source latency |
| 0.00 0.00 12.50 v clock (in) |
| 1 2.99 clock (net) |
| 0.00 0.00 12.50 v padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.10 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.10 0.00 13.37 v clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.15 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.15 0.00 13.77 v clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.13 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.13 0.00 14.15 v clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.36 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.36 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.23 0.88 15.47 v clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 1 0.02 clock_ctrl/reset_delay[0] (net) |
| 0.23 0.00 15.47 v clock_ctrl/_246_/A2 (NOR2_X1_7T5P0) |
| 0.39 0.30 15.77 ^ clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 1 0.01 clock_ctrl/_049_ (net) |
| 0.39 0.00 15.77 ^ clock_ctrl/_247_/I (CLKBUF_X1_7T5P0) |
| 0.42 0.45 16.22 ^ clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 1 0.02 clock_ctrl/net13 (net) |
| 0.42 0.00 16.22 ^ clock_ctrl/output13/I (BUF_X4_7T5P0) |
| 0.17 0.26 16.49 ^ clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 6 0.03 caravel_rstn (net) |
| 0.17 0.00 16.49 ^ housekeeping/input162/I (CLKBUF_X16_7T5P0) |
| 0.58 0.50 16.99 ^ housekeeping/input162/Z (CLKBUF_X16_7T5P0) |
| 66 0.62 housekeeping/net162 (net) |
| 0.70 0.15 17.13 ^ housekeeping/_11221_/RN (DFFRNQ_X1_7T5P0) |
| 17.13 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ housekeeping/clkbuf_0_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.49 0.58 28.15 ^ housekeeping/clkbuf_0_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 16 0.46 housekeeping/clknet_0_wb_clk_i (net) |
| 0.50 0.03 28.17 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/I (CLKBUF_X16_7T5P0) |
| 0.29 0.42 28.59 ^ housekeeping/clkbuf_3_6__f_wb_clk_i/Z (CLKBUF_X16_7T5P0) |
| 32 0.25 housekeeping/clknet_3_6__leaf_wb_clk_i (net) |
| 0.29 0.00 28.60 ^ housekeeping/_11221_/CLK (DFFRNQ_X1_7T5P0) |
| -0.25 28.35 clock uncertainty |
| 0.20 28.54 clock reconvergence pessimism |
| 0.18 28.72 library recovery time |
| 28.72 data required time |
| ----------------------------------------------------------------------------- |
| 28.72 data required time |
| -17.13 data arrival time |
| ----------------------------------------------------------------------------- |
| 11.59 slack (MET) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44447_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21336_/I (CLKBUF_X2_7T5P0) |
| 1.94 1.55 43.04 v soc/_21336_/Z (CLKBUF_X2_7T5P0) |
| 16 0.25 soc/_20548_ (net) |
| 1.95 0.02 43.06 v soc/_26778_/A1 (NOR2_X2_7T5P0) |
| 12.01 7.55 50.61 ^ soc/_26778_/ZN (NOR2_X2_7T5P0) |
| 14 0.83 soc/_08573_ (net) |
| 12.03 0.25 50.86 ^ soc/_34438_/I (CLKBUF_X2_7T5P0) |
| 5.26 4.17 55.03 ^ soc/_34438_/Z (CLKBUF_X2_7T5P0) |
| 16 0.69 soc/_14448_ (net) |
| 5.26 0.01 55.03 ^ soc/_34473_/A1 (NAND4_X1_7T5P0) |
| 11.30 8.29 63.32 v soc/_34473_/ZN (NAND4_X1_7T5P0) |
| 2 0.46 soc/_14483_ (net) |
| 11.30 0.11 63.44 v soc/_34474_/B (OAI21_X1_7T5P0) |
| 2.03 2.49 65.92 ^ soc/_34474_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14484_ (net) |
| 2.03 0.00 65.92 ^ soc/_34475_/I (CLKBUF_X1_7T5P0) |
| 0.16 0.39 66.31 ^ soc/_34475_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02517_ (net) |
| 0.16 0.00 66.31 ^ soc/_44447_/D (DFFQ_X1_7T5P0) |
| 66.31 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.38 31.02 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 31.02 ^ soc/clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 31.61 ^ soc/clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.32 soc/clknet_6_32_0_core_clk (net) |
| 0.68 0.01 31.63 ^ soc/clkbuf_leaf_439_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.36 31.99 ^ soc/clkbuf_leaf_439_core_clk/Z (CLKBUF_X16_7T5P0) |
| 14 0.09 soc/clknet_leaf_439_core_clk (net) |
| 0.16 0.00 31.99 ^ soc/_44447_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.74 clock uncertainty |
| 0.31 32.05 clock reconvergence pessimism |
| -0.21 31.84 library setup time |
| 31.84 data required time |
| ----------------------------------------------------------------------------- |
| 31.84 data required time |
| -66.31 data arrival time |
| ----------------------------------------------------------------------------- |
| -34.47 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43707_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21336_/I (CLKBUF_X2_7T5P0) |
| 1.94 1.55 43.04 v soc/_21336_/Z (CLKBUF_X2_7T5P0) |
| 16 0.25 soc/_20548_ (net) |
| 1.95 0.02 43.06 v soc/_26778_/A1 (NOR2_X2_7T5P0) |
| 12.01 7.55 50.61 ^ soc/_26778_/ZN (NOR2_X2_7T5P0) |
| 14 0.83 soc/_08573_ (net) |
| 12.03 0.23 50.84 ^ soc/_26799_/I (CLKBUF_X2_7T5P0) |
| 6.38 4.97 55.81 ^ soc/_26799_/Z (CLKBUF_X2_7T5P0) |
| 16 0.85 soc/_08591_ (net) |
| 6.38 0.13 55.94 ^ soc/_31491_/A1 (NAND4_X2_7T5P0) |
| 5.68 4.61 60.55 v soc/_31491_/ZN (NAND4_X2_7T5P0) |
| 4 0.43 soc/_12337_ (net) |
| 5.69 0.07 60.63 v soc/_31907_/A1 (AOI21_X1_7T5P0) |
| 1.33 1.52 62.15 ^ soc/_31907_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_12617_ (net) |
| 1.33 0.00 62.15 ^ soc/_31908_/I (CLKBUF_X1_7T5P0) |
| 0.14 0.34 62.49 ^ soc/_31908_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_01817_ (net) |
| 0.14 0.00 62.49 ^ soc/_43707_/D (DFFQ_X1_7T5P0) |
| 62.49 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 30.24 ^ soc/clkbuf_5_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_5_0_core_clk (net) |
| 0.19 0.00 30.24 ^ soc/clkbuf_6_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.54 0.49 30.74 ^ soc/clkbuf_6_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.25 soc/clknet_6_10_0_core_clk (net) |
| 0.54 0.01 30.74 ^ soc/clkbuf_leaf_47_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.10 0.30 31.04 ^ soc/clkbuf_leaf_47_core_clk/Z (CLKBUF_X16_7T5P0) |
| 3 0.02 soc/clknet_leaf_47_core_clk (net) |
| 0.10 0.00 31.04 ^ soc/_43707_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.79 clock uncertainty |
| 0.35 31.14 clock reconvergence pessimism |
| -0.22 30.92 library setup time |
| 30.92 data required time |
| ----------------------------------------------------------------------------- |
| 30.92 data required time |
| -62.49 data arrival time |
| ----------------------------------------------------------------------------- |
| -31.57 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43524_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21336_/I (CLKBUF_X2_7T5P0) |
| 1.94 1.55 43.04 v soc/_21336_/Z (CLKBUF_X2_7T5P0) |
| 16 0.25 soc/_20548_ (net) |
| 1.95 0.02 43.06 v soc/_26778_/A1 (NOR2_X2_7T5P0) |
| 12.01 7.55 50.61 ^ soc/_26778_/ZN (NOR2_X2_7T5P0) |
| 14 0.83 soc/_08573_ (net) |
| 12.03 0.23 50.84 ^ soc/_26799_/I (CLKBUF_X2_7T5P0) |
| 6.38 4.97 55.81 ^ soc/_26799_/Z (CLKBUF_X2_7T5P0) |
| 16 0.85 soc/_08591_ (net) |
| 6.38 0.13 55.94 ^ soc/_31491_/A1 (NAND4_X2_7T5P0) |
| 5.68 4.61 60.55 v soc/_31491_/ZN (NAND4_X2_7T5P0) |
| 4 0.43 soc/_12337_ (net) |
| 5.68 0.00 60.56 v soc/_31492_/A2 (AOI21_X1_7T5P0) |
| 1.35 1.78 62.34 ^ soc/_31492_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_12338_ (net) |
| 1.35 0.00 62.34 ^ soc/_31493_/I (CLKBUF_X1_7T5P0) |
| 0.17 0.37 62.71 ^ soc/_31493_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_01681_ (net) |
| 0.17 0.00 62.71 ^ soc/_43524_/D (DFFQ_X1_7T5P0) |
| 62.71 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.38 31.02 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 31.02 ^ soc/clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 31.61 ^ soc/clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.32 soc/clknet_6_32_0_core_clk (net) |
| 0.68 0.01 31.63 ^ soc/clkbuf_leaf_439_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.36 31.99 ^ soc/clkbuf_leaf_439_core_clk/Z (CLKBUF_X16_7T5P0) |
| 14 0.09 soc/clknet_leaf_439_core_clk (net) |
| 0.16 0.00 31.99 ^ soc/_43524_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.74 clock uncertainty |
| 0.31 32.05 clock reconvergence pessimism |
| -0.21 31.84 library setup time |
| 31.84 data required time |
| ----------------------------------------------------------------------------- |
| 31.84 data required time |
| -62.71 data arrival time |
| ----------------------------------------------------------------------------- |
| -30.87 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44364_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_28689_/I (CLKBUF_X2_7T5P0) |
| 5.11 4.22 59.16 v soc/_28689_/Z (CLKBUF_X2_7T5P0) |
| 16 0.67 soc/_10020_ (net) |
| 5.11 0.02 59.18 v soc/_34229_/A2 (OAI21_X1_7T5P0) |
| 1.15 1.12 60.29 ^ soc/_34229_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14322_ (net) |
| 1.15 0.00 60.29 ^ soc/_34230_/I (CLKBUF_X1_7T5P0) |
| 0.17 0.36 60.65 ^ soc/_34230_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_02434_ (net) |
| 0.17 0.00 60.65 ^ soc/_44364_/D (DFFQ_X1_7T5P0) |
| 60.65 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 30.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 30.64 ^ soc/clkbuf_leaf_61_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 30.95 ^ soc/clkbuf_leaf_61_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_61_core_clk (net) |
| 0.13 0.00 30.95 ^ soc/_44364_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.70 clock uncertainty |
| 0.35 31.05 clock reconvergence pessimism |
| -0.22 30.84 library setup time |
| 30.84 data required time |
| ----------------------------------------------------------------------------- |
| 30.84 data required time |
| -60.65 data arrival time |
| ----------------------------------------------------------------------------- |
| -29.81 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44359_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_28689_/I (CLKBUF_X2_7T5P0) |
| 5.11 4.22 59.16 v soc/_28689_/Z (CLKBUF_X2_7T5P0) |
| 16 0.67 soc/_10020_ (net) |
| 5.11 0.01 59.17 v soc/_34216_/A2 (OAI21_X1_7T5P0) |
| 1.13 1.10 60.27 ^ soc/_34216_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14314_ (net) |
| 1.13 0.00 60.27 ^ soc/_34217_/I (CLKBUF_X1_7T5P0) |
| 0.18 0.37 60.64 ^ soc/_34217_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_02429_ (net) |
| 0.18 0.00 60.64 ^ soc/_44359_/D (DFFQ_X1_7T5P0) |
| 60.64 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 30.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 30.64 ^ soc/clkbuf_leaf_61_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 30.95 ^ soc/clkbuf_leaf_61_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_61_core_clk (net) |
| 0.13 0.00 30.95 ^ soc/_44359_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.70 clock uncertainty |
| 0.35 31.05 clock reconvergence pessimism |
| -0.22 30.84 library setup time |
| 30.84 data required time |
| ----------------------------------------------------------------------------- |
| 30.84 data required time |
| -60.64 data arrival time |
| ----------------------------------------------------------------------------- |
| -29.80 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44360_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_28689_/I (CLKBUF_X2_7T5P0) |
| 5.11 4.22 59.16 v soc/_28689_/Z (CLKBUF_X2_7T5P0) |
| 16 0.67 soc/_10020_ (net) |
| 5.11 0.02 59.18 v soc/_34219_/A2 (OAI21_X1_7T5P0) |
| 1.12 1.08 60.26 ^ soc/_34219_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14316_ (net) |
| 1.12 0.00 60.26 ^ soc/_34220_/I (CLKBUF_X1_7T5P0) |
| 0.19 0.37 60.63 ^ soc/_34220_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_02430_ (net) |
| 0.19 0.00 60.63 ^ soc/_44360_/D (DFFQ_X1_7T5P0) |
| 60.63 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 30.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 30.64 ^ soc/clkbuf_leaf_61_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 30.95 ^ soc/clkbuf_leaf_61_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_61_core_clk (net) |
| 0.13 0.00 30.95 ^ soc/_44360_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.70 clock uncertainty |
| 0.35 31.05 clock reconvergence pessimism |
| -0.22 30.83 library setup time |
| 30.83 data required time |
| ----------------------------------------------------------------------------- |
| 30.83 data required time |
| -60.63 data arrival time |
| ----------------------------------------------------------------------------- |
| -29.80 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44370_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_28689_/I (CLKBUF_X2_7T5P0) |
| 5.11 4.22 59.16 v soc/_28689_/Z (CLKBUF_X2_7T5P0) |
| 16 0.67 soc/_10020_ (net) |
| 5.11 0.06 59.21 v soc/_34244_/A2 (OAI21_X1_7T5P0) |
| 1.09 1.05 60.26 ^ soc/_34244_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14331_ (net) |
| 1.09 0.00 60.26 ^ soc/_34245_/I (CLKBUF_X1_7T5P0) |
| 0.18 0.36 60.63 ^ soc/_34245_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_02440_ (net) |
| 0.18 0.00 60.63 ^ soc/_44370_/D (DFFQ_X1_7T5P0) |
| 60.63 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 30.24 ^ soc/clkbuf_5_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_5_0_core_clk (net) |
| 0.19 0.00 30.24 ^ soc/clkbuf_6_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.52 0.48 30.73 ^ soc/clkbuf_6_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.24 soc/clknet_6_11_0_core_clk (net) |
| 0.52 0.01 30.73 ^ soc/clkbuf_leaf_49_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.30 31.04 ^ soc/clkbuf_leaf_49_core_clk/Z (CLKBUF_X16_7T5P0) |
| 5 0.04 soc/clknet_leaf_49_core_clk (net) |
| 0.12 0.00 31.04 ^ soc/_44370_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.79 clock uncertainty |
| 0.35 31.14 clock reconvergence pessimism |
| -0.22 30.92 library setup time |
| 30.92 data required time |
| ----------------------------------------------------------------------------- |
| 30.92 data required time |
| -60.63 data arrival time |
| ----------------------------------------------------------------------------- |
| -29.71 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44358_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_28689_/I (CLKBUF_X2_7T5P0) |
| 5.11 4.22 59.16 v soc/_28689_/Z (CLKBUF_X2_7T5P0) |
| 16 0.67 soc/_10020_ (net) |
| 5.11 0.01 59.17 v soc/_34213_/A2 (OAI21_X1_7T5P0) |
| 0.99 0.96 60.13 ^ soc/_34213_/ZN (OAI21_X1_7T5P0) |
| 1 0.00 soc/_14312_ (net) |
| 0.99 0.00 60.13 ^ soc/_34214_/I (CLKBUF_X1_7T5P0) |
| 0.14 0.32 60.46 ^ soc/_34214_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02428_ (net) |
| 0.14 0.00 60.46 ^ soc/_44358_/D (DFFQ_X1_7T5P0) |
| 60.46 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 30.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 30.64 ^ soc/clkbuf_leaf_61_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 30.95 ^ soc/clkbuf_leaf_61_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_61_core_clk (net) |
| 0.13 0.00 30.95 ^ soc/_44358_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.70 clock uncertainty |
| 0.35 31.05 clock reconvergence pessimism |
| -0.21 30.84 library setup time |
| 30.84 data required time |
| ----------------------------------------------------------------------------- |
| 30.84 data required time |
| -60.46 data arrival time |
| ----------------------------------------------------------------------------- |
| -29.62 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44372_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_28689_/I (CLKBUF_X2_7T5P0) |
| 5.11 4.22 59.16 v soc/_28689_/Z (CLKBUF_X2_7T5P0) |
| 16 0.67 soc/_10020_ (net) |
| 5.11 0.06 59.21 v soc/_34249_/A2 (OAI21_X1_7T5P0) |
| 1.01 0.98 60.19 ^ soc/_34249_/ZN (OAI21_X1_7T5P0) |
| 1 0.00 soc/_14334_ (net) |
| 1.01 0.00 60.19 ^ soc/_34250_/I (CLKBUF_X1_7T5P0) |
| 0.12 0.32 60.51 ^ soc/_34250_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02442_ (net) |
| 0.12 0.00 60.51 ^ soc/_44372_/D (DFFQ_X1_7T5P0) |
| 60.51 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.30 30.24 ^ soc/clkbuf_5_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_5_0_core_clk (net) |
| 0.19 0.00 30.24 ^ soc/clkbuf_6_10_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.54 0.49 30.74 ^ soc/clkbuf_6_10_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.25 soc/clknet_6_10_0_core_clk (net) |
| 0.54 0.01 30.75 ^ soc/clkbuf_leaf_46_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.36 31.10 ^ soc/clkbuf_leaf_46_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.12 soc/clknet_leaf_46_core_clk (net) |
| 0.18 0.00 31.11 ^ soc/_44372_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.86 clock uncertainty |
| 0.35 31.21 clock reconvergence pessimism |
| -0.20 31.01 library setup time |
| 31.01 data required time |
| ----------------------------------------------------------------------------- |
| 31.01 data required time |
| -60.51 data arrival time |
| ----------------------------------------------------------------------------- |
| -29.50 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43003_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_28689_/I (CLKBUF_X2_7T5P0) |
| 5.11 4.22 59.16 v soc/_28689_/Z (CLKBUF_X2_7T5P0) |
| 16 0.67 soc/_10020_ (net) |
| 5.13 0.18 59.34 v soc/_28745_/A2 (AOI21_X1_7T5P0) |
| 1.03 1.61 60.95 ^ soc/_28745_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10076_ (net) |
| 1.03 0.00 60.95 ^ soc/_28746_/I (CLKINV_X1_7T5P0) |
| 0.31 0.22 61.17 v soc/_28746_/ZN (CLKINV_X1_7T5P0) |
| 1 0.01 soc/_01196_ (net) |
| 0.31 0.00 61.17 v soc/_43003_/D (DFFQ_X1_7T5P0) |
| 61.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.38 31.02 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 31.02 ^ soc/clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 31.61 ^ soc/clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.32 soc/clknet_6_32_0_core_clk (net) |
| 0.68 0.01 31.63 ^ soc/clkbuf_leaf_438_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.36 31.98 ^ soc/clkbuf_leaf_438_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.09 soc/clknet_leaf_438_core_clk (net) |
| 0.16 0.00 31.98 ^ soc/_43003_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.73 clock uncertainty |
| 0.31 32.04 clock reconvergence pessimism |
| -0.28 31.76 library setup time |
| 31.76 data required time |
| ----------------------------------------------------------------------------- |
| 31.76 data required time |
| -61.17 data arrival time |
| ----------------------------------------------------------------------------- |
| -29.41 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43004_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_28689_/I (CLKBUF_X2_7T5P0) |
| 5.11 4.22 59.16 v soc/_28689_/Z (CLKBUF_X2_7T5P0) |
| 16 0.67 soc/_10020_ (net) |
| 5.13 0.18 59.34 v soc/_28757_/A2 (AOI21_X1_7T5P0) |
| 1.01 1.60 60.93 ^ soc/_28757_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10087_ (net) |
| 1.01 0.00 60.93 ^ soc/_28758_/I (CLKINV_X1_7T5P0) |
| 0.26 0.16 61.10 v soc/_28758_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01197_ (net) |
| 0.26 0.00 61.10 v soc/_43004_/D (DFFQ_X1_7T5P0) |
| 61.10 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.38 31.02 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 31.02 ^ soc/clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 31.61 ^ soc/clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.32 soc/clknet_6_32_0_core_clk (net) |
| 0.68 0.01 31.63 ^ soc/clkbuf_leaf_438_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.36 31.98 ^ soc/clkbuf_leaf_438_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.09 soc/clknet_leaf_438_core_clk (net) |
| 0.16 0.00 31.98 ^ soc/_43004_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.73 clock uncertainty |
| 0.31 32.04 clock reconvergence pessimism |
| -0.26 31.78 library setup time |
| 31.78 data required time |
| ----------------------------------------------------------------------------- |
| 31.78 data required time |
| -61.10 data arrival time |
| ----------------------------------------------------------------------------- |
| -29.32 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44348_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_34178_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_34178_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_14288_ (net) |
| 1.54 0.01 56.87 v soc/_34184_/A2 (OAI21_X1_7T5P0) |
| 0.87 0.74 57.61 ^ soc/_34184_/ZN (OAI21_X1_7T5P0) |
| 1 0.02 soc/_14293_ (net) |
| 0.87 0.00 57.61 ^ soc/_34185_/I (CLKBUF_X1_7T5P0) |
| 0.16 0.33 57.94 ^ soc/_34185_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_02418_ (net) |
| 0.16 0.00 57.94 ^ soc/_44348_/D (DFFQ_X1_7T5P0) |
| 57.94 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.37 0.39 30.60 ^ soc/clkbuf_6_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.17 soc/clknet_6_8_0_core_clk (net) |
| 0.37 0.00 30.60 ^ soc/clkbuf_leaf_53_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 30.89 ^ soc/clkbuf_leaf_53_core_clk/Z (CLKBUF_X16_7T5P0) |
| 8 0.05 soc/clknet_leaf_53_core_clk (net) |
| 0.12 0.00 30.89 ^ soc/_44348_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.64 clock uncertainty |
| 0.35 30.99 clock reconvergence pessimism |
| -0.22 30.77 library setup time |
| 30.77 data required time |
| ----------------------------------------------------------------------------- |
| 30.77 data required time |
| -57.94 data arrival time |
| ----------------------------------------------------------------------------- |
| -27.17 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44347_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_34178_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_34178_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_14288_ (net) |
| 1.54 0.01 56.87 v soc/_34180_/A2 (OAI21_X1_7T5P0) |
| 0.67 0.54 57.41 ^ soc/_34180_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14290_ (net) |
| 0.67 0.00 57.41 ^ soc/_34181_/I (CLKBUF_X1_7T5P0) |
| 0.15 0.31 57.72 ^ soc/_34181_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_02417_ (net) |
| 0.15 0.00 57.72 ^ soc/_44347_/D (DFFQ_X1_7T5P0) |
| 57.72 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.37 0.39 30.60 ^ soc/clkbuf_6_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.17 soc/clknet_6_8_0_core_clk (net) |
| 0.37 0.00 30.60 ^ soc/clkbuf_leaf_53_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.28 30.89 ^ soc/clkbuf_leaf_53_core_clk/Z (CLKBUF_X16_7T5P0) |
| 8 0.05 soc/clknet_leaf_53_core_clk (net) |
| 0.12 0.00 30.89 ^ soc/_44347_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.64 clock uncertainty |
| 0.35 30.99 clock reconvergence pessimism |
| -0.22 30.77 library setup time |
| 30.77 data required time |
| ----------------------------------------------------------------------------- |
| 30.77 data required time |
| -57.72 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.95 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_46294_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_23442_/A2 (AOI21_X1_7T5P0) |
| 2.84 1.82 43.31 ^ soc/_23442_/ZN (AOI21_X1_7T5P0) |
| 8 0.09 soc/_06016_ (net) |
| 2.84 0.01 43.31 ^ soc/_23453_/I (BUF_X1_7T5P0) |
| 9.15 5.68 49.00 ^ soc/_23453_/Z (BUF_X1_7T5P0) |
| 16 0.57 soc/_06027_ (net) |
| 9.15 0.15 49.15 ^ soc/_23484_/I (CLKBUF_X2_7T5P0) |
| 1.55 1.66 50.80 ^ soc/_23484_/Z (CLKBUF_X2_7T5P0) |
| 16 0.17 soc/_06058_ (net) |
| 1.55 0.00 50.81 ^ soc/_23645_/S1 (MUX4_X1_7T5P0) |
| 0.42 0.53 51.33 ^ soc/_23645_/Z (MUX4_X1_7T5P0) |
| 1 0.01 soc/_06212_ (net) |
| 0.42 0.00 51.33 ^ soc/_23646_/A2 (NOR2_X1_7T5P0) |
| 0.53 0.44 51.78 v soc/_23646_/ZN (NOR2_X1_7T5P0) |
| 1 0.03 soc/_06213_ (net) |
| 0.53 0.00 51.78 v soc/_23651_/A3 (OAI32_X1_7T5P0) |
| 10.68 6.50 58.28 ^ soc/_23651_/ZN (OAI32_X1_7T5P0) |
| 2 0.24 soc/_06218_ (net) |
| 10.68 0.03 58.31 ^ soc/_23652_/I1 (MUX2_X2_7T5P0) |
| 0.36 0.00 58.31 ^ soc/_23652_/Z (MUX2_X2_7T5P0) |
| 1 0.02 soc/_06219_ (net) |
| 0.36 0.00 58.31 ^ soc/_23653_/I (CLKBUF_X1_7T5P0) |
| 0.17 0.29 58.60 ^ soc/_23653_/Z (CLKBUF_X1_7T5P0) |
| 1 0.01 soc/_00029_ (net) |
| 0.17 0.00 58.60 ^ soc/_46294_/D (DFFQ_X1_7T5P0) |
| 58.60 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.35 29.02 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 29.02 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.34 29.36 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.01 29.37 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.26 29.63 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 29.64 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.35 29.98 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 29.99 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 30.36 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.01 30.36 ^ soc/clkbuf_5_25_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.33 30.69 ^ soc/clkbuf_5_25_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_25_0_core_clk (net) |
| 0.23 0.00 30.70 ^ soc/clkbuf_6_51_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.65 31.35 ^ soc/clkbuf_6_51_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.39 soc/clknet_6_51_0_core_clk (net) |
| 0.81 0.01 31.36 ^ soc/clkbuf_leaf_295_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.25 0.43 31.78 ^ soc/clkbuf_leaf_295_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.19 soc/clknet_leaf_295_core_clk (net) |
| 0.25 0.01 31.80 ^ soc/_46294_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.55 clock uncertainty |
| 0.31 31.85 clock reconvergence pessimism |
| -0.19 31.66 library setup time |
| 31.66 data required time |
| ----------------------------------------------------------------------------- |
| 31.66 data required time |
| -58.60 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.94 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44354_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_34178_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_34178_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_14288_ (net) |
| 1.54 0.00 56.87 v soc/_34201_/A2 (OAI21_X1_7T5P0) |
| 0.70 0.58 57.45 ^ soc/_34201_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14304_ (net) |
| 0.70 0.00 57.45 ^ soc/_34202_/I (CLKBUF_X1_7T5P0) |
| 0.12 0.29 57.73 ^ soc/_34202_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02424_ (net) |
| 0.12 0.00 57.73 ^ soc/_44354_/D (DFFQ_X1_7T5P0) |
| 57.73 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 30.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 30.64 ^ soc/clkbuf_leaf_60_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 30.95 ^ soc/clkbuf_leaf_60_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_60_core_clk (net) |
| 0.13 0.00 30.95 ^ soc/_44354_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.70 clock uncertainty |
| 0.35 31.06 clock reconvergence pessimism |
| -0.21 30.85 library setup time |
| 30.85 data required time |
| ----------------------------------------------------------------------------- |
| 30.85 data required time |
| -57.73 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.89 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44349_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_34178_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_34178_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_14288_ (net) |
| 1.54 0.00 56.86 v soc/_34187_/A2 (OAI21_X1_7T5P0) |
| 0.58 0.52 57.38 ^ soc/_34187_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14295_ (net) |
| 0.58 0.00 57.38 ^ soc/_34188_/I (CLKBUF_X1_7T5P0) |
| 0.12 0.28 57.66 ^ soc/_34188_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02419_ (net) |
| 0.12 0.00 57.66 ^ soc/_44349_/D (DFFQ_X1_7T5P0) |
| 57.66 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.37 0.39 30.60 ^ soc/clkbuf_6_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.17 soc/clknet_6_8_0_core_clk (net) |
| 0.37 0.00 30.60 ^ soc/clkbuf_leaf_55_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.12 0.29 30.89 ^ soc/clkbuf_leaf_55_core_clk/Z (CLKBUF_X16_7T5P0) |
| 7 0.05 soc/clknet_leaf_55_core_clk (net) |
| 0.12 0.00 30.89 ^ soc/_44349_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.64 clock uncertainty |
| 0.35 30.99 clock reconvergence pessimism |
| -0.21 30.78 library setup time |
| 30.78 data required time |
| ----------------------------------------------------------------------------- |
| 30.78 data required time |
| -57.66 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.89 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44352_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_34178_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_34178_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_14288_ (net) |
| 1.54 0.00 56.87 v soc/_34195_/A2 (OAI21_X1_7T5P0) |
| 0.56 0.53 57.40 ^ soc/_34195_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14300_ (net) |
| 0.56 0.00 57.40 ^ soc/_34196_/I (CLKBUF_X1_7T5P0) |
| 0.14 0.29 57.68 ^ soc/_34196_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02422_ (net) |
| 0.14 0.00 57.68 ^ soc/_44352_/D (DFFQ_X1_7T5P0) |
| 57.68 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.37 0.39 30.60 ^ soc/clkbuf_6_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.17 soc/clknet_6_8_0_core_clk (net) |
| 0.37 0.00 30.60 ^ soc/clkbuf_leaf_52_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.31 30.92 ^ soc/clkbuf_leaf_52_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.10 soc/clknet_leaf_52_core_clk (net) |
| 0.16 0.00 30.92 ^ soc/_44352_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.67 clock uncertainty |
| 0.35 31.02 clock reconvergence pessimism |
| -0.21 30.81 library setup time |
| 30.81 data required time |
| ----------------------------------------------------------------------------- |
| 30.81 data required time |
| -57.68 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.87 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44356_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_34178_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_34178_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_14288_ (net) |
| 1.54 0.00 56.87 v soc/_34207_/A2 (OAI21_X1_7T5P0) |
| 0.60 0.55 57.42 ^ soc/_34207_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14308_ (net) |
| 0.60 0.00 57.42 ^ soc/_34208_/I (CLKBUF_X1_7T5P0) |
| 0.11 0.28 57.69 ^ soc/_34208_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02426_ (net) |
| 0.11 0.00 57.69 ^ soc/_44356_/D (DFFQ_X1_7T5P0) |
| 57.69 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 30.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 30.64 ^ soc/clkbuf_leaf_60_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 30.95 ^ soc/clkbuf_leaf_60_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_60_core_clk (net) |
| 0.13 0.00 30.95 ^ soc/_44356_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.70 clock uncertainty |
| 0.35 31.06 clock reconvergence pessimism |
| -0.21 30.85 library setup time |
| 30.85 data required time |
| ----------------------------------------------------------------------------- |
| 30.85 data required time |
| -57.69 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.85 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44357_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_34178_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_34178_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_14288_ (net) |
| 1.54 0.00 56.86 v soc/_34210_/A2 (OAI21_X1_7T5P0) |
| 0.60 0.55 57.41 ^ soc/_34210_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14310_ (net) |
| 0.60 0.00 57.41 ^ soc/_34211_/I (CLKBUF_X1_7T5P0) |
| 0.11 0.28 57.69 ^ soc/_34211_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02427_ (net) |
| 0.11 0.00 57.69 ^ soc/_44357_/D (DFFQ_X1_7T5P0) |
| 57.69 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 30.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 30.64 ^ soc/clkbuf_leaf_60_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 30.95 ^ soc/clkbuf_leaf_60_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_60_core_clk (net) |
| 0.13 0.00 30.95 ^ soc/_44357_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.70 clock uncertainty |
| 0.35 31.06 clock reconvergence pessimism |
| -0.21 30.85 library setup time |
| 30.85 data required time |
| ----------------------------------------------------------------------------- |
| 30.85 data required time |
| -57.69 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.84 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_44355_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_34178_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_34178_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_14288_ (net) |
| 1.54 0.00 56.86 v soc/_34204_/A2 (OAI21_X1_7T5P0) |
| 0.55 0.53 57.39 ^ soc/_34204_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_14306_ (net) |
| 0.55 0.00 57.39 ^ soc/_34205_/I (CLKBUF_X1_7T5P0) |
| 0.11 0.27 57.66 ^ soc/_34205_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_02425_ (net) |
| 0.11 0.00 57.66 ^ soc/_44355_/D (DFFQ_X1_7T5P0) |
| 57.66 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.33 29.94 ^ soc/clkbuf_4_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_2_0_core_clk (net) |
| 0.19 0.00 29.94 ^ soc/clkbuf_5_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.26 30.20 ^ soc/clkbuf_5_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 2 0.04 soc/clknet_5_4_0_core_clk (net) |
| 0.14 0.00 30.20 ^ soc/clkbuf_6_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.44 0.43 30.64 ^ soc/clkbuf_6_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 8 0.20 soc/clknet_6_9_0_core_clk (net) |
| 0.44 0.01 30.64 ^ soc/clkbuf_leaf_60_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.31 30.95 ^ soc/clkbuf_leaf_60_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.07 soc/clknet_leaf_60_core_clk (net) |
| 0.13 0.00 30.95 ^ soc/_44355_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.70 clock uncertainty |
| 0.35 31.06 clock reconvergence pessimism |
| -0.21 30.85 library setup time |
| 30.85 data required time |
| ----------------------------------------------------------------------------- |
| 30.85 data required time |
| -57.66 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.82 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42557_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_26789_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_26789_/Z (CLKBUF_X2_7T5P0) |
| 16 0.19 soc/_08582_ (net) |
| 1.55 0.02 56.88 v soc/_26871_/A2 (NAND2_X1_7T5P0) |
| 0.51 0.57 57.45 ^ soc/_26871_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_08648_ (net) |
| 0.51 0.00 57.45 ^ soc/_26874_/A1 (NAND2_X1_7T5P0) |
| 0.27 0.18 57.63 v soc/_26874_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_00750_ (net) |
| 0.27 0.00 57.63 v soc/_42557_/D (DFFQ_X1_7T5P0) |
| 57.63 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_14_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.52 0.49 30.80 ^ soc/clkbuf_6_14_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 12 0.24 soc/clknet_6_14_0_core_clk (net) |
| 0.52 0.00 30.80 ^ soc/clkbuf_leaf_80_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.32 31.12 ^ soc/clkbuf_leaf_80_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.06 soc/clknet_leaf_80_core_clk (net) |
| 0.13 0.00 31.12 ^ soc/_42557_/CLK (DFFQ_X1_7T5P0) |
| -0.25 30.87 clock uncertainty |
| 0.35 31.22 clock reconvergence pessimism |
| -0.27 30.95 library setup time |
| 30.95 data required time |
| ----------------------------------------------------------------------------- |
| 30.95 data required time |
| -57.63 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.68 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42552_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_26789_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_26789_/Z (CLKBUF_X2_7T5P0) |
| 16 0.19 soc/_08582_ (net) |
| 1.55 0.02 56.88 v soc/_26848_/A2 (NAND2_X1_7T5P0) |
| 0.53 0.60 57.48 ^ soc/_26848_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_08630_ (net) |
| 0.53 0.00 57.48 ^ soc/_26851_/A1 (NAND2_X1_7T5P0) |
| 0.22 0.16 57.64 v soc/_26851_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_00745_ (net) |
| 0.22 0.00 57.64 v soc/_42552_/D (DFFQ_X1_7T5P0) |
| 57.64 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.57 30.88 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.01 30.89 ^ soc/clkbuf_leaf_81_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.39 31.28 ^ soc/clkbuf_leaf_81_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.14 soc/clknet_leaf_81_core_clk (net) |
| 0.20 0.00 31.28 ^ soc/_42552_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.03 clock uncertainty |
| 0.35 31.39 clock reconvergence pessimism |
| -0.24 31.14 library setup time |
| 31.14 data required time |
| ----------------------------------------------------------------------------- |
| 31.14 data required time |
| -57.64 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.50 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42551_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_26789_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_26789_/Z (CLKBUF_X2_7T5P0) |
| 16 0.19 soc/_08582_ (net) |
| 1.55 0.02 56.88 v soc/_26844_/A2 (NAND2_X1_7T5P0) |
| 0.46 0.53 57.41 ^ soc/_26844_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_08627_ (net) |
| 0.46 0.00 57.41 ^ soc/_26847_/A1 (NAND2_X1_7T5P0) |
| 0.44 0.13 57.54 v soc/_26847_/ZN (NAND2_X1_7T5P0) |
| 1 0.00 soc/_00744_ (net) |
| 0.44 0.00 57.54 v soc/_42551_/D (DFFQ_X1_7T5P0) |
| 57.54 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.57 30.88 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.01 30.89 ^ soc/clkbuf_leaf_81_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.39 31.28 ^ soc/clkbuf_leaf_81_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.14 soc/clknet_leaf_81_core_clk (net) |
| 0.20 0.00 31.28 ^ soc/_42551_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.03 clock uncertainty |
| 0.35 31.38 clock reconvergence pessimism |
| -0.32 31.07 library setup time |
| 31.07 data required time |
| ----------------------------------------------------------------------------- |
| 31.07 data required time |
| -57.54 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.48 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42545_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_26789_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_26789_/Z (CLKBUF_X2_7T5P0) |
| 16 0.19 soc/_08582_ (net) |
| 1.55 0.02 56.88 v soc/_26816_/A2 (NAND2_X1_7T5P0) |
| 0.51 0.58 57.46 ^ soc/_26816_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_08605_ (net) |
| 0.51 0.00 57.46 ^ soc/_26820_/A1 (NAND2_X1_7T5P0) |
| 0.23 0.13 57.59 v soc/_26820_/ZN (NAND2_X1_7T5P0) |
| 1 0.00 soc/_00738_ (net) |
| 0.23 0.00 57.59 v soc/_42545_/D (DFFQ_X1_7T5P0) |
| 57.59 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.57 30.88 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.02 30.90 ^ soc/clkbuf_leaf_86_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.36 31.26 ^ soc/clkbuf_leaf_86_core_clk/Z (CLKBUF_X16_7T5P0) |
| 20 0.09 soc/clknet_leaf_86_core_clk (net) |
| 0.16 0.00 31.26 ^ soc/_42545_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.01 clock uncertainty |
| 0.35 31.36 clock reconvergence pessimism |
| -0.25 31.11 library setup time |
| 31.11 data required time |
| ----------------------------------------------------------------------------- |
| 31.11 data required time |
| -57.59 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.47 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_46295_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_23442_/A2 (AOI21_X1_7T5P0) |
| 2.84 1.82 43.31 ^ soc/_23442_/ZN (AOI21_X1_7T5P0) |
| 8 0.09 soc/_06016_ (net) |
| 2.84 0.01 43.31 ^ soc/_23461_/I (BUF_X1_7T5P0) |
| 7.13 4.46 47.78 ^ soc/_23461_/Z (BUF_X1_7T5P0) |
| 16 0.45 soc/_06035_ (net) |
| 7.14 0.12 47.90 ^ soc/_23515_/I (CLKBUF_X2_7T5P0) |
| 1.55 1.58 49.48 ^ soc/_23515_/Z (CLKBUF_X2_7T5P0) |
| 16 0.18 soc/_06088_ (net) |
| 1.55 0.00 49.49 ^ soc/_23681_/S1 (MUX4_X1_7T5P0) |
| 0.35 0.52 50.01 v soc/_23681_/Z (MUX4_X1_7T5P0) |
| 1 0.00 soc/_06247_ (net) |
| 0.35 0.00 50.01 v soc/_23682_/A2 (NOR2_X1_7T5P0) |
| 10.10 6.12 56.13 ^ soc/_23682_/ZN (NOR2_X1_7T5P0) |
| 2 0.34 soc/_06248_ (net) |
| 10.10 0.10 56.23 ^ soc/_23689_/B1 (OAI32_X1_7T5P0) |
| 2.35 0.31 56.54 v soc/_23689_/ZN (OAI32_X1_7T5P0) |
| 1 0.02 soc/_06255_ (net) |
| 2.35 0.00 56.54 v soc/_23691_/I1 (MUX2_X2_7T5P0) |
| 0.41 1.11 57.64 v soc/_23691_/Z (MUX2_X2_7T5P0) |
| 2 0.06 soc/_06257_ (net) |
| 0.41 0.00 57.65 v soc/_23692_/I (CLKBUF_X1_7T5P0) |
| 0.11 0.27 57.91 v soc/_23692_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_00030_ (net) |
| 0.11 0.00 57.91 v soc/_46295_/D (DFFQ_X1_7T5P0) |
| 57.91 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.35 29.02 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 29.02 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.34 29.36 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.01 29.37 ^ soc/clkbuf_3_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.27 29.64 ^ soc/clkbuf_3_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_7_0_core_clk (net) |
| 0.12 0.00 29.64 ^ soc/clkbuf_3_7_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.33 29.97 ^ soc/clkbuf_3_7_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_3_7_1_core_clk (net) |
| 0.28 0.01 29.98 ^ soc/clkbuf_4_14_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.32 30.30 ^ soc/clkbuf_4_14_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_14_0_core_clk (net) |
| 0.19 0.00 30.30 ^ soc/clkbuf_5_28_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.24 0.32 30.62 ^ soc/clkbuf_5_28_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_28_0_core_clk (net) |
| 0.24 0.00 30.63 ^ soc/clkbuf_6_57_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.70 0.59 31.22 ^ soc/clkbuf_6_57_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.33 soc/clknet_6_57_0_core_clk (net) |
| 0.70 0.01 31.22 ^ soc/clkbuf_leaf_393_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.18 0.37 31.60 ^ soc/clkbuf_leaf_393_core_clk/Z (CLKBUF_X16_7T5P0) |
| 16 0.11 soc/clknet_leaf_393_core_clk (net) |
| 0.18 0.00 31.60 ^ soc/_46295_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.35 clock uncertainty |
| 0.31 31.66 clock reconvergence pessimism |
| -0.21 31.44 library setup time |
| 31.44 data required time |
| ----------------------------------------------------------------------------- |
| 31.44 data required time |
| -57.91 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.47 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42541_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_26789_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_26789_/Z (CLKBUF_X2_7T5P0) |
| 16 0.19 soc/_08582_ (net) |
| 1.55 0.02 56.88 v soc/_26790_/A2 (NAND2_X1_7T5P0) |
| 0.48 0.55 57.43 ^ soc/_26790_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_08583_ (net) |
| 0.48 0.00 57.43 ^ soc/_26793_/A1 (NAND2_X1_7T5P0) |
| 0.26 0.15 57.58 v soc/_26793_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_00734_ (net) |
| 0.26 0.00 57.58 v soc/_42541_/D (DFFQ_X1_7T5P0) |
| 57.58 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.57 30.88 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.01 30.89 ^ soc/clkbuf_leaf_81_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.39 31.28 ^ soc/clkbuf_leaf_81_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.14 soc/clknet_leaf_81_core_clk (net) |
| 0.20 0.00 31.28 ^ soc/_42541_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.03 clock uncertainty |
| 0.35 31.38 clock reconvergence pessimism |
| -0.25 31.13 library setup time |
| 31.13 data required time |
| ----------------------------------------------------------------------------- |
| 31.13 data required time |
| -57.58 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.45 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42549_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_26789_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_26789_/Z (CLKBUF_X2_7T5P0) |
| 16 0.19 soc/_08582_ (net) |
| 1.55 0.02 56.88 v soc/_26835_/A2 (NAND2_X1_7T5P0) |
| 0.45 0.52 57.40 ^ soc/_26835_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_08620_ (net) |
| 0.45 0.00 57.40 ^ soc/_26838_/A1 (NAND2_X1_7T5P0) |
| 0.32 0.13 57.54 v soc/_26838_/ZN (NAND2_X1_7T5P0) |
| 1 0.00 soc/_00742_ (net) |
| 0.32 0.00 57.54 v soc/_42549_/D (DFFQ_X1_7T5P0) |
| 57.54 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.57 30.88 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.01 30.89 ^ soc/clkbuf_leaf_81_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.39 31.28 ^ soc/clkbuf_leaf_81_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.14 soc/clknet_leaf_81_core_clk (net) |
| 0.20 0.00 31.28 ^ soc/_42549_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.03 clock uncertainty |
| 0.35 31.39 clock reconvergence pessimism |
| -0.27 31.11 library setup time |
| 31.11 data required time |
| ----------------------------------------------------------------------------- |
| 31.11 data required time |
| -57.54 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.43 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42553_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_26789_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_26789_/Z (CLKBUF_X2_7T5P0) |
| 16 0.19 soc/_08582_ (net) |
| 1.55 0.02 56.88 v soc/_26852_/A2 (NAND2_X1_7T5P0) |
| 0.46 0.53 57.40 ^ soc/_26852_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_08633_ (net) |
| 0.46 0.00 57.40 ^ soc/_26855_/A1 (NAND2_X1_7T5P0) |
| 0.24 0.16 57.56 v soc/_26855_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_00746_ (net) |
| 0.24 0.00 57.56 v soc/_42553_/D (DFFQ_X1_7T5P0) |
| 57.56 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.57 30.88 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.01 30.89 ^ soc/clkbuf_leaf_81_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.39 31.28 ^ soc/clkbuf_leaf_81_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.14 soc/clknet_leaf_81_core_clk (net) |
| 0.20 0.00 31.28 ^ soc/_42553_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.03 clock uncertainty |
| 0.35 31.38 clock reconvergence pessimism |
| -0.25 31.14 library setup time |
| 31.14 data required time |
| ----------------------------------------------------------------------------- |
| 31.14 data required time |
| -57.56 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.42 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42547_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.53 0.01 54.94 v soc/_26789_/I (CLKBUF_X2_7T5P0) |
| 1.54 1.92 56.86 v soc/_26789_/Z (CLKBUF_X2_7T5P0) |
| 16 0.19 soc/_08582_ (net) |
| 1.55 0.02 56.88 v soc/_26826_/A2 (NAND2_X1_7T5P0) |
| 0.47 0.54 57.42 ^ soc/_26826_/ZN (NAND2_X1_7T5P0) |
| 1 0.01 soc/_08613_ (net) |
| 0.47 0.00 57.42 ^ soc/_26829_/A1 (NAND2_X1_7T5P0) |
| 0.24 0.12 57.54 v soc/_26829_/ZN (NAND2_X1_7T5P0) |
| 1 0.00 soc/_00740_ (net) |
| 0.24 0.00 57.54 v soc/_42547_/D (DFFQ_X1_7T5P0) |
| 57.54 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.57 30.88 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.01 30.89 ^ soc/clkbuf_leaf_81_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.39 31.28 ^ soc/clkbuf_leaf_81_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.14 soc/clknet_leaf_81_core_clk (net) |
| 0.20 0.01 31.28 ^ soc/_42547_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.03 clock uncertainty |
| 0.35 31.39 clock reconvergence pessimism |
| -0.25 31.14 library setup time |
| 31.14 data required time |
| ----------------------------------------------------------------------------- |
| 31.14 data required time |
| -57.54 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.40 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42371_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21346_/A2 (AOI21_X1_7T5P0) |
| 2.54 1.66 43.15 ^ soc/_21346_/ZN (AOI21_X1_7T5P0) |
| 8 0.08 soc/_20558_ (net) |
| 2.54 0.01 43.16 ^ soc/_21375_/I (BUF_X1_7T5P0) |
| 7.53 4.72 47.88 ^ soc/_21375_/Z (BUF_X1_7T5P0) |
| 16 0.47 soc/_20587_ (net) |
| 7.53 0.11 47.98 ^ soc/_21427_/I (CLKBUF_X2_7T5P0) |
| 1.75 1.72 49.70 ^ soc/_21427_/Z (CLKBUF_X2_7T5P0) |
| 16 0.20 soc/_20638_ (net) |
| 1.75 0.03 49.73 ^ soc/_21586_/S1 (MUX4_X1_7T5P0) |
| 0.43 0.59 50.32 v soc/_21586_/Z (MUX4_X1_7T5P0) |
| 1 0.01 soc/_20790_ (net) |
| 0.43 0.00 50.32 v soc/_21587_/A2 (NOR2_X1_7T5P0) |
| 9.00 5.47 55.80 ^ soc/_21587_/ZN (NOR2_X1_7T5P0) |
| 2 0.31 soc/_20791_ (net) |
| 9.00 0.08 55.87 ^ soc/_21594_/B1 (OAI32_X1_7T5P0) |
| 2.34 0.57 56.44 v soc/_21594_/ZN (OAI32_X1_7T5P0) |
| 1 0.03 soc/_20798_ (net) |
| 2.34 0.00 56.44 v soc/_21596_/I1 (MUX2_X2_7T5P0) |
| 0.40 1.09 57.54 v soc/_21596_/Z (MUX2_X2_7T5P0) |
| 2 0.05 soc/_20800_ (net) |
| 0.40 0.00 57.54 v soc/_21597_/I (CLKBUF_X1_7T5P0) |
| 0.11 0.26 57.80 v soc/_21597_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_00062_ (net) |
| 0.11 0.00 57.80 v soc/_42371_/D (DFFQ_X1_7T5P0) |
| 57.80 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.35 29.02 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 29.02 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.34 29.36 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.01 29.37 ^ soc/clkbuf_3_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.27 29.64 ^ soc/clkbuf_3_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_7_0_core_clk (net) |
| 0.12 0.00 29.64 ^ soc/clkbuf_3_7_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.33 29.97 ^ soc/clkbuf_3_7_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_3_7_1_core_clk (net) |
| 0.28 0.01 29.98 ^ soc/clkbuf_4_14_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.32 30.30 ^ soc/clkbuf_4_14_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_14_0_core_clk (net) |
| 0.19 0.00 30.30 ^ soc/clkbuf_5_28_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.24 0.32 30.62 ^ soc/clkbuf_5_28_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_28_0_core_clk (net) |
| 0.24 0.00 30.63 ^ soc/clkbuf_6_56_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.76 0.63 31.25 ^ soc/clkbuf_6_56_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.36 soc/clknet_6_56_0_core_clk (net) |
| 0.76 0.01 31.26 ^ soc/clkbuf_leaf_396_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.14 0.35 31.61 ^ soc/clkbuf_leaf_396_core_clk/Z (CLKBUF_X16_7T5P0) |
| 10 0.06 soc/clknet_leaf_396_core_clk (net) |
| 0.14 0.00 31.61 ^ soc/_42371_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.36 clock uncertainty |
| 0.31 31.67 clock reconvergence pessimism |
| -0.22 31.45 library setup time |
| 31.45 data required time |
| ----------------------------------------------------------------------------- |
| 31.45 data required time |
| -57.80 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.35 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43017_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28863_/I (CLKBUF_X2_7T5P0) |
| 0.91 1.49 56.59 v soc/_28863_/Z (CLKBUF_X2_7T5P0) |
| 16 0.10 soc/_10184_ (net) |
| 0.91 0.00 56.59 v soc/_28918_/A2 (AOI21_X1_7T5P0) |
| 0.57 0.52 57.11 ^ soc/_28918_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10235_ (net) |
| 0.57 0.00 57.11 ^ soc/_28919_/I (CLKINV_X1_7T5P0) |
| 0.25 0.21 57.32 v soc/_28919_/ZN (CLKINV_X1_7T5P0) |
| 1 0.01 soc/_01210_ (net) |
| 0.25 0.00 57.32 v soc/_43017_/D (DFFQ_X1_7T5P0) |
| 57.32 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 29.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 29.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 29.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 29.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 30.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 30.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 30.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 30.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 30.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 30.95 ^ soc/clkbuf_leaf_419_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.34 31.29 ^ soc/clkbuf_leaf_419_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.10 soc/clknet_leaf_419_core_clk (net) |
| 0.17 0.00 31.30 ^ soc/_43017_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.05 clock uncertainty |
| 0.31 31.35 clock reconvergence pessimism |
| -0.26 31.10 library setup time |
| 31.10 data required time |
| ----------------------------------------------------------------------------- |
| 31.10 data required time |
| -57.32 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.23 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43019_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28863_/I (CLKBUF_X2_7T5P0) |
| 0.91 1.49 56.59 v soc/_28863_/Z (CLKBUF_X2_7T5P0) |
| 16 0.10 soc/_10184_ (net) |
| 0.91 0.00 56.59 v soc/_28953_/A2 (AOI21_X1_7T5P0) |
| 0.61 0.57 57.16 ^ soc/_28953_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10268_ (net) |
| 0.61 0.00 57.16 ^ soc/_28954_/I (CLKINV_X1_7T5P0) |
| 0.20 0.15 57.31 v soc/_28954_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01212_ (net) |
| 0.20 0.00 57.31 v soc/_43019_/D (DFFQ_X1_7T5P0) |
| 57.31 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 29.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 29.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 29.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 29.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 30.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 30.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 30.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 30.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 30.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 30.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 31.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 31.29 ^ soc/_43019_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.04 clock uncertainty |
| 0.31 31.35 clock reconvergence pessimism |
| -0.24 31.10 library setup time |
| 31.10 data required time |
| ----------------------------------------------------------------------------- |
| 31.10 data required time |
| -57.31 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.21 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43020_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28863_/I (CLKBUF_X2_7T5P0) |
| 0.91 1.49 56.59 v soc/_28863_/Z (CLKBUF_X2_7T5P0) |
| 16 0.10 soc/_10184_ (net) |
| 0.91 0.00 56.59 v soc/_28965_/A2 (AOI21_X1_7T5P0) |
| 0.58 0.51 57.10 ^ soc/_28965_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10279_ (net) |
| 0.58 0.00 57.10 ^ soc/_28966_/I (CLKINV_X1_7T5P0) |
| 0.21 0.17 57.27 v soc/_28966_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01213_ (net) |
| 0.21 0.00 57.27 v soc/_43020_/D (DFFQ_X1_7T5P0) |
| 57.27 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 29.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 29.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 29.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 29.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 30.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 30.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 30.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 30.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 30.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 30.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 31.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 31.29 ^ soc/_43020_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.04 clock uncertainty |
| 0.31 31.35 clock reconvergence pessimism |
| -0.25 31.10 library setup time |
| 31.10 data required time |
| ----------------------------------------------------------------------------- |
| 31.10 data required time |
| -57.27 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.17 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43024_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28967_/I (CLKBUF_X2_7T5P0) |
| 0.84 1.45 56.54 v soc/_28967_/Z (CLKBUF_X2_7T5P0) |
| 16 0.09 soc/_10280_ (net) |
| 0.84 0.01 56.54 v soc/_29011_/A2 (AOI21_X1_7T5P0) |
| 0.66 0.56 57.10 ^ soc/_29011_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10321_ (net) |
| 0.66 0.00 57.10 ^ soc/_29012_/I (CLKINV_X1_7T5P0) |
| 0.21 0.16 57.26 v soc/_29012_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01217_ (net) |
| 0.21 0.00 57.26 v soc/_43024_/D (DFFQ_X1_7T5P0) |
| 57.26 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 29.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 29.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 29.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 29.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 30.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 30.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 30.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 30.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 30.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 30.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 31.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 31.29 ^ soc/_43024_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.04 clock uncertainty |
| 0.31 31.35 clock reconvergence pessimism |
| -0.25 31.10 library setup time |
| 31.10 data required time |
| ----------------------------------------------------------------------------- |
| 31.10 data required time |
| -57.26 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.16 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43022_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28967_/I (CLKBUF_X2_7T5P0) |
| 0.84 1.45 56.54 v soc/_28967_/Z (CLKBUF_X2_7T5P0) |
| 16 0.09 soc/_10280_ (net) |
| 0.84 0.00 56.54 v soc/_28988_/A2 (AOI21_X1_7T5P0) |
| 0.63 0.50 57.04 ^ soc/_28988_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10300_ (net) |
| 0.63 0.00 57.04 ^ soc/_28989_/I (CLKINV_X1_7T5P0) |
| 0.20 0.15 57.20 v soc/_28989_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01215_ (net) |
| 0.20 0.00 57.20 v soc/_43022_/D (DFFQ_X1_7T5P0) |
| 57.20 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 29.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 29.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 29.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 29.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 30.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 30.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 30.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 30.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 30.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 30.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 31.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 31.29 ^ soc/_43022_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.04 clock uncertainty |
| 0.31 31.35 clock reconvergence pessimism |
| -0.25 31.10 library setup time |
| 31.10 data required time |
| ----------------------------------------------------------------------------- |
| 31.10 data required time |
| -57.20 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.09 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43026_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28967_/I (CLKBUF_X2_7T5P0) |
| 0.84 1.45 56.54 v soc/_28967_/Z (CLKBUF_X2_7T5P0) |
| 16 0.09 soc/_10280_ (net) |
| 0.84 0.00 56.54 v soc/_29044_/A2 (AOI21_X1_7T5P0) |
| 0.59 0.49 57.04 ^ soc/_29044_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10352_ (net) |
| 0.59 0.00 57.04 ^ soc/_29045_/I (CLKINV_X1_7T5P0) |
| 0.19 0.14 57.17 v soc/_29045_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01219_ (net) |
| 0.19 0.00 57.17 v soc/_43026_/D (DFFQ_X1_7T5P0) |
| 57.17 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 29.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 29.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 29.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 29.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 30.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 30.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 30.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 30.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 30.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 30.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 31.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 31.29 ^ soc/_43026_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.04 clock uncertainty |
| 0.31 31.35 clock reconvergence pessimism |
| -0.24 31.11 library setup time |
| 31.11 data required time |
| ----------------------------------------------------------------------------- |
| 31.11 data required time |
| -57.17 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.07 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43021_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28967_/I (CLKBUF_X2_7T5P0) |
| 0.84 1.45 56.54 v soc/_28967_/Z (CLKBUF_X2_7T5P0) |
| 16 0.09 soc/_10280_ (net) |
| 0.84 0.00 56.54 v soc/_28977_/A2 (AOI21_X1_7T5P0) |
| 0.53 0.47 57.01 ^ soc/_28977_/ZN (AOI21_X1_7T5P0) |
| 1 0.00 soc/_10290_ (net) |
| 0.53 0.00 57.01 ^ soc/_28978_/I (CLKINV_X1_7T5P0) |
| 0.19 0.15 57.16 v soc/_28978_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01214_ (net) |
| 0.19 0.00 57.16 v soc/_43021_/D (DFFQ_X1_7T5P0) |
| 57.16 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.01 29.37 ^ soc/clkbuf_3_5_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.63 ^ soc/clkbuf_3_5_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_5_0_core_clk (net) |
| 0.12 0.00 29.63 ^ soc/clkbuf_3_5_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.28 29.91 ^ soc/clkbuf_3_5_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_3_5_1_core_clk (net) |
| 0.19 0.00 29.92 ^ soc/clkbuf_4_11_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.15 0.27 30.19 ^ soc/clkbuf_4_11_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.04 soc/clknet_4_11_0_core_clk (net) |
| 0.15 0.00 30.19 ^ soc/clkbuf_5_23_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.18 0.28 30.47 ^ soc/clkbuf_5_23_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.06 soc/clknet_5_23_0_core_clk (net) |
| 0.18 0.00 30.47 ^ soc/clkbuf_6_47_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.50 0.47 30.94 ^ soc/clkbuf_6_47_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.23 soc/clknet_6_47_0_core_clk (net) |
| 0.50 0.01 30.95 ^ soc/clkbuf_leaf_412_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.16 0.33 31.29 ^ soc/clkbuf_leaf_412_core_clk/Z (CLKBUF_X16_7T5P0) |
| 28 0.09 soc/clknet_leaf_412_core_clk (net) |
| 0.16 0.00 31.29 ^ soc/_43021_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.04 clock uncertainty |
| 0.31 31.35 clock reconvergence pessimism |
| -0.24 31.11 library setup time |
| 31.11 data required time |
| ----------------------------------------------------------------------------- |
| 31.11 data required time |
| -57.16 data arrival time |
| ----------------------------------------------------------------------------- |
| -26.05 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_46293_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_23442_/A2 (AOI21_X1_7T5P0) |
| 2.84 1.82 43.31 ^ soc/_23442_/ZN (AOI21_X1_7T5P0) |
| 8 0.09 soc/_06016_ (net) |
| 2.84 0.01 43.31 ^ soc/_23453_/I (BUF_X1_7T5P0) |
| 9.15 5.68 49.00 ^ soc/_23453_/Z (BUF_X1_7T5P0) |
| 16 0.57 soc/_06027_ (net) |
| 9.15 0.15 49.15 ^ soc/_23484_/I (CLKBUF_X2_7T5P0) |
| 1.55 1.66 50.80 ^ soc/_23484_/Z (CLKBUF_X2_7T5P0) |
| 16 0.17 soc/_06058_ (net) |
| 1.55 0.00 50.81 ^ soc/_23620_/S1 (MUX4_X1_7T5P0) |
| 0.39 0.50 51.30 ^ soc/_23620_/Z (MUX4_X1_7T5P0) |
| 1 0.01 soc/_06188_ (net) |
| 0.39 0.00 51.30 ^ soc/_23621_/A2 (NOR2_X1_7T5P0) |
| 0.48 0.40 51.70 v soc/_23621_/ZN (NOR2_X1_7T5P0) |
| 1 0.03 soc/_06189_ (net) |
| 0.48 0.00 51.70 v soc/_23626_/A3 (OAI32_X1_7T5P0) |
| 9.24 5.64 57.34 ^ soc/_23626_/ZN (OAI32_X1_7T5P0) |
| 2 0.20 soc/_06194_ (net) |
| 9.24 0.03 57.37 ^ soc/_23627_/I1 (MUX2_X2_7T5P0) |
| 0.28 0.00 57.36 ^ soc/_23627_/Z (MUX2_X2_7T5P0) |
| 1 0.01 soc/_06195_ (net) |
| 0.28 0.00 57.36 ^ soc/_23628_/I (CLKBUF_X1_7T5P0) |
| 0.13 0.25 57.61 ^ soc/_23628_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_00028_ (net) |
| 0.13 0.00 57.61 ^ soc/_46293_/D (DFFQ_X1_7T5P0) |
| 57.61 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.35 29.02 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 29.02 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.34 29.36 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.01 29.37 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.26 29.63 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 29.64 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.35 29.98 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 29.99 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 30.36 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.01 30.36 ^ soc/clkbuf_5_25_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.33 30.69 ^ soc/clkbuf_5_25_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_25_0_core_clk (net) |
| 0.23 0.00 30.70 ^ soc/clkbuf_6_51_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.65 31.35 ^ soc/clkbuf_6_51_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.39 soc/clknet_6_51_0_core_clk (net) |
| 0.81 0.01 31.36 ^ soc/clkbuf_leaf_295_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.25 0.43 31.78 ^ soc/clkbuf_leaf_295_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.19 soc/clknet_leaf_295_core_clk (net) |
| 0.25 0.02 31.80 ^ soc/_46293_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.55 clock uncertainty |
| 0.31 31.86 clock reconvergence pessimism |
| -0.19 31.67 library setup time |
| 31.67 data required time |
| ----------------------------------------------------------------------------- |
| 31.67 data required time |
| -57.61 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.94 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43085_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43005_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.42 6.65 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 6.66 ^ soc/clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.65 7.31 ^ soc/clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.32 soc/clknet_6_32_0_core_clk (net) |
| 0.68 0.02 7.33 ^ soc/clkbuf_leaf_441_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.37 7.70 ^ soc/clkbuf_leaf_441_core_clk/Z (CLKBUF_X16_7T5P0) |
| 8 0.05 soc/clknet_leaf_441_core_clk (net) |
| 0.13 0.00 7.70 ^ soc/_43085_/CLK (DFFQ_X1_7T5P0) |
| 4.96 3.82 11.52 v soc/_43085_/Q (DFFQ_X1_7T5P0) |
| 10 0.52 soc/core.VexRiscv.CsrPlugin_exceptionPendings_3 (net) |
| 4.96 0.02 11.53 v soc/_22139_/A4 (NOR4_X1_7T5P0) |
| 1.62 1.12 12.65 ^ soc/_22139_/ZN (NOR4_X1_7T5P0) |
| 1 0.01 soc/_04815_ (net) |
| 1.62 0.00 12.65 ^ soc/_22140_/A4 (AND4_X1_7T5P0) |
| 3.90 2.84 15.49 ^ soc/_22140_/Z (AND4_X1_7T5P0) |
| 10 0.24 soc/_04816_ (net) |
| 3.90 0.04 15.53 ^ soc/_22172_/A2 (OR2_X1_7T5P0) |
| 6.86 4.24 19.77 ^ soc/_22172_/Z (OR2_X1_7T5P0) |
| 12 0.43 soc/_04846_ (net) |
| 6.86 0.01 19.78 ^ soc/_26755_/A2 (NOR2_X2_7T5P0) |
| 2.89 1.95 21.73 v soc/_26755_/ZN (NOR2_X2_7T5P0) |
| 14 0.20 soc/_08550_ (net) |
| 2.89 0.00 21.73 v soc/_26756_/A2 (NAND2_X1_7T5P0) |
| 8.32 5.85 27.57 ^ soc/_26756_/ZN (NAND2_X1_7T5P0) |
| 6 0.48 soc/_08551_ (net) |
| 8.32 0.10 27.67 ^ soc/_26763_/A1 (NOR2_X1_7T5P0) |
| 4.06 2.98 30.65 v soc/_26763_/ZN (NOR2_X1_7T5P0) |
| 4 0.16 soc/_08558_ (net) |
| 4.06 0.02 30.66 v soc/_26773_/A1 (NOR3_X1_7T5P0) |
| 17.39 11.14 41.80 ^ soc/_26773_/ZN (NOR3_X1_7T5P0) |
| 6 0.41 soc/_08568_ (net) |
| 17.39 0.07 41.87 ^ soc/_26774_/I (BUF_X1_7T5P0) |
| 10.30 5.99 47.85 ^ soc/_26774_/Z (BUF_X1_7T5P0) |
| 16 0.70 soc/_08569_ (net) |
| 10.30 0.01 47.86 ^ soc/_26881_/I (BUF_X1_7T5P0) |
| 10.14 6.08 53.95 ^ soc/_26881_/Z (BUF_X1_7T5P0) |
| 16 0.66 soc/_08656_ (net) |
| 10.15 0.14 54.08 ^ soc/_28767_/B (AOI21_X1_7T5P0) |
| 2.53 0.78 54.86 v soc/_28767_/ZN (AOI21_X1_7T5P0) |
| 1 0.02 soc/_10096_ (net) |
| 2.53 0.00 54.86 v soc/_28768_/B2 (AOI221_X1_7T5P0) |
| 3.17 2.38 57.25 ^ soc/_28768_/ZN (AOI221_X1_7T5P0) |
| 2 0.06 soc/_10097_ (net) |
| 3.17 0.00 57.25 ^ soc/_28769_/B (AOI21_X1_7T5P0) |
| 0.90 0.37 57.62 v soc/_28769_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10098_ (net) |
| 0.90 0.00 57.62 v soc/_28770_/I (CLKINV_X1_7T5P0) |
| 0.31 0.29 57.91 ^ soc/_28770_/ZN (CLKINV_X1_7T5P0) |
| 1 0.01 soc/_01198_ (net) |
| 0.31 0.00 57.91 ^ soc/_43005_/D (DFFQ_X1_7T5P0) |
| 57.91 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.68 31.67 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.02 31.68 ^ soc/clkbuf_leaf_435_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.41 32.09 ^ soc/clkbuf_leaf_435_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.13 soc/clknet_leaf_435_core_clk (net) |
| 0.20 0.00 32.09 ^ soc/_43005_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.84 clock uncertainty |
| 0.59 32.43 clock reconvergence pessimism |
| -0.22 32.21 library setup time |
| 32.21 data required time |
| ----------------------------------------------------------------------------- |
| 32.21 data required time |
| -57.91 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.70 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_46292_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_23442_/A2 (AOI21_X1_7T5P0) |
| 2.84 1.82 43.31 ^ soc/_23442_/ZN (AOI21_X1_7T5P0) |
| 8 0.09 soc/_06016_ (net) |
| 2.84 0.01 43.31 ^ soc/_23453_/I (BUF_X1_7T5P0) |
| 9.15 5.68 49.00 ^ soc/_23453_/Z (BUF_X1_7T5P0) |
| 16 0.57 soc/_06027_ (net) |
| 9.15 0.15 49.15 ^ soc/_23484_/I (CLKBUF_X2_7T5P0) |
| 1.55 1.66 50.80 ^ soc/_23484_/Z (CLKBUF_X2_7T5P0) |
| 16 0.17 soc/_06058_ (net) |
| 1.55 0.00 50.81 ^ soc/_23600_/S1 (MUX4_X1_7T5P0) |
| 0.44 0.53 51.34 ^ soc/_23600_/Z (MUX4_X1_7T5P0) |
| 1 0.01 soc/_06169_ (net) |
| 0.44 0.00 51.34 ^ soc/_23601_/A2 (NOR2_X1_7T5P0) |
| 0.42 0.36 51.70 v soc/_23601_/ZN (NOR2_X1_7T5P0) |
| 1 0.02 soc/_06170_ (net) |
| 0.42 0.00 51.70 v soc/_23606_/A3 (OAI32_X1_7T5P0) |
| 8.79 5.36 57.06 ^ soc/_23606_/ZN (OAI32_X1_7T5P0) |
| 2 0.19 soc/_06175_ (net) |
| 8.79 0.03 57.09 ^ soc/_23607_/I1 (MUX2_X2_7T5P0) |
| 0.26 0.00 57.10 ^ soc/_23607_/Z (MUX2_X2_7T5P0) |
| 1 0.01 soc/_06176_ (net) |
| 0.26 0.00 57.10 ^ soc/_23608_/I (CLKBUF_X1_7T5P0) |
| 0.12 0.24 57.33 ^ soc/_23608_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_00027_ (net) |
| 0.12 0.00 57.33 ^ soc/_46292_/D (DFFQ_X1_7T5P0) |
| 57.33 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.13 0.35 29.02 ^ soc/clkbuf_2_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_3_0_core_clk (net) |
| 0.13 0.00 29.02 ^ soc/clkbuf_2_3_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.28 0.34 29.36 ^ soc/clkbuf_2_3_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.12 soc/clknet_2_3_1_core_clk (net) |
| 0.28 0.01 29.37 ^ soc/clkbuf_3_6_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.26 29.63 ^ soc/clkbuf_3_6_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_6_0_core_clk (net) |
| 0.11 0.00 29.64 ^ soc/clkbuf_3_6_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.31 0.35 29.98 ^ soc/clkbuf_3_6_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_6_1_core_clk (net) |
| 0.31 0.01 29.99 ^ soc/clkbuf_4_12_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 30.36 ^ soc/clkbuf_4_12_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_12_0_core_clk (net) |
| 0.26 0.01 30.36 ^ soc/clkbuf_5_25_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.33 30.69 ^ soc/clkbuf_5_25_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_25_0_core_clk (net) |
| 0.23 0.00 30.70 ^ soc/clkbuf_6_51_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.81 0.65 31.35 ^ soc/clkbuf_6_51_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 16 0.39 soc/clknet_6_51_0_core_clk (net) |
| 0.81 0.01 31.36 ^ soc/clkbuf_leaf_295_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.25 0.43 31.78 ^ soc/clkbuf_leaf_295_core_clk/Z (CLKBUF_X16_7T5P0) |
| 30 0.19 soc/clknet_leaf_295_core_clk (net) |
| 0.25 0.02 31.80 ^ soc/_46292_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.55 clock uncertainty |
| 0.31 31.86 clock reconvergence pessimism |
| -0.19 31.67 library setup time |
| 31.67 data required time |
| ----------------------------------------------------------------------------- |
| 31.67 data required time |
| -57.33 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.67 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_43085_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43007_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.75 3.98 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 4.06 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.40 4.46 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 4.46 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.36 4.82 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 4.82 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.28 5.10 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 5.10 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.59 5.70 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.06 5.76 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.47 6.23 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 6.23 ^ soc/clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.30 0.42 6.65 ^ soc/clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_5_16_0_core_clk (net) |
| 0.30 0.01 6.66 ^ soc/clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.65 7.31 ^ soc/clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.32 soc/clknet_6_32_0_core_clk (net) |
| 0.68 0.02 7.33 ^ soc/clkbuf_leaf_441_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.37 7.70 ^ soc/clkbuf_leaf_441_core_clk/Z (CLKBUF_X16_7T5P0) |
| 8 0.05 soc/clknet_leaf_441_core_clk (net) |
| 0.13 0.00 7.70 ^ soc/_43085_/CLK (DFFQ_X1_7T5P0) |
| 4.96 3.82 11.52 v soc/_43085_/Q (DFFQ_X1_7T5P0) |
| 10 0.52 soc/core.VexRiscv.CsrPlugin_exceptionPendings_3 (net) |
| 4.96 0.02 11.53 v soc/_22139_/A4 (NOR4_X1_7T5P0) |
| 1.62 1.12 12.65 ^ soc/_22139_/ZN (NOR4_X1_7T5P0) |
| 1 0.01 soc/_04815_ (net) |
| 1.62 0.00 12.65 ^ soc/_22140_/A4 (AND4_X1_7T5P0) |
| 3.90 2.84 15.49 ^ soc/_22140_/Z (AND4_X1_7T5P0) |
| 10 0.24 soc/_04816_ (net) |
| 3.90 0.04 15.53 ^ soc/_22172_/A2 (OR2_X1_7T5P0) |
| 6.86 4.24 19.77 ^ soc/_22172_/Z (OR2_X1_7T5P0) |
| 12 0.43 soc/_04846_ (net) |
| 6.86 0.01 19.78 ^ soc/_26755_/A2 (NOR2_X2_7T5P0) |
| 2.89 1.95 21.73 v soc/_26755_/ZN (NOR2_X2_7T5P0) |
| 14 0.20 soc/_08550_ (net) |
| 2.89 0.00 21.73 v soc/_26756_/A2 (NAND2_X1_7T5P0) |
| 8.32 5.85 27.57 ^ soc/_26756_/ZN (NAND2_X1_7T5P0) |
| 6 0.48 soc/_08551_ (net) |
| 8.32 0.10 27.67 ^ soc/_26763_/A1 (NOR2_X1_7T5P0) |
| 4.06 2.98 30.65 v soc/_26763_/ZN (NOR2_X1_7T5P0) |
| 4 0.16 soc/_08558_ (net) |
| 4.06 0.02 30.66 v soc/_26773_/A1 (NOR3_X1_7T5P0) |
| 17.39 11.14 41.80 ^ soc/_26773_/ZN (NOR3_X1_7T5P0) |
| 6 0.41 soc/_08568_ (net) |
| 17.39 0.07 41.87 ^ soc/_26774_/I (BUF_X1_7T5P0) |
| 10.30 5.99 47.85 ^ soc/_26774_/Z (BUF_X1_7T5P0) |
| 16 0.70 soc/_08569_ (net) |
| 10.30 0.01 47.86 ^ soc/_26881_/I (BUF_X1_7T5P0) |
| 10.14 6.08 53.95 ^ soc/_26881_/Z (BUF_X1_7T5P0) |
| 16 0.66 soc/_08656_ (net) |
| 10.15 0.14 54.08 ^ soc/_28789_/B (AOI21_X1_7T5P0) |
| 2.22 0.45 54.54 v soc/_28789_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10116_ (net) |
| 2.22 0.00 54.54 v soc/_28790_/B2 (AOI221_X1_7T5P0) |
| 3.75 2.66 57.20 ^ soc/_28790_/ZN (AOI221_X1_7T5P0) |
| 2 0.08 soc/_10117_ (net) |
| 3.75 0.00 57.20 ^ soc/_28791_/B (AOI21_X1_7T5P0) |
| 1.04 0.41 57.62 v soc/_28791_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10118_ (net) |
| 1.04 0.00 57.62 v soc/_28792_/I (CLKINV_X1_7T5P0) |
| 0.30 0.28 57.89 ^ soc/_28792_/ZN (CLKINV_X1_7T5P0) |
| 1 0.01 soc/_01200_ (net) |
| 0.30 0.00 57.89 ^ soc/_43007_/D (DFFQ_X1_7T5P0) |
| 57.89 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.53 31.51 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 31.52 ^ soc/clkbuf_opt_26_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.34 31.86 ^ soc/clkbuf_opt_26_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_26_0_core_clk (net) |
| 0.15 0.01 31.86 ^ soc/clkbuf_leaf_432_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.27 32.13 ^ soc/clkbuf_leaf_432_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.09 soc/clknet_leaf_432_core_clk (net) |
| 0.15 0.00 32.13 ^ soc/_43007_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.88 clock uncertainty |
| 0.59 32.47 clock reconvergence pessimism |
| -0.23 32.24 library setup time |
| 32.24 data required time |
| ----------------------------------------------------------------------------- |
| 32.24 data required time |
| -57.89 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.65 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_42542_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21336_/I (CLKBUF_X2_7T5P0) |
| 1.94 1.55 43.04 v soc/_21336_/Z (CLKBUF_X2_7T5P0) |
| 16 0.25 soc/_20548_ (net) |
| 1.95 0.02 43.06 v soc/_26778_/A1 (NOR2_X2_7T5P0) |
| 12.01 7.55 50.61 ^ soc/_26778_/ZN (NOR2_X2_7T5P0) |
| 14 0.83 soc/_08573_ (net) |
| 12.03 0.23 50.84 ^ soc/_26799_/I (CLKBUF_X2_7T5P0) |
| 6.38 4.97 55.81 ^ soc/_26799_/Z (CLKBUF_X2_7T5P0) |
| 16 0.85 soc/_08591_ (net) |
| 6.38 0.04 55.85 ^ soc/_26800_/C (OAI211_X1_7T5P0) |
| 1.34 -0.02 55.83 v soc/_26800_/ZN (OAI211_X1_7T5P0) |
| 1 0.01 soc/_08592_ (net) |
| 1.34 0.00 55.83 v soc/_26801_/B (OAI21_X1_7T5P0) |
| 0.66 0.57 56.40 ^ soc/_26801_/ZN (OAI21_X1_7T5P0) |
| 1 0.01 soc/_08593_ (net) |
| 0.66 0.00 56.40 ^ soc/_26802_/I (CLKBUF_X1_7T5P0) |
| 0.12 0.28 56.68 ^ soc/_26802_/Z (CLKBUF_X1_7T5P0) |
| 1 0.00 soc/_00735_ (net) |
| 0.12 0.00 56.68 ^ soc/_42542_/D (DFFQ_X1_7T5P0) |
| 56.68 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.43 28.36 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.01 28.37 ^ soc/clkbuf_2_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.29 28.66 ^ soc/clkbuf_2_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_0_0_core_clk (net) |
| 0.11 0.00 28.66 ^ soc/clkbuf_2_0_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.31 28.96 ^ soc/clkbuf_2_0_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_2_0_1_core_clk (net) |
| 0.23 0.00 28.97 ^ soc/clkbuf_3_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.12 0.26 29.23 ^ soc/clkbuf_3_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_3_1_0_core_clk (net) |
| 0.12 0.00 29.23 ^ soc/clkbuf_3_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.34 0.37 29.60 ^ soc/clkbuf_3_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.15 soc/clknet_3_1_1_core_clk (net) |
| 0.34 0.01 29.61 ^ soc/clkbuf_4_3_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.38 29.98 ^ soc/clkbuf_4_3_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_3_0_core_clk (net) |
| 0.27 0.01 29.99 ^ soc/clkbuf_5_7_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.20 0.32 30.31 ^ soc/clkbuf_5_7_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_5_7_0_core_clk (net) |
| 0.20 0.00 30.31 ^ soc/clkbuf_6_15_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.57 30.88 ^ soc/clkbuf_6_15_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.33 soc/clknet_6_15_0_core_clk (net) |
| 0.69 0.01 30.89 ^ soc/clkbuf_leaf_81_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.39 31.28 ^ soc/clkbuf_leaf_81_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.14 soc/clknet_leaf_81_core_clk (net) |
| 0.20 0.01 31.29 ^ soc/_42542_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.04 clock uncertainty |
| 0.35 31.39 clock reconvergence pessimism |
| -0.20 31.19 library setup time |
| 31.19 data required time |
| ----------------------------------------------------------------------------- |
| 31.19 data required time |
| -56.68 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.49 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43009_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.16 55.09 v soc/_28759_/I (CLKBUF_X2_7T5P0) |
| 0.94 1.51 56.60 v soc/_28759_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_10088_ (net) |
| 0.94 0.00 56.61 v soc/_28814_/A2 (AOI21_X1_7T5P0) |
| 0.58 0.59 57.19 ^ soc/_28814_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10139_ (net) |
| 0.58 0.00 57.19 ^ soc/_28815_/I (CLKINV_X1_7T5P0) |
| 0.23 0.19 57.38 v soc/_28815_/ZN (CLKINV_X1_7T5P0) |
| 1 0.01 soc/_01202_ (net) |
| 0.23 0.00 57.38 v soc/_43009_/D (DFFQ_X1_7T5P0) |
| 57.38 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.68 31.67 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.02 31.68 ^ soc/clkbuf_leaf_435_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.41 32.09 ^ soc/clkbuf_leaf_435_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.13 soc/clknet_leaf_435_core_clk (net) |
| 0.20 0.00 32.09 ^ soc/_43009_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.84 clock uncertainty |
| 0.31 32.15 clock reconvergence pessimism |
| -0.24 31.90 library setup time |
| 31.90 data required time |
| ----------------------------------------------------------------------------- |
| 31.90 data required time |
| -57.38 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.48 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43008_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.16 55.09 v soc/_28759_/I (CLKBUF_X2_7T5P0) |
| 0.94 1.51 56.60 v soc/_28759_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_10088_ (net) |
| 0.94 0.01 56.61 v soc/_28803_/A2 (AOI21_X1_7T5P0) |
| 0.50 0.52 57.13 ^ soc/_28803_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10129_ (net) |
| 0.50 0.00 57.13 ^ soc/_28804_/I (CLKINV_X1_7T5P0) |
| 0.23 0.19 57.32 v soc/_28804_/ZN (CLKINV_X1_7T5P0) |
| 1 0.01 soc/_01201_ (net) |
| 0.23 0.00 57.32 v soc/_43008_/D (DFFQ_X1_7T5P0) |
| 57.32 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.53 31.51 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 31.52 ^ soc/clkbuf_opt_26_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.34 31.86 ^ soc/clkbuf_opt_26_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_26_0_core_clk (net) |
| 0.15 0.01 31.86 ^ soc/clkbuf_leaf_432_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.27 32.13 ^ soc/clkbuf_leaf_432_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.09 soc/clknet_leaf_432_core_clk (net) |
| 0.15 0.00 32.13 ^ soc/_43008_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.88 clock uncertainty |
| 0.31 32.19 clock reconvergence pessimism |
| -0.25 31.93 library setup time |
| 31.93 data required time |
| ----------------------------------------------------------------------------- |
| 31.93 data required time |
| -57.32 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.39 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43012_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.16 55.09 v soc/_28759_/I (CLKBUF_X2_7T5P0) |
| 0.94 1.51 56.60 v soc/_28759_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_10088_ (net) |
| 0.94 0.00 56.60 v soc/_28861_/A2 (AOI21_X1_7T5P0) |
| 0.65 0.55 57.16 ^ soc/_28861_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10183_ (net) |
| 0.65 0.00 57.16 ^ soc/_28862_/I (CLKINV_X1_7T5P0) |
| 0.20 0.14 57.30 v soc/_28862_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01205_ (net) |
| 0.20 0.00 57.30 v soc/_43012_/D (DFFQ_X1_7T5P0) |
| 57.30 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_35_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.87 0.68 31.67 ^ soc/clkbuf_6_35_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 20 0.42 soc/clknet_6_35_0_core_clk (net) |
| 0.87 0.02 31.68 ^ soc/clkbuf_leaf_435_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.41 32.09 ^ soc/clkbuf_leaf_435_core_clk/Z (CLKBUF_X16_7T5P0) |
| 26 0.13 soc/clknet_leaf_435_core_clk (net) |
| 0.20 0.00 32.09 ^ soc/_43012_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.84 clock uncertainty |
| 0.31 32.15 clock reconvergence pessimism |
| -0.23 31.92 library setup time |
| 31.92 data required time |
| ----------------------------------------------------------------------------- |
| 31.92 data required time |
| -57.30 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.38 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43010_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.16 55.09 v soc/_28759_/I (CLKBUF_X2_7T5P0) |
| 0.94 1.51 56.60 v soc/_28759_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_10088_ (net) |
| 0.94 0.00 56.61 v soc/_28836_/A2 (AOI21_X1_7T5P0) |
| 0.61 0.57 57.17 ^ soc/_28836_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10160_ (net) |
| 0.61 0.00 57.17 ^ soc/_28837_/I (CLKINV_X1_7T5P0) |
| 0.20 0.15 57.32 v soc/_28837_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01203_ (net) |
| 0.20 0.00 57.32 v soc/_43010_/D (DFFQ_X1_7T5P0) |
| 57.32 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.53 31.51 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 31.52 ^ soc/clkbuf_opt_26_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.34 31.86 ^ soc/clkbuf_opt_26_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_26_0_core_clk (net) |
| 0.15 0.01 31.86 ^ soc/clkbuf_leaf_432_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.27 32.13 ^ soc/clkbuf_leaf_432_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.09 soc/clknet_leaf_432_core_clk (net) |
| 0.15 0.00 32.13 ^ soc/_43010_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.88 clock uncertainty |
| 0.31 32.19 clock reconvergence pessimism |
| -0.25 31.94 library setup time |
| 31.94 data required time |
| ----------------------------------------------------------------------------- |
| 31.94 data required time |
| -57.32 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.38 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43011_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.16 55.09 v soc/_28759_/I (CLKBUF_X2_7T5P0) |
| 0.94 1.51 56.60 v soc/_28759_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_10088_ (net) |
| 0.94 0.01 56.61 v soc/_28849_/A2 (AOI21_X1_7T5P0) |
| 0.56 0.54 57.15 ^ soc/_28849_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10172_ (net) |
| 0.56 0.00 57.15 ^ soc/_28850_/I (CLKINV_X1_7T5P0) |
| 0.18 0.14 57.28 v soc/_28850_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01204_ (net) |
| 0.18 0.00 57.28 v soc/_43011_/D (DFFQ_X1_7T5P0) |
| 57.28 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.53 31.51 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 31.52 ^ soc/clkbuf_opt_27_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.34 31.86 ^ soc/clkbuf_opt_27_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_27_0_core_clk (net) |
| 0.15 0.00 31.86 ^ soc/clkbuf_leaf_433_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.28 32.14 ^ soc/clkbuf_leaf_433_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.11 soc/clknet_leaf_433_core_clk (net) |
| 0.17 0.00 32.14 ^ soc/_43011_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.89 clock uncertainty |
| 0.31 32.20 clock reconvergence pessimism |
| -0.24 31.96 library setup time |
| 31.96 data required time |
| ----------------------------------------------------------------------------- |
| 31.96 data required time |
| -57.28 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.32 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43006_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.16 55.09 v soc/_28759_/I (CLKBUF_X2_7T5P0) |
| 0.94 1.51 56.60 v soc/_28759_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_10088_ (net) |
| 0.94 0.01 56.61 v soc/_28780_/A2 (AOI21_X1_7T5P0) |
| 0.52 0.53 57.14 ^ soc/_28780_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10108_ (net) |
| 0.52 0.00 57.14 ^ soc/_28781_/I (CLKINV_X1_7T5P0) |
| 0.17 0.13 57.27 v soc/_28781_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01199_ (net) |
| 0.17 0.00 57.27 v soc/_43006_/D (DFFQ_X1_7T5P0) |
| 57.27 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.53 31.51 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 31.52 ^ soc/clkbuf_opt_26_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.34 31.86 ^ soc/clkbuf_opt_26_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_26_0_core_clk (net) |
| 0.15 0.01 31.86 ^ soc/clkbuf_leaf_432_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.27 32.13 ^ soc/clkbuf_leaf_432_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.09 soc/clknet_leaf_432_core_clk (net) |
| 0.15 0.00 32.13 ^ soc/_43006_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.88 clock uncertainty |
| 0.31 32.19 clock reconvergence pessimism |
| -0.24 31.95 library setup time |
| 31.95 data required time |
| ----------------------------------------------------------------------------- |
| 31.95 data required time |
| -57.27 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.32 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43014_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28863_/I (CLKBUF_X2_7T5P0) |
| 0.91 1.49 56.59 v soc/_28863_/Z (CLKBUF_X2_7T5P0) |
| 16 0.10 soc/_10184_ (net) |
| 0.91 0.00 56.59 v soc/_28884_/A2 (AOI21_X1_7T5P0) |
| 0.55 0.51 57.10 ^ soc/_28884_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10204_ (net) |
| 0.55 0.00 57.10 ^ soc/_28885_/I (CLKINV_X1_7T5P0) |
| 0.20 0.16 57.26 v soc/_28885_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01207_ (net) |
| 0.20 0.00 57.26 v soc/_43014_/D (DFFQ_X1_7T5P0) |
| 57.26 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.53 31.51 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 31.52 ^ soc/clkbuf_opt_27_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.34 31.86 ^ soc/clkbuf_opt_27_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_27_0_core_clk (net) |
| 0.15 0.00 31.86 ^ soc/clkbuf_leaf_433_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.17 0.28 32.14 ^ soc/clkbuf_leaf_433_core_clk/Z (CLKBUF_X16_7T5P0) |
| 22 0.11 soc/clknet_leaf_433_core_clk (net) |
| 0.17 0.00 32.14 ^ soc/_43014_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.89 clock uncertainty |
| 0.31 32.20 clock reconvergence pessimism |
| -0.24 31.96 library setup time |
| 31.96 data required time |
| ----------------------------------------------------------------------------- |
| 31.96 data required time |
| -57.26 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.31 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_45338_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: soc/_43015_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock source latency |
| 0.00 0.00 0.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 0.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 1.02 1.02 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 1.02 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.31 1.33 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 1.33 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.29 1.62 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 1.62 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.49 2.12 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 2.12 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.73 2.84 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 2.84 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.39 3.23 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 3.24 ^ soc/clkbuf_1_0_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.45 0.48 3.71 ^ soc/clkbuf_1_0_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.21 soc/clknet_1_0_0_core_clk (net) |
| 0.45 0.02 3.73 ^ soc/clkbuf_2_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.31 4.04 ^ soc/clkbuf_2_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_2_1_0_core_clk (net) |
| 0.11 0.00 4.04 ^ soc/clkbuf_2_1_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.25 0.35 4.39 ^ soc/clkbuf_2_1_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.10 soc/clknet_2_1_1_core_clk (net) |
| 0.25 0.01 4.39 ^ soc/clkbuf_3_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.27 4.67 ^ soc/clkbuf_3_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_2_0_core_clk (net) |
| 0.11 0.00 4.67 ^ soc/clkbuf_3_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.29 0.38 5.04 ^ soc/clkbuf_3_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.13 soc/clknet_3_2_1_core_clk (net) |
| 0.29 0.01 5.05 ^ soc/clkbuf_4_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.19 0.35 5.40 ^ soc/clkbuf_4_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.07 soc/clknet_4_4_0_core_clk (net) |
| 0.19 0.00 5.40 ^ soc/clkbuf_5_9_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.22 0.35 5.75 ^ soc/clkbuf_5_9_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_9_0_core_clk (net) |
| 0.22 0.00 5.75 ^ soc/clkbuf_6_19_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.78 0.70 6.45 ^ soc/clkbuf_6_19_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 18 0.38 soc/clknet_6_19_0_core_clk (net) |
| 0.78 0.01 6.46 ^ soc/clkbuf_leaf_123_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.20 0.44 6.90 ^ soc/clkbuf_leaf_123_core_clk/Z (CLKBUF_X16_7T5P0) |
| 24 0.13 soc/clknet_leaf_123_core_clk (net) |
| 0.20 0.00 6.90 ^ soc/_45338_/CLK (DFFQ_X1_7T5P0) |
| 10.76 7.24 14.14 ^ soc/_45338_/Q (DFFQ_X1_7T5P0) |
| 6 0.68 soc/net416 (net) |
| 10.77 0.18 14.32 ^ soc/output416/I (CLKBUF_X4_7T5P0) |
| 2.88 2.73 17.05 ^ soc/output416/Z (CLKBUF_X4_7T5P0) |
| 66 0.67 mprj_iena_wb (net) |
| 2.88 0.00 17.05 ^ mgmt_buffers/user_wb_ack_gate/A2 (NAND2_X4_7T5P0) |
| 0.66 0.15 17.20 v mgmt_buffers/user_wb_ack_gate/ZN (NAND2_X4_7T5P0) |
| 1 0.05 mgmt_buffers/mprj_ack_i_core_bar (net) |
| 0.66 0.00 17.20 v mgmt_buffers/user_wb_ack_buffer/I (INV_X8_7T5P0) |
| 0.14 0.18 17.37 ^ mgmt_buffers/user_wb_ack_buffer/ZN (INV_X8_7T5P0) |
| 2 0.00 mprj_ack_i_core (net) |
| 0.14 0.00 17.37 ^ soc/input108/I (CLKBUF_X1_7T5P0) |
| 9.02 5.54 22.91 ^ soc/input108/Z (CLKBUF_X1_7T5P0) |
| 2 0.56 soc/net108 (net) |
| 9.04 0.23 23.14 ^ soc/_21137_/A3 (NOR4_X2_7T5P0) |
| 2.43 0.28 23.42 v soc/_21137_/ZN (NOR4_X2_7T5P0) |
| 1 0.02 soc/_20349_ (net) |
| 2.43 0.00 23.42 v soc/_21138_/A4 (NAND4_X4_7T5P0) |
| 1.80 1.78 25.20 ^ soc/_21138_/ZN (NAND4_X4_7T5P0) |
| 10 0.23 soc/_20350_ (net) |
| 1.80 0.01 25.21 ^ soc/_21139_/A2 (NAND2_X1_7T5P0) |
| 1.00 0.69 25.90 v soc/_21139_/ZN (NAND2_X1_7T5P0) |
| 4 0.05 soc/_20351_ (net) |
| 1.00 0.00 25.91 v soc/_21140_/A3 (NOR3_X2_7T5P0) |
| 15.90 9.51 35.42 ^ soc/_21140_/ZN (NOR3_X2_7T5P0) |
| 6 0.74 soc/_20352_ (net) |
| 15.90 0.09 35.51 ^ soc/_21141_/A3 (OR3_X1_7T5P0) |
| 0.62 -0.94 34.58 ^ soc/_21141_/Z (OR3_X1_7T5P0) |
| 2 0.02 soc/_20353_ (net) |
| 0.62 0.00 34.58 ^ soc/_21142_/A2 (NAND2_X2_7T5P0) |
| 1.66 0.81 35.38 v soc/_21142_/ZN (NAND2_X2_7T5P0) |
| 14 0.15 soc/_20354_ (net) |
| 1.66 0.01 35.39 v soc/_21218_/A1 (OR2_X1_7T5P0) |
| 3.05 2.88 38.27 v soc/_21218_/Z (OR2_X1_7T5P0) |
| 8 0.32 soc/_20430_ (net) |
| 3.06 0.07 38.34 v soc/_21328_/A1 (OR3_X1_7T5P0) |
| 1.04 2.39 40.73 v soc/_21328_/Z (OR3_X1_7T5P0) |
| 6 0.09 soc/_20540_ (net) |
| 1.04 0.01 40.74 v soc/_21329_/I (CLKBUF_X2_7T5P0) |
| 0.52 0.74 41.48 v soc/_21329_/Z (CLKBUF_X2_7T5P0) |
| 8 0.06 soc/_20541_ (net) |
| 0.52 0.00 41.49 v soc/_21330_/I (CLKINV_X1_7T5P0) |
| 0.41 0.38 41.87 ^ soc/_21330_/ZN (CLKINV_X1_7T5P0) |
| 3 0.02 soc/_20542_ (net) |
| 0.41 0.00 41.87 ^ soc/_21331_/I (CLKBUF_X2_7T5P0) |
| 0.95 0.84 42.70 ^ soc/_21331_/Z (CLKBUF_X2_7T5P0) |
| 16 0.11 soc/_20543_ (net) |
| 0.95 0.00 42.71 ^ soc/_26750_/A1 (NAND2_X1_7T5P0) |
| 1.96 0.99 43.69 v soc/_26750_/ZN (NAND2_X1_7T5P0) |
| 10 0.08 soc/_08545_ (net) |
| 1.96 0.00 43.70 v soc/_26787_/I (BUF_X1_7T5P0) |
| 7.44 5.41 49.11 v soc/_26787_/Z (BUF_X1_7T5P0) |
| 16 0.78 soc/_08580_ (net) |
| 7.46 0.23 49.33 v soc/_26788_/I (BUF_X1_7T5P0) |
| 5.53 5.59 54.93 v soc/_26788_/Z (BUF_X1_7T5P0) |
| 16 0.60 soc/_08581_ (net) |
| 5.55 0.17 55.09 v soc/_28863_/I (CLKBUF_X2_7T5P0) |
| 0.91 1.49 56.59 v soc/_28863_/Z (CLKBUF_X2_7T5P0) |
| 16 0.10 soc/_10184_ (net) |
| 0.91 0.00 56.59 v soc/_28895_/A2 (AOI21_X1_7T5P0) |
| 0.73 0.50 57.08 ^ soc/_28895_/ZN (AOI21_X1_7T5P0) |
| 1 0.01 soc/_10214_ (net) |
| 0.73 0.00 57.08 ^ soc/_28896_/I (CLKINV_X1_7T5P0) |
| 0.21 0.15 57.23 v soc/_28896_/ZN (CLKINV_X1_7T5P0) |
| 1 0.00 soc/_01208_ (net) |
| 0.21 0.00 57.23 v soc/_43015_/D (DFFQ_X1_7T5P0) |
| 57.23 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock source latency |
| 0.00 0.00 25.00 ^ clock (in) |
| 1 2.96 clock (net) |
| 0.00 0.00 25.00 ^ padframe/mgmt_clock_input_pad/PAD (GF_NI_IN_C) |
| 0.18 0.92 25.92 ^ padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 6 0.02 clock_core (net) |
| 0.18 0.00 25.92 ^ clock_ctrl/_231_/I0 (MUX2_X2_7T5P0) |
| 0.14 0.28 26.20 ^ clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 2 0.01 clock_ctrl/_038_ (net) |
| 0.14 0.00 26.20 ^ clock_ctrl/_232_/I0 (MUX2_X2_7T5P0) |
| 0.11 0.26 26.47 ^ clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 1 0.01 clock_ctrl/_039_ (net) |
| 0.11 0.00 26.47 ^ clock_ctrl/_233_/I (BUF_X2_7T5P0) |
| 0.59 0.45 26.91 ^ clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 8 0.07 clock_ctrl/net12 (net) |
| 0.59 0.00 26.92 ^ clock_ctrl/output12/I (BUF_X1_7T5P0) |
| 0.90 0.66 27.57 ^ clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 6 0.05 caravel_clk (net) |
| 0.90 0.00 27.57 ^ soc/clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.13 0.36 27.93 ^ soc/clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.05 soc/clknet_0_core_clk (net) |
| 0.13 0.00 27.93 ^ soc/clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.95 0.68 28.60 ^ soc/clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.47 soc/clknet_1_1_0_core_clk (net) |
| 0.96 0.07 28.67 ^ soc/clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.14 0.36 29.03 ^ soc/clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.03 soc/clknet_2_2_0_core_clk (net) |
| 0.14 0.00 29.03 ^ soc/clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.26 0.33 29.36 ^ soc/clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_2_2_1_core_clk (net) |
| 0.26 0.00 29.37 ^ soc/clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.11 0.25 29.62 ^ soc/clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 1 0.02 soc/clknet_3_4_0_core_clk (net) |
| 0.11 0.00 29.62 ^ soc/clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.68 0.54 30.15 ^ soc/clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.33 soc/clknet_3_4_1_core_clk (net) |
| 0.69 0.05 30.21 ^ soc/clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.27 0.42 30.63 ^ soc/clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.11 soc/clknet_4_8_0_core_clk (net) |
| 0.27 0.01 30.64 ^ soc/clkbuf_5_17_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.23 0.34 30.98 ^ soc/clkbuf_5_17_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 4 0.09 soc/clknet_5_17_0_core_clk (net) |
| 0.23 0.01 30.98 ^ soc/clkbuf_6_34_0_core_clk/I (CLKBUF_X8_7T5P0) |
| 0.59 0.53 31.51 ^ soc/clkbuf_6_34_0_core_clk/Z (CLKBUF_X8_7T5P0) |
| 14 0.28 soc/clknet_6_34_0_core_clk (net) |
| 0.59 0.01 31.52 ^ soc/clkbuf_opt_26_0_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.34 31.86 ^ soc/clkbuf_opt_26_0_core_clk/Z (CLKBUF_X16_7T5P0) |
| 2 0.08 soc/clknet_opt_26_0_core_clk (net) |
| 0.15 0.01 31.86 ^ soc/clkbuf_leaf_432_core_clk/I (CLKBUF_X16_7T5P0) |
| 0.15 0.27 32.13 ^ soc/clkbuf_leaf_432_core_clk/Z (CLKBUF_X16_7T5P0) |
| 18 0.09 soc/clknet_leaf_432_core_clk (net) |
| 0.15 0.00 32.13 ^ soc/_43015_/CLK (DFFQ_X1_7T5P0) |
| -0.25 31.88 clock uncertainty |
| 0.31 32.19 clock reconvergence pessimism |
| -0.25 31.94 library setup time |
| 31.94 data required time |
| ----------------------------------------------------------------------------- |
| 31.94 data required time |
| -57.23 data arrival time |
| ----------------------------------------------------------------------------- |
| -25.30 slack (VIOLATED) |
| |
| |
| Management Area Interface |
| No paths found. |
| User project Interface |
| Startpoint: clock (clock source 'clock') |
| Endpoint: mprj/wb_clk_i (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 12.50 v clock (in) |
| 0.87 13.37 v padframe/mgmt_clock_input_pad/Y (GF_NI_IN_C) |
| 0.40 13.77 v clock_ctrl/_231_/Z (MUX2_X2_7T5P0) |
| 0.38 14.15 v clock_ctrl/_232_/Z (MUX2_X2_7T5P0) |
| 0.43 14.58 v clock_ctrl/_233_/Z (BUF_X2_7T5P0) |
| 0.65 15.23 v clock_ctrl/output12/Z (BUF_X1_7T5P0) |
| 0.35 15.58 v mgmt_buffers/_199_/Z (BUF_X1_7T5P0) |
| 0.00 15.58 v mprj/wb_clk_i (user_project_wrapper) |
| 15.58 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: clock_ctrl/_445_ (falling edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wb_rst_i (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 14.59 v clock_ctrl/_445_/CLKN (DFFNSNQ_X1_7T5P0) |
| 0.96 15.55 ^ clock_ctrl/_445_/Q (DFFNSNQ_X1_7T5P0) |
| 0.21 15.76 v clock_ctrl/_246_/ZN (NOR2_X1_7T5P0) |
| 0.44 16.20 v clock_ctrl/_247_/Z (CLKBUF_X1_7T5P0) |
| 0.33 16.52 v clock_ctrl/output13/Z (BUF_X4_7T5P0) |
| 0.22 16.74 v mgmt_buffers/_201_/Z (BUF_X1_7T5P0) |
| 0.00 16.74 v mprj/wb_rst_i (user_project_wrapper) |
| 16.74 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44446_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_cyc_i (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.78 ^ soc/_44446_/CLK (DFFQ_X1_7T5P0) |
| 7.18 13.96 ^ soc/_44446_/Q (DFFQ_X1_7T5P0) |
| 9.18 23.14 v soc/_21076_/ZN (CLKINV_X1_7T5P0) |
| 3.91 27.06 ^ soc/_21078_/ZN (OAI21_X1_7T5P0) |
| 0.49 27.54 v soc/_21079_/ZN (AOI22_X1_7T5P0) |
| 0.59 28.14 ^ soc/_21080_/ZN (NOR2_X1_7T5P0) |
| 0.97 29.10 v soc/_21081_/ZN (AOI21_X4_7T5P0) |
| 10.27 39.37 ^ soc/_24370_/ZN (NOR2_X1_7T5P0) |
| 1.07 40.45 ^ soc/_24371_/Z (CLKBUF_X1_7T5P0) |
| 0.31 40.76 ^ soc/output378/Z (CLKBUF_X4_7T5P0) |
| 0.17 40.93 ^ mgmt_buffers/_160_/Z (BUF_X1_7T5P0) |
| 0.00 40.93 ^ mprj/wbs_cyc_i (user_project_wrapper) |
| 40.93 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44446_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_stb_i (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.78 ^ soc/_44446_/CLK (DFFQ_X1_7T5P0) |
| 7.18 13.96 ^ soc/_44446_/Q (DFFQ_X1_7T5P0) |
| 9.18 23.14 v soc/_21076_/ZN (CLKINV_X1_7T5P0) |
| 3.91 27.06 ^ soc/_21078_/ZN (OAI21_X1_7T5P0) |
| 0.49 27.54 v soc/_21079_/ZN (AOI22_X1_7T5P0) |
| 0.59 28.14 ^ soc/_21080_/ZN (NOR2_X1_7T5P0) |
| 0.97 29.10 v soc/_21081_/ZN (AOI21_X4_7T5P0) |
| 5.18 34.28 ^ soc/_21082_/ZN (INV_X2_7T5P0) |
| 1.32 35.61 ^ soc/_46517_/Z (CLKBUF_X1_7T5P0) |
| 0.35 35.95 ^ soc/output415/Z (CLKBUF_X4_7T5P0) |
| 0.17 36.12 ^ mgmt_buffers/_197_/Z (BUF_X1_7T5P0) |
| 0.00 36.12 ^ mprj/wbs_stb_i (user_project_wrapper) |
| 36.12 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_we_i (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.30 11.39 v soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.86 12.25 v soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.18 13.42 v soc/_20842_/Z (BUF_X2_7T5P0) |
| 2.18 15.60 ^ soc/_21052_/ZN (AOI22_X4_7T5P0) |
| 7.66 23.26 v soc/_21053_/ZN (CLKINV_X1_7T5P0) |
| 1.66 24.92 v soc/output417/Z (CLKBUF_X4_7T5P0) |
| 0.29 25.21 v mgmt_buffers/_198_/Z (BUF_X1_7T5P0) |
| 0.00 25.21 v mprj/wbs_we_i (user_project_wrapper) |
| 25.21 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_sel_i[0] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.52 13.93 ^ soc/_20842_/Z (BUF_X2_7T5P0) |
| 1.30 15.23 ^ soc/_20843_/Z (BUF_X3_7T5P0) |
| 1.21 16.44 ^ soc/_20844_/Z (CLKBUF_X2_7T5P0) |
| 1.05 17.49 v soc/_21054_/ZN (NAND2_X1_7T5P0) |
| 1.07 18.57 v soc/_21071_/Z (OR2_X1_7T5P0) |
| 3.02 21.59 v soc/_21072_/Z (CLKBUF_X2_7T5P0) |
| 0.92 22.50 v soc/output414/Z (CLKBUF_X4_7T5P0) |
| 0.24 22.74 v mgmt_buffers/_196_/Z (BUF_X1_7T5P0) |
| 0.00 22.74 v mprj/wbs_sel_i[0] (user_project_wrapper) |
| 22.74 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_sel_i[3] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.52 13.93 ^ soc/_20842_/Z (BUF_X2_7T5P0) |
| 1.30 15.23 ^ soc/_20843_/Z (BUF_X3_7T5P0) |
| 1.21 16.44 ^ soc/_20844_/Z (CLKBUF_X2_7T5P0) |
| 1.05 17.49 v soc/_21054_/ZN (NAND2_X1_7T5P0) |
| 1.04 18.54 v soc/_21056_/Z (OR2_X1_7T5P0) |
| 2.22 20.76 v soc/_21057_/Z (CLKBUF_X2_7T5P0) |
| 0.79 21.55 v soc/output411/Z (CLKBUF_X4_7T5P0) |
| 0.23 21.79 v mgmt_buffers/_193_/Z (BUF_X1_7T5P0) |
| 0.00 21.79 v mprj/wbs_sel_i[3] (user_project_wrapper) |
| 21.79 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_sel_i[2] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.52 13.93 ^ soc/_20842_/Z (BUF_X2_7T5P0) |
| 1.30 15.23 ^ soc/_20843_/Z (BUF_X3_7T5P0) |
| 1.21 16.44 ^ soc/_20844_/Z (CLKBUF_X2_7T5P0) |
| 1.05 17.49 v soc/_21054_/ZN (NAND2_X1_7T5P0) |
| 1.05 18.54 v soc/_21061_/Z (OR2_X1_7T5P0) |
| 2.17 20.71 v soc/_21062_/Z (CLKBUF_X2_7T5P0) |
| 0.76 21.48 v soc/output412/Z (CLKBUF_X4_7T5P0) |
| 0.23 21.71 v mgmt_buffers/_194_/Z (BUF_X1_7T5P0) |
| 0.00 21.71 v mprj/wbs_sel_i[2] (user_project_wrapper) |
| 21.71 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_sel_i[1] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.52 13.93 ^ soc/_20842_/Z (BUF_X2_7T5P0) |
| 1.30 15.23 ^ soc/_20843_/Z (BUF_X3_7T5P0) |
| 1.21 16.44 ^ soc/_20844_/Z (CLKBUF_X2_7T5P0) |
| 1.05 17.49 v soc/_21054_/ZN (NAND2_X1_7T5P0) |
| 1.08 18.58 v soc/_21067_/Z (OR2_X1_7T5P0) |
| 1.97 20.55 v soc/_21068_/Z (CLKBUF_X2_7T5P0) |
| 0.74 21.29 v soc/output413/Z (CLKBUF_X4_7T5P0) |
| 0.23 21.52 v mgmt_buffers/_195_/Z (BUF_X1_7T5P0) |
| 0.00 21.52 v mprj/wbs_sel_i[1] (user_project_wrapper) |
| 21.52 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[16] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.52 13.93 ^ soc/_20842_/Z (BUF_X2_7T5P0) |
| 0.26 14.19 v soc/_21033_/ZN (AOI22_X1_7T5P0) |
| 0.67 14.86 v soc/_21034_/Z (AND2_X1_7T5P0) |
| 1.64 16.50 v soc/_21035_/Z (CLKBUF_X2_7T5P0) |
| 7.27 23.77 ^ soc/_21036_/ZN (INV_X1_7T5P0) |
| 1.23 25.00 ^ soc/output353/Z (CLKBUF_X4_7T5P0) |
| 0.21 25.21 ^ mgmt_buffers/_143_/Z (BUF_X1_7T5P0) |
| 0.00 25.21 ^ mprj/wbs_adr_i[16] (user_project_wrapper) |
| 25.21 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[14] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.80 9.58 v soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.31 10.90 v soc/_20940_/Z (CLKBUF_X2_7T5P0) |
| 2.68 13.58 ^ soc/_20984_/ZN (AOI22_X1_7T5P0) |
| 1.38 14.95 ^ soc/_20985_/Z (AND2_X1_7T5P0) |
| 6.83 21.78 v soc/_20986_/ZN (CLKINV_X1_7T5P0) |
| 1.50 23.28 v soc/output355/Z (CLKBUF_X4_7T5P0) |
| 0.29 23.57 v mgmt_buffers/_145_/Z (BUF_X1_7T5P0) |
| 0.00 23.57 v mprj/wbs_adr_i[14] (user_project_wrapper) |
| 23.57 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[12] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.80 9.58 v soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.31 10.90 v soc/_20940_/Z (CLKBUF_X2_7T5P0) |
| 0.88 11.78 v soc/_20941_/Z (CLKBUF_X2_7T5P0) |
| 0.33 12.11 ^ soc/_20975_/ZN (NAND2_X1_7T5P0) |
| 2.79 14.90 ^ soc/_20977_/Z (AND2_X1_7T5P0) |
| 6.89 21.80 v soc/_20978_/ZN (CLKINV_X1_7T5P0) |
| 1.48 23.28 v soc/output357/Z (CLKBUF_X4_7T5P0) |
| 0.28 23.55 v mgmt_buffers/_147_/Z (BUF_X1_7T5P0) |
| 0.00 23.55 v mprj/wbs_adr_i[12] (user_project_wrapper) |
| 23.55 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[18] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.30 11.39 v soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.86 12.25 v soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.40 13.65 ^ soc/_21024_/ZN (NAND2_X1_7T5P0) |
| 1.52 15.17 ^ soc/_21026_/Z (AND2_X2_7T5P0) |
| 4.17 19.34 v soc/_21027_/ZN (CLKINV_X2_7T5P0) |
| 1.26 20.60 v soc/output351/Z (CLKBUF_X4_7T5P0) |
| 0.26 20.85 v mgmt_buffers/_141_/Z (BUF_X1_7T5P0) |
| 0.00 20.85 v mprj/wbs_adr_i[18] (user_project_wrapper) |
| 20.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[19] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.30 11.39 v soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.86 12.25 v soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.18 13.42 v soc/_20842_/Z (BUF_X2_7T5P0) |
| 0.68 14.11 ^ soc/_21021_/ZN (AOI22_X1_7T5P0) |
| 1.58 15.68 ^ soc/_21022_/Z (AND2_X2_7T5P0) |
| 3.81 19.49 v soc/_21023_/ZN (CLKINV_X2_7T5P0) |
| 1.08 20.57 v soc/output350/Z (CLKBUF_X4_7T5P0) |
| 0.25 20.82 v mgmt_buffers/_140_/Z (BUF_X1_7T5P0) |
| 0.00 20.82 v mprj/wbs_adr_i[19] (user_project_wrapper) |
| 20.82 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[17] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.30 11.39 v soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.86 12.25 v soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.18 13.42 v soc/_20842_/Z (BUF_X2_7T5P0) |
| 0.62 14.05 ^ soc/_21029_/ZN (AOI22_X1_7T5P0) |
| 1.76 15.81 ^ soc/_21030_/Z (AND2_X2_7T5P0) |
| 3.70 19.51 v soc/_21031_/ZN (CLKINV_X2_7T5P0) |
| 1.03 20.55 v soc/output352/Z (CLKBUF_X4_7T5P0) |
| 0.25 20.79 v mgmt_buffers/_142_/Z (BUF_X1_7T5P0) |
| 0.00 20.79 v mprj/wbs_adr_i[17] (user_project_wrapper) |
| 20.79 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44900_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[3] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44900_/CLK (DFFQ_X1_7T5P0) |
| 1.01 8.11 v soc/_44900_/Q (DFFQ_X1_7T5P0) |
| 0.67 8.78 ^ soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.90 9.68 ^ soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.31 10.99 ^ soc/_20940_/Z (CLKBUF_X2_7T5P0) |
| 0.76 11.75 v soc/_20999_/ZN (NAND2_X1_7T5P0) |
| 0.99 12.73 v soc/_21001_/Z (AND2_X1_7T5P0) |
| 6.66 19.40 ^ soc/_21002_/ZN (INV_X1_7T5P0) |
| 1.06 20.46 ^ soc/output366/Z (CLKBUF_X4_7T5P0) |
| 0.21 20.67 ^ mgmt_buffers/_156_/Z (BUF_X1_7T5P0) |
| 0.00 20.67 ^ mprj/wbs_adr_i[3] (user_project_wrapper) |
| 20.67 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[20] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.30 11.39 v soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.86 12.25 v soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 1.18 13.42 v soc/_20842_/Z (BUF_X2_7T5P0) |
| 0.65 14.07 ^ soc/_21014_/ZN (AOI22_X1_7T5P0) |
| 0.87 14.94 ^ soc/_21015_/Z (AND2_X1_7T5P0) |
| 3.94 18.88 v soc/_21016_/ZN (CLKINV_X2_7T5P0) |
| 1.21 20.09 v soc/output349/Z (CLKBUF_X4_7T5P0) |
| 0.26 20.35 v mgmt_buffers/_139_/Z (BUF_X1_7T5P0) |
| 0.00 20.35 v mprj/wbs_adr_i[20] (user_project_wrapper) |
| 20.35 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[26] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.30 11.39 v soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.86 12.25 v soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 0.30 12.54 ^ soc/_20950_/ZN (NAND2_X1_7T5P0) |
| 2.98 15.52 ^ soc/_20952_/Z (AND2_X1_7T5P0) |
| 1.87 17.39 v soc/_20953_/ZN (INV_X1_7T5P0) |
| 1.63 19.02 v soc/_20954_/Z (BUF_X8_7T5P0) |
| 0.77 19.79 v soc/output373/Z (CLKBUF_X4_7T5P0) |
| 0.22 20.01 v mgmt_buffers/_133_/Z (BUF_X1_7T5P0) |
| 0.00 20.01 v mprj/wbs_adr_i[26] (user_project_wrapper) |
| 20.01 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[29] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.80 9.58 v soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.31 10.90 v soc/_20940_/Z (CLKBUF_X2_7T5P0) |
| 0.88 11.78 v soc/_20941_/Z (CLKBUF_X2_7T5P0) |
| 1.11 12.89 v soc/_20965_/Z (CLKBUF_X2_7T5P0) |
| 0.60 13.49 ^ soc/_20966_/ZN (NAND2_X1_7T5P0) |
| 2.96 16.44 ^ soc/_20968_/Z (AND2_X1_7T5P0) |
| 0.75 17.19 v soc/_20969_/ZN (CLKINV_X2_7T5P0) |
| 1.33 18.52 v soc/_20970_/Z (CLKBUF_X12_7T5P0) |
| 0.98 19.50 v soc/output368/Z (CLKBUF_X4_7T5P0) |
| 0.23 19.73 v mgmt_buffers/_130_/Z (BUF_X1_7T5P0) |
| 0.00 19.73 v mprj/wbs_adr_i[29] (user_project_wrapper) |
| 19.73 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_43729_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[11] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.81 ^ soc/_43729_/CLK (DFFQ_X1_7T5P0) |
| 1.88 8.69 v soc/_43729_/Q (DFFQ_X1_7T5P0) |
| 0.82 9.51 v soc/_21101_/Z (AND2_X1_7T5P0) |
| 1.31 10.82 ^ soc/_21102_/ZN (AOI221_X4_7T5P0) |
| 7.00 17.82 v soc/_21103_/ZN (CLKINV_X1_7T5P0) |
| 1.62 19.44 v soc/output358/Z (CLKBUF_X4_7T5P0) |
| 0.29 19.72 v mgmt_buffers/_148_/Z (BUF_X1_7T5P0) |
| 0.00 19.72 v mprj/wbs_adr_i[11] (user_project_wrapper) |
| 19.72 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[4] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.97 12.06 ^ soc/_21097_/ZN (AOI222_X2_7T5P0) |
| 5.79 17.85 v soc/_21098_/ZN (CLKINV_X1_7T5P0) |
| 1.30 19.15 v soc/output365/Z (CLKBUF_X4_7T5P0) |
| 0.27 19.41 v mgmt_buffers/_155_/Z (BUF_X1_7T5P0) |
| 0.00 19.41 v mprj/wbs_adr_i[4] (user_project_wrapper) |
| 19.41 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[7] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.58 9.36 v soc/_21004_/Z (AND2_X1_7T5P0) |
| 1.59 10.95 ^ soc/_21005_/ZN (AOI221_X4_7T5P0) |
| 6.43 17.38 v soc/_21006_/ZN (CLKINV_X1_7T5P0) |
| 1.36 18.74 v soc/output362/Z (CLKBUF_X4_7T5P0) |
| 0.28 19.02 v mgmt_buffers/_152_/Z (BUF_X1_7T5P0) |
| 0.00 19.02 v mprj/wbs_adr_i[7] (user_project_wrapper) |
| 19.02 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45158_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[6] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.84 ^ soc/_45158_/CLK (DFFQ_X1_7T5P0) |
| 2.11 8.95 v soc/_45158_/Q (DFFQ_X1_7T5P0) |
| 1.73 10.69 ^ soc/_21011_/ZN (AOI221_X4_7T5P0) |
| 6.55 17.24 v soc/_21012_/ZN (CLKINV_X1_7T5P0) |
| 1.39 18.63 v soc/output363/Z (CLKBUF_X4_7T5P0) |
| 0.28 18.91 v mgmt_buffers/_153_/Z (BUF_X1_7T5P0) |
| 0.00 18.91 v mprj/wbs_adr_i[6] (user_project_wrapper) |
| 18.91 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[13] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.80 9.58 v soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.31 10.90 v soc/_20940_/Z (CLKBUF_X2_7T5P0) |
| 2.79 13.69 ^ soc/_20980_/ZN (AOI22_X1_7T5P0) |
| 0.31 14.00 v soc/_20981_/ZN (NAND2_X1_7T5P0) |
| 3.50 17.49 v soc/_20982_/Z (CLKBUF_X2_7T5P0) |
| 1.14 18.63 v soc/output356/Z (CLKBUF_X4_7T5P0) |
| 0.25 18.88 v mgmt_buffers/_146_/Z (BUF_X1_7T5P0) |
| 0.00 18.88 v mprj/wbs_adr_i[13] (user_project_wrapper) |
| 18.88 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[8] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.80 9.58 v soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.49 11.07 ^ soc/_21099_/ZN (AOI222_X4_7T5P0) |
| 5.77 16.84 v soc/_21100_/ZN (CLKINV_X1_7T5P0) |
| 1.32 18.16 v soc/output361/Z (CLKBUF_X4_7T5P0) |
| 0.27 18.44 v mgmt_buffers/_151_/Z (BUF_X1_7T5P0) |
| 0.00 18.44 v mprj/wbs_adr_i[8] (user_project_wrapper) |
| 18.44 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[5] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.25 11.34 ^ soc/_21008_/ZN (AOI221_X4_7T5P0) |
| 5.37 16.71 v soc/_21009_/ZN (CLKINV_X1_7T5P0) |
| 1.30 18.01 v soc/output364/Z (CLKBUF_X4_7T5P0) |
| 0.27 18.28 v mgmt_buffers/_154_/Z (BUF_X1_7T5P0) |
| 0.00 18.28 v mprj/wbs_adr_i[5] (user_project_wrapper) |
| 18.28 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[1] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.84 11.92 ^ soc/_20994_/ZN (AOI221_X2_7T5P0) |
| 4.92 16.85 v soc/_20995_/ZN (CLKINV_X1_7T5P0) |
| 1.16 18.01 v soc/output369/Z (CLKBUF_X4_7T5P0) |
| 0.26 18.27 v mgmt_buffers/_158_/Z (BUF_X1_7T5P0) |
| 0.00 18.27 v mprj/wbs_adr_i[1] (user_project_wrapper) |
| 18.27 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[15] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.80 9.58 v soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.31 10.90 v soc/_20940_/Z (CLKBUF_X2_7T5P0) |
| 2.61 13.51 ^ soc/_20988_/ZN (AOI22_X1_7T5P0) |
| 0.30 13.81 v soc/_20989_/ZN (NAND2_X1_7T5P0) |
| 3.17 16.98 v soc/_20990_/Z (CLKBUF_X2_7T5P0) |
| 0.99 17.97 v soc/output354/Z (CLKBUF_X4_7T5P0) |
| 0.24 18.22 v mgmt_buffers/_144_/Z (BUF_X1_7T5P0) |
| 0.00 18.22 v mprj/wbs_adr_i[15] (user_project_wrapper) |
| 18.22 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[0] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.00 8.10 v soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.62 8.72 ^ soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.50 9.22 v soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.87 10.09 v soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.21 11.30 ^ soc/_20991_/ZN (AOI222_X4_7T5P0) |
| 5.41 16.71 v soc/_20992_/ZN (CLKINV_X1_7T5P0) |
| 1.22 17.93 v soc/output370/Z (CLKBUF_X4_7T5P0) |
| 0.27 18.20 v mgmt_buffers/_159_/Z (BUF_X1_7T5P0) |
| 0.00 18.20 v mprj/wbs_adr_i[0] (user_project_wrapper) |
| 18.20 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[27] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 0.22 12.63 v soc/_20956_/ZN (AOI22_X1_7T5P0) |
| 0.69 13.32 v soc/_20957_/Z (AND2_X1_7T5P0) |
| 1.42 14.74 v soc/_20958_/Z (CLKBUF_X4_7T5P0) |
| 2.03 16.76 ^ soc/_20959_/ZN (INV_X8_7T5P0) |
| 0.91 17.68 ^ soc/output372/Z (CLKBUF_X4_7T5P0) |
| 0.19 17.86 ^ mgmt_buffers/_132_/Z (BUF_X1_7T5P0) |
| 0.00 17.86 ^ mprj/wbs_adr_i[27] (user_project_wrapper) |
| 17.86 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[9] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.80 9.58 v soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.36 10.94 ^ soc/_21104_/ZN (AOI222_X4_7T5P0) |
| 5.39 16.34 v soc/_21105_/ZN (CLKINV_X1_7T5P0) |
| 1.24 17.58 v soc/output360/Z (CLKBUF_X4_7T5P0) |
| 0.27 17.84 v mgmt_buffers/_150_/Z (BUF_X1_7T5P0) |
| 0.00 17.84 v mprj/wbs_adr_i[9] (user_project_wrapper) |
| 17.84 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[2] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 0.54 10.95 v soc/_20997_/ZN (AOI221_X4_7T5P0) |
| 5.69 16.64 ^ soc/_20998_/ZN (INV_X1_7T5P0) |
| 0.95 17.59 ^ soc/output367/Z (CLKBUF_X4_7T5P0) |
| 0.20 17.79 ^ mgmt_buffers/_157_/Z (BUF_X1_7T5P0) |
| 0.00 17.79 ^ mprj/wbs_adr_i[2] (user_project_wrapper) |
| 17.79 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45154_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[10] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_45154_/CLK (DFFQ_X1_7T5P0) |
| 2.16 9.04 v soc/_45154_/Q (DFFQ_X1_7T5P0) |
| 2.00 11.04 ^ soc/_21018_/ZN (AOI221_X4_7T5P0) |
| 4.83 15.87 v soc/_21019_/ZN (CLKINV_X1_7T5P0) |
| 1.12 16.99 v soc/output359/Z (CLKBUF_X4_7T5P0) |
| 0.26 17.25 v mgmt_buffers/_149_/Z (BUF_X1_7T5P0) |
| 0.00 17.25 v mprj/wbs_adr_i[10] (user_project_wrapper) |
| 17.25 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[28] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 0.23 12.64 v soc/_20961_/ZN (AOI22_X1_7T5P0) |
| 0.54 13.18 v soc/_20962_/Z (AND2_X1_7T5P0) |
| 0.98 14.17 v soc/_20963_/Z (BUF_X3_7T5P0) |
| 1.82 15.99 ^ soc/_20964_/ZN (INV_X8_7T5P0) |
| 0.90 16.89 ^ soc/output371/Z (CLKBUF_X4_7T5P0) |
| 0.19 17.08 ^ mgmt_buffers/_131_/Z (BUF_X1_7T5P0) |
| 0.00 17.08 ^ mprj/wbs_adr_i[28] (user_project_wrapper) |
| 17.08 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[22] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20938_/ZN (NOR2_X1_7T5P0) |
| 0.80 9.58 v soc/_20939_/Z (BUF_X3_7T5P0) |
| 1.31 10.90 v soc/_20940_/Z (CLKBUF_X2_7T5P0) |
| 1.48 12.38 ^ soc/_21042_/ZN (AOI22_X1_7T5P0) |
| 1.43 13.81 ^ soc/_21043_/Z (AND2_X2_7T5P0) |
| 1.34 15.15 v soc/_21044_/ZN (INV_X8_7T5P0) |
| 0.91 16.06 v soc/output377/Z (CLKBUF_X4_7T5P0) |
| 0.22 16.28 v mgmt_buffers/_137_/Z (BUF_X1_7T5P0) |
| 0.00 16.28 v mprj/wbs_adr_i[22] (user_project_wrapper) |
| 16.28 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[24] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 0.30 12.71 v soc/_20943_/ZN (AOI22_X1_7T5P0) |
| 0.99 13.70 v soc/_20944_/Z (AND2_X2_7T5P0) |
| 1.44 15.14 ^ soc/_20945_/ZN (INV_X8_7T5P0) |
| 0.77 15.91 ^ soc/output375/Z (CLKBUF_X4_7T5P0) |
| 0.18 16.09 ^ mgmt_buffers/_135_/Z (BUF_X1_7T5P0) |
| 0.00 16.09 ^ mprj/wbs_adr_i[24] (user_project_wrapper) |
| 16.09 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[21] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 1.17 12.82 v soc/_21045_/ZN (NAND2_X1_7T5P0) |
| 0.70 13.52 ^ soc/_21047_/ZN (NAND2_X1_7T5P0) |
| 1.26 14.78 ^ soc/_21048_/Z (BUF_X8_7T5P0) |
| 0.96 15.75 ^ soc/output348/Z (CLKBUF_X4_7T5P0) |
| 0.18 15.93 ^ mgmt_buffers/_138_/Z (BUF_X1_7T5P0) |
| 0.00 15.93 ^ mprj/wbs_adr_i[21] (user_project_wrapper) |
| 15.93 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[23] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.76 12.41 ^ soc/_20841_/Z (CLKBUF_X2_7T5P0) |
| 0.33 12.74 v soc/_21038_/ZN (AOI22_X1_7T5P0) |
| 0.70 13.44 ^ soc/_21039_/ZN (NAND2_X1_7T5P0) |
| 1.33 14.77 ^ soc/_21040_/Z (BUF_X8_7T5P0) |
| 0.88 15.64 ^ soc/output376/Z (CLKBUF_X4_7T5P0) |
| 0.18 15.83 ^ mgmt_buffers/_136_/Z (BUF_X1_7T5P0) |
| 0.00 15.83 ^ mprj/wbs_adr_i[23] (user_project_wrapper) |
| 15.83 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44899_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/wbs_adr_i[25] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.10 ^ soc/_44899_/CLK (DFFQ_X1_7T5P0) |
| 1.23 8.32 ^ soc/_44899_/Q (DFFQ_X1_7T5P0) |
| 0.46 8.78 v soc/_20837_/ZN (INV_X1_7T5P0) |
| 0.76 9.54 ^ soc/_20838_/ZN (NOR2_X4_7T5P0) |
| 0.88 10.42 ^ soc/_20839_/Z (CLKBUF_X4_7T5P0) |
| 1.23 11.65 ^ soc/_20840_/Z (CLKBUF_X2_7T5P0) |
| 0.27 11.92 v soc/_20947_/ZN (AOI22_X1_7T5P0) |
| 1.03 12.95 v soc/_20948_/Z (AND2_X2_7T5P0) |
| 1.41 14.36 ^ soc/_20949_/ZN (INV_X8_7T5P0) |
| 0.76 15.13 ^ soc/output374/Z (CLKBUF_X4_7T5P0) |
| 0.18 15.31 ^ mgmt_buffers/_134_/Z (BUF_X1_7T5P0) |
| 0.00 15.31 ^ mprj/wbs_adr_i[25] (user_project_wrapper) |
| 15.31 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[8]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[10] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[8]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[8]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[27]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[8]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[10] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[7]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[11] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[7]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[7]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[26]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[7]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[11] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[6]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[12] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[6]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[6]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[25]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[6]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[12] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[5]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[13] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[5]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[5]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[24]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[5]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[13] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[4]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[14] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[4]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[4]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[23]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[4]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[14] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[3]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[15] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[3]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[3]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[22]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[3]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[15] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[2]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[16] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[2]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[2]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[21]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[2]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[16] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[1]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[17] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[1]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[1]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[20]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[1]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[17] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[0]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[18] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[0]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[0]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[19]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[0]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[18] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[10]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[19] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[10]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[10]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[18]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[10]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[19] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[9]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[20] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[9]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[9]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[17]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[9]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[20] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[8]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[21] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[8]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[8]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[16]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[8]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[21] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[7]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[22] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[7]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[7]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[15]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[7]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[22] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[6]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[23] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[6]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[6]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[14]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[6]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[23] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[5]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[24] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[5]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[5]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[13]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[5]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[24] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[4]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[25] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[4]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[4]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[12]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[4]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[25] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[3]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[26] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[3]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[3]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[11]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[3]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[26] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[2]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[27] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[2]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[2]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[10]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[2]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[27] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[1]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[28] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[1]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[1]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[9]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[1]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[28] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1[0]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[29] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1[0]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1[0]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[8]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1[0]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[29] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_bidir_2[0]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[2] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_bidir_2[0]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_bidir_2[0]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[35]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_bidir_2[0]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[2] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1a[5]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[30] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1a[5]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1a[5]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[7]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1a[5]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[30] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1a[4]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[31] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1a[4]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1a[4]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[6]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1a[4]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[31] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1a[3]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[32] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1a[3]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1a[3]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[5]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1a[3]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[32] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1a[2]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[33] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1a[2]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1a[2]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[4]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1a[2]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[33] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1a[1]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[34] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1a[1]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1a[1]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[3]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1a[1]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[34] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_1a[0]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[35] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_1a[0]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_1a[0]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[2]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_1a[0]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[35] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[15]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[3] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[15]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[15]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[34]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[15]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[3] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[14]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[4] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[14]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[14]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[33]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[14]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[4] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[13]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[5] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[13]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[13]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[32]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[13]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[5] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[12]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[6] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[12]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[12]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[31]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[12]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[6] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: gpio_control_in_2[11]/_093_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/io_in[7] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ gpio_control_in_2[11]/_093_/CLK (DFFRSNQ_X1_7T5P0) |
| 1.15 1.15 ^ gpio_control_in_2[11]/_093_/Q (DFFRSNQ_X1_7T5P0) |
| 1.51 2.67 ^ padframe/mprj_pads[30]/Y (GF_NI_BI_T) |
| 0.19 2.85 ^ gpio_control_in_2[11]/_115_/Z (BUF_X1_7T5P0) |
| 0.00 2.85 ^ mprj/io_in[7] (user_project_wrapper) |
| 2.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: housekeeping/_11272_ (rising edge-triggered flip-flop) |
| Endpoint: mprj/user_clock2 (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 ^ housekeeping/_11272_/CLK (DFFSNQ_X1_7T5P0) |
| 1.72 1.72 ^ housekeeping/_11272_/Q (DFFSNQ_X1_7T5P0) |
| 0.44 2.16 ^ housekeeping/output263/Z (CLKBUF_X4_7T5P0) |
| 0.26 2.42 ^ pll/input1/Z (BUF_X4_7T5P0) |
| 0.71 3.12 ^ pll/_485_/Z (CLKBUF_X1_7T5P0) |
| 0.61 3.74 ^ pll/_524_/Z (BUF_X1_7T5P0) |
| 0.19 3.93 v pll/_527_/ZN (NAND2_X1_7T5P0) |
| 0.40 4.33 ^ pll/_528_/ZN (NAND2_X1_7T5P0) |
| 0.39 4.72 ^ pll/ringosc.dstage[8].id.delayen0/ZN (INVZ_X1_7T5P0) |
| 0.27 4.99 ^ pll/ringosc.dstage[9].id.delaybuf0/Z (CLKBUF_X1_7T5P0) |
| 0.26 5.24 ^ pll/ringosc.dstage[9].id.delaybuf1/Z (CLKBUF_X1_7T5P0) |
| 0.62 5.87 v pll/ringosc.dstage[9].id.delayen1/ZN (INVZ_X1_7T5P0) |
| 0.05 5.92 ^ pll/ringosc.dstage[9].id.delayint0/ZN (CLKINV_X2_7T5P0) |
| 0.52 6.44 v pll/ringosc.dstage[9].id.delayen0/ZN (INVZ_X1_7T5P0) |
| 0.25 6.69 v pll/ringosc.dstage[10].id.delaybuf0/Z (CLKBUF_X1_7T5P0) |
| 0.23 6.92 v pll/ringosc.dstage[10].id.delaybuf1/Z (CLKBUF_X1_7T5P0) |
| 0.62 7.54 ^ pll/ringosc.dstage[10].id.delayen1/ZN (INVZ_X1_7T5P0) |
| 0.05 7.59 v pll/ringosc.dstage[10].id.delayint0/ZN (CLKINV_X2_7T5P0) |
| 0.56 8.14 ^ pll/ringosc.dstage[10].id.delayen0/ZN (INVZ_X1_7T5P0) |
| 0.29 8.43 ^ pll/ringosc.dstage[11].id.delaybuf0/Z (CLKBUF_X1_7T5P0) |
| 0.24 8.67 ^ pll/ringosc.dstage[11].id.delaybuf1/Z (CLKBUF_X1_7T5P0) |
| 0.57 9.24 v pll/ringosc.dstage[11].id.delayen1/ZN (INVZ_X1_7T5P0) |
| 0.05 9.29 ^ pll/ringosc.dstage[11].id.delayint0/ZN (CLKINV_X2_7T5P0) |
| 0.46 9.75 v pll/ringosc.dstage[11].id.delayen0/ZN (INVZ_X2_7T5P0) |
| 0.18 9.92 v pll/ringosc.iss.delaybuf0/Z (CLKBUF_X1_7T5P0) |
| 0.59 10.51 ^ pll/ringosc.iss.delayen1/ZN (INVZ_X1_7T5P0) |
| 0.12 10.64 v pll/ringosc.iss.delayint0/ZN (CLKINV_X1_7T5P0) |
| 0.52 11.15 ^ pll/ringosc.iss.delayen0/ZN (INVZ_X2_7T5P0) |
| 0.20 11.35 v pll/ringosc.ibufp00/ZN (CLKINV_X2_7T5P0) |
| 0.33 11.68 ^ pll/ringosc.ibufp01/ZN (CLKINV_X8_7T5P0) |
| 0.33 12.01 ^ pll/_686_/Z (CLKBUF_X1_7T5P0) |
| 0.27 12.27 ^ pll/output36/Z (CLKBUF_X4_7T5P0) |
| 0.84 13.11 ^ clock_ctrl/input4/Z (BUF_X3_7T5P0) |
| 0.38 13.49 v clock_ctrl/_238_/ZN (NOR3_X1_7T5P0) |
| 0.63 14.12 ^ clock_ctrl/_241_/ZN (OAI32_X1_7T5P0) |
| 0.47 14.59 ^ clock_ctrl/_242_/Z (BUF_X2_7T5P0) |
| 0.32 14.91 ^ clock_ctrl/_243_/Z (MUX2_X2_7T5P0) |
| 0.21 15.12 ^ clock_ctrl/_244_/Z (BUF_X2_7T5P0) |
| 0.27 15.39 ^ clock_ctrl/output14/Z (BUF_X1_7T5P0) |
| 0.19 15.58 ^ mgmt_buffers/_200_/Z (BUF_X1_7T5P0) |
| 0.00 15.58 ^ mprj/user_clock2 (user_project_wrapper) |
| 15.58 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| No paths found. |
| Startpoint: soc/_42857_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[29] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.14 ^ soc/_42857_/CLK (DFFQ_X1_7T5P0) |
| 3.68 10.82 ^ soc/_42857_/Q (DFFQ_X1_7T5P0) |
| 0.63 11.45 v soc/_24246_/ZN (CLKINV_X1_7T5P0) |
| 0.47 11.92 v soc/output247/Z (CLKBUF_X4_7T5P0) |
| 0.21 12.14 ^ mgmt_buffers/_009_/ZN (INV_X1_7T5P0) |
| 0.23 12.36 ^ mgmt_buffers/la_buf[34]/Z (BUFZ_X8_7T5P0) |
| 0.00 12.36 ^ mprj/la_data_in[29] (user_project_wrapper) |
| 12.36 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42860_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[26] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.04 ^ soc/_42860_/CLK (DFFQ_X1_7T5P0) |
| 3.76 10.80 ^ soc/_42860_/Q (DFFQ_X1_7T5P0) |
| 0.45 11.25 v soc/_24243_/ZN (CLKINV_X1_7T5P0) |
| 0.45 11.70 v soc/output250/Z (CLKBUF_X4_7T5P0) |
| 0.19 11.88 ^ mgmt_buffers/_012_/ZN (INV_X1_7T5P0) |
| 0.22 12.10 ^ mgmt_buffers/la_buf[37]/Z (BUFZ_X8_7T5P0) |
| 0.00 12.10 ^ mprj/la_data_in[26] (user_project_wrapper) |
| 12.10 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42861_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[25] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_42861_/CLK (DFFQ_X1_7T5P0) |
| 3.81 10.94 ^ soc/_42861_/Q (DFFQ_X1_7T5P0) |
| 0.30 11.24 v soc/_24242_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.66 v soc/output251/Z (CLKBUF_X4_7T5P0) |
| 0.20 11.86 ^ mgmt_buffers/_013_/ZN (INV_X1_7T5P0) |
| 0.22 12.08 ^ mgmt_buffers/la_buf[38]/Z (BUFZ_X8_7T5P0) |
| 0.00 12.08 ^ mprj/la_data_in[25] (user_project_wrapper) |
| 12.08 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42871_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[15] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_42871_/CLK (DFFQ_X1_7T5P0) |
| 3.56 10.44 ^ soc/_42871_/Q (DFFQ_X1_7T5P0) |
| 0.41 10.85 v soc/_24232_/ZN (CLKINV_X1_7T5P0) |
| 0.44 11.29 v soc/output262/Z (CLKBUF_X4_7T5P0) |
| 0.50 11.79 ^ mgmt_buffers/_023_/ZN (INV_X1_7T5P0) |
| 0.25 12.03 ^ mgmt_buffers/la_buf[48]/Z (BUFZ_X8_7T5P0) |
| 0.00 12.03 ^ mprj/la_data_in[15] (user_project_wrapper) |
| 12.03 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42864_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[22] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42864_/CLK (DFFQ_X1_7T5P0) |
| 3.75 10.65 ^ soc/_42864_/Q (DFFQ_X1_7T5P0) |
| 0.41 11.05 v soc/_24239_/ZN (CLKINV_X1_7T5P0) |
| 0.44 11.50 v soc/output255/Z (CLKBUF_X4_7T5P0) |
| 0.25 11.75 ^ mgmt_buffers/_016_/ZN (INV_X1_7T5P0) |
| 0.24 11.98 ^ mgmt_buffers/la_buf[41]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.98 ^ mprj/la_data_in[22] (user_project_wrapper) |
| 11.98 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42855_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[31] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.04 ^ soc/_42855_/CLK (DFFQ_X1_7T5P0) |
| 3.43 10.47 ^ soc/_42855_/Q (DFFQ_X1_7T5P0) |
| 0.66 11.12 v soc/_24248_/ZN (CLKINV_X1_7T5P0) |
| 0.47 11.60 v soc/output245/Z (CLKBUF_X4_7T5P0) |
| 0.17 11.76 ^ mgmt_buffers/_007_/ZN (INV_X1_7T5P0) |
| 0.22 11.98 ^ mgmt_buffers/la_buf[32]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.98 ^ mprj/la_data_in[31] (user_project_wrapper) |
| 11.98 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42870_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[16] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42870_/CLK (DFFQ_X1_7T5P0) |
| 3.66 10.56 ^ soc/_42870_/Q (DFFQ_X1_7T5P0) |
| 0.34 10.89 v soc/_24233_/ZN (CLKINV_X1_7T5P0) |
| 0.43 11.32 v soc/output261/Z (CLKBUF_X4_7T5P0) |
| 0.38 11.70 ^ mgmt_buffers/_022_/ZN (INV_X1_7T5P0) |
| 0.25 11.95 ^ mgmt_buffers/la_buf[47]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.95 ^ mprj/la_data_in[16] (user_project_wrapper) |
| 11.95 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42885_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[1] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42885_/CLK (DFFQ_X1_7T5P0) |
| 3.46 10.34 ^ soc/_42885_/Q (DFFQ_X1_7T5P0) |
| 0.63 10.98 v soc/_24218_/ZN (CLKINV_X1_7T5P0) |
| 0.47 11.45 v soc/output278/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.67 ^ mgmt_buffers/_037_/ZN (INV_X1_7T5P0) |
| 0.23 11.90 ^ mgmt_buffers/la_buf[62]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.90 ^ mprj/la_data_in[1] (user_project_wrapper) |
| 11.90 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42856_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[30] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.07 ^ soc/_42856_/CLK (DFFQ_X1_7T5P0) |
| 3.34 10.41 ^ soc/_42856_/Q (DFFQ_X1_7T5P0) |
| 0.55 10.95 v soc/_24247_/ZN (CLKINV_X1_7T5P0) |
| 0.45 11.40 v soc/output246/Z (CLKBUF_X4_7T5P0) |
| 0.21 11.61 ^ mgmt_buffers/_008_/ZN (INV_X1_7T5P0) |
| 0.23 11.84 ^ mgmt_buffers/la_buf[33]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.84 ^ mprj/la_data_in[30] (user_project_wrapper) |
| 11.84 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42866_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[20] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42866_/CLK (DFFQ_X1_7T5P0) |
| 3.67 10.58 ^ soc/_42866_/Q (DFFQ_X1_7T5P0) |
| 0.32 10.90 v soc/_24237_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.32 v soc/output257/Z (CLKBUF_X4_7T5P0) |
| 0.24 11.56 ^ mgmt_buffers/_018_/ZN (INV_X1_7T5P0) |
| 0.23 11.80 ^ mgmt_buffers/la_buf[43]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.80 ^ mprj/la_data_in[20] (user_project_wrapper) |
| 11.80 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42883_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[3] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42883_/CLK (DFFQ_X1_7T5P0) |
| 3.37 10.29 ^ soc/_42883_/Q (DFFQ_X1_7T5P0) |
| 0.65 10.94 v soc/_24220_/ZN (CLKINV_X1_7T5P0) |
| 0.47 11.41 v soc/output276/Z (CLKBUF_X4_7T5P0) |
| 0.17 11.58 ^ mgmt_buffers/_035_/ZN (INV_X1_7T5P0) |
| 0.22 11.79 ^ mgmt_buffers/la_buf[60]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.79 ^ mprj/la_data_in[3] (user_project_wrapper) |
| 11.79 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42868_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[18] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42868_/CLK (DFFQ_X1_7T5P0) |
| 3.41 10.31 ^ soc/_42868_/Q (DFFQ_X1_7T5P0) |
| 0.31 10.62 v soc/_24235_/ZN (CLKINV_X1_7T5P0) |
| 0.41 11.03 v soc/output259/Z (CLKBUF_X4_7T5P0) |
| 0.45 11.48 ^ mgmt_buffers/_020_/ZN (INV_X1_7T5P0) |
| 0.25 11.73 ^ mgmt_buffers/la_buf[45]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.73 ^ mprj/la_data_in[18] (user_project_wrapper) |
| 11.73 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42872_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[14] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42872_/CLK (DFFQ_X1_7T5P0) |
| 3.19 10.10 ^ soc/_42872_/Q (DFFQ_X1_7T5P0) |
| 0.50 10.60 v soc/_24231_/ZN (CLKINV_X1_7T5P0) |
| 0.44 11.04 v soc/output263/Z (CLKBUF_X4_7T5P0) |
| 0.44 11.48 ^ mgmt_buffers/_024_/ZN (INV_X1_7T5P0) |
| 0.25 11.73 ^ mgmt_buffers/la_buf[49]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.73 ^ mprj/la_data_in[14] (user_project_wrapper) |
| 11.73 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42863_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[23] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42863_/CLK (DFFQ_X1_7T5P0) |
| 3.61 10.51 ^ soc/_42863_/Q (DFFQ_X1_7T5P0) |
| 0.33 10.84 v soc/_24240_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.26 v soc/output254/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.49 ^ mgmt_buffers/_015_/ZN (INV_X1_7T5P0) |
| 0.23 11.72 ^ mgmt_buffers/la_buf[40]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.72 ^ mprj/la_data_in[23] (user_project_wrapper) |
| 11.72 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42862_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[24] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_42862_/CLK (DFFQ_X1_7T5P0) |
| 3.45 10.58 ^ soc/_42862_/Q (DFFQ_X1_7T5P0) |
| 0.33 10.91 v soc/_24241_/ZN (CLKINV_X1_7T5P0) |
| 0.41 11.32 v soc/output252/Z (CLKBUF_X4_7T5P0) |
| 0.17 11.50 ^ mgmt_buffers/_014_/ZN (INV_X1_7T5P0) |
| 0.22 11.71 ^ mgmt_buffers/la_buf[39]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.71 ^ mprj/la_data_in[24] (user_project_wrapper) |
| 11.71 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42859_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[27] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_42859_/CLK (DFFQ_X1_7T5P0) |
| 3.32 10.45 ^ soc/_42859_/Q (DFFQ_X1_7T5P0) |
| 0.37 10.82 v soc/_24244_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.24 v soc/output249/Z (CLKBUF_X4_7T5P0) |
| 0.19 11.43 ^ mgmt_buffers/_011_/ZN (INV_X1_7T5P0) |
| 0.22 11.66 ^ mgmt_buffers/la_buf[36]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.66 ^ mprj/la_data_in[27] (user_project_wrapper) |
| 11.66 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42858_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[28] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_42858_/CLK (DFFQ_X1_7T5P0) |
| 3.24 10.36 ^ soc/_42858_/Q (DFFQ_X1_7T5P0) |
| 0.42 10.78 v soc/_24245_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.20 v soc/output248/Z (CLKBUF_X4_7T5P0) |
| 0.20 11.40 ^ mgmt_buffers/_010_/ZN (INV_X1_7T5P0) |
| 0.22 11.62 ^ mgmt_buffers/la_buf[35]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.62 ^ mprj/la_data_in[28] (user_project_wrapper) |
| 11.62 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42869_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[17] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42869_/CLK (DFFQ_X1_7T5P0) |
| 3.27 10.17 ^ soc/_42869_/Q (DFFQ_X1_7T5P0) |
| 0.35 10.52 v soc/_24234_/ZN (CLKINV_X1_7T5P0) |
| 0.42 10.93 v soc/output260/Z (CLKBUF_X4_7T5P0) |
| 0.44 11.37 ^ mgmt_buffers/_021_/ZN (INV_X1_7T5P0) |
| 0.25 11.62 ^ mgmt_buffers/la_buf[46]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.62 ^ mprj/la_data_in[17] (user_project_wrapper) |
| 11.62 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42865_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[21] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42865_/CLK (DFFQ_X1_7T5P0) |
| 3.35 10.25 ^ soc/_42865_/Q (DFFQ_X1_7T5P0) |
| 0.43 10.69 v soc/_24238_/ZN (CLKINV_X1_7T5P0) |
| 0.43 11.12 v soc/output256/Z (CLKBUF_X4_7T5P0) |
| 0.26 11.38 ^ mgmt_buffers/_017_/ZN (INV_X1_7T5P0) |
| 0.24 11.61 ^ mgmt_buffers/la_buf[42]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.61 ^ mprj/la_data_in[21] (user_project_wrapper) |
| 11.61 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42886_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[0] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42886_/CLK (DFFQ_X1_7T5P0) |
| 3.26 10.14 ^ soc/_42886_/Q (DFFQ_X1_7T5P0) |
| 0.43 10.57 v soc/_24217_/ZN (CLKINV_X1_7T5P0) |
| 0.43 11.00 v soc/output279/Z (CLKBUF_X4_7T5P0) |
| 0.21 11.22 ^ mgmt_buffers/_038_/ZN (INV_X1_7T5P0) |
| 0.23 11.44 ^ mgmt_buffers/la_buf[63]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.44 ^ mprj/la_data_in[0] (user_project_wrapper) |
| 11.44 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42880_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[6] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42880_/CLK (DFFQ_X1_7T5P0) |
| 3.22 10.13 ^ soc/_42880_/Q (DFFQ_X1_7T5P0) |
| 0.45 10.59 v soc/_24223_/ZN (CLKINV_X1_7T5P0) |
| 0.43 11.02 v soc/output272/Z (CLKBUF_X4_7T5P0) |
| 0.18 11.20 ^ mgmt_buffers/_032_/ZN (INV_X1_7T5P0) |
| 0.22 11.42 ^ mgmt_buffers/la_buf[57]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.42 ^ mprj/la_data_in[6] (user_project_wrapper) |
| 11.42 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42867_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[19] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42867_/CLK (DFFQ_X1_7T5P0) |
| 3.26 10.16 ^ soc/_42867_/Q (DFFQ_X1_7T5P0) |
| 0.31 10.47 v soc/_24236_/ZN (CLKINV_X1_7T5P0) |
| 0.41 10.88 v soc/output258/Z (CLKBUF_X4_7T5P0) |
| 0.26 11.14 ^ mgmt_buffers/_019_/ZN (INV_X1_7T5P0) |
| 0.24 11.38 ^ mgmt_buffers/la_buf[44]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.38 ^ mprj/la_data_in[19] (user_project_wrapper) |
| 11.38 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42875_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[11] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42875_/CLK (DFFQ_X1_7T5P0) |
| 2.80 9.70 ^ soc/_42875_/Q (DFFQ_X1_7T5P0) |
| 0.58 10.27 v soc/_24228_/ZN (CLKINV_X1_7T5P0) |
| 0.44 10.71 v soc/output267/Z (CLKBUF_X4_7T5P0) |
| 0.35 11.07 ^ mgmt_buffers/_027_/ZN (INV_X1_7T5P0) |
| 0.24 11.31 ^ mgmt_buffers/la_buf[52]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.31 ^ mprj/la_data_in[11] (user_project_wrapper) |
| 11.31 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42884_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[2] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42884_/CLK (DFFQ_X1_7T5P0) |
| 2.87 9.78 ^ soc/_42884_/Q (DFFQ_X1_7T5P0) |
| 0.64 10.42 v soc/_24219_/ZN (CLKINV_X1_7T5P0) |
| 0.45 10.88 v soc/output277/Z (CLKBUF_X4_7T5P0) |
| 0.16 11.04 ^ mgmt_buffers/_036_/ZN (INV_X1_7T5P0) |
| 0.22 11.26 ^ mgmt_buffers/la_buf[61]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.26 ^ mprj/la_data_in[2] (user_project_wrapper) |
| 11.26 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42879_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[7] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42879_/CLK (DFFQ_X1_7T5P0) |
| 2.94 9.85 ^ soc/_42879_/Q (DFFQ_X1_7T5P0) |
| 0.54 10.39 v soc/_24224_/ZN (CLKINV_X1_7T5P0) |
| 0.44 10.83 v soc/output271/Z (CLKBUF_X4_7T5P0) |
| 0.20 11.03 ^ mgmt_buffers/_031_/ZN (INV_X1_7T5P0) |
| 0.22 11.25 ^ mgmt_buffers/la_buf[56]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.25 ^ mprj/la_data_in[7] (user_project_wrapper) |
| 11.25 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42877_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[9] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42877_/CLK (DFFQ_X1_7T5P0) |
| 2.90 9.80 ^ soc/_42877_/Q (DFFQ_X1_7T5P0) |
| 0.30 10.10 v soc/_24226_/ZN (CLKINV_X1_7T5P0) |
| 0.39 10.49 v soc/output269/Z (CLKBUF_X4_7T5P0) |
| 0.35 10.84 ^ mgmt_buffers/_029_/ZN (INV_X1_7T5P0) |
| 0.24 11.09 ^ mgmt_buffers/la_buf[54]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.09 ^ mprj/la_data_in[9] (user_project_wrapper) |
| 11.09 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42878_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[8] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42878_/CLK (DFFQ_X1_7T5P0) |
| 2.88 9.78 ^ soc/_42878_/Q (DFFQ_X1_7T5P0) |
| 0.29 10.07 v soc/_24225_/ZN (CLKINV_X1_7T5P0) |
| 0.39 10.46 v soc/output270/Z (CLKBUF_X4_7T5P0) |
| 0.34 10.80 ^ mgmt_buffers/_030_/ZN (INV_X1_7T5P0) |
| 0.24 11.04 ^ mgmt_buffers/la_buf[55]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.04 ^ mprj/la_data_in[8] (user_project_wrapper) |
| 11.04 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42881_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[5] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42881_/CLK (DFFQ_X1_7T5P0) |
| 2.90 9.79 ^ soc/_42881_/Q (DFFQ_X1_7T5P0) |
| 0.43 10.22 v soc/_24222_/ZN (CLKINV_X1_7T5P0) |
| 0.42 10.63 v soc/output273/Z (CLKBUF_X4_7T5P0) |
| 0.17 10.80 ^ mgmt_buffers/_033_/ZN (INV_X1_7T5P0) |
| 0.22 11.02 ^ mgmt_buffers/la_buf[58]/Z (BUFZ_X8_7T5P0) |
| 0.00 11.02 ^ mprj/la_data_in[5] (user_project_wrapper) |
| 11.02 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42882_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[4] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42882_/CLK (DFFQ_X1_7T5P0) |
| 2.83 9.74 ^ soc/_42882_/Q (DFFQ_X1_7T5P0) |
| 0.40 10.14 v soc/_24221_/ZN (CLKINV_X1_7T5P0) |
| 0.41 10.55 v soc/output274/Z (CLKBUF_X4_7T5P0) |
| 0.16 10.71 ^ mgmt_buffers/_034_/ZN (INV_X1_7T5P0) |
| 0.22 10.93 ^ mgmt_buffers/la_buf[59]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.93 ^ mprj/la_data_in[4] (user_project_wrapper) |
| 10.93 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45001_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[63] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.05 ^ soc/_45001_/CLK (DFFQ_X1_7T5P0) |
| 1.95 9.00 ^ soc/_45001_/Q (DFFQ_X1_7T5P0) |
| 0.26 9.26 v soc/_24280_/ZN (CLKINV_X1_7T5P0) |
| 0.35 9.61 v soc/output220/Z (CLKBUF_X4_7T5P0) |
| 1.09 10.70 ^ mgmt_buffers/_039_/ZN (INV_X1_7T5P0) |
| 0.22 10.92 v mgmt_buffers/la_buf[0]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.92 v mprj/la_data_in[63] (user_project_wrapper) |
| 10.92 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42874_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[12] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_42874_/CLK (DFFQ_X1_7T5P0) |
| 2.52 9.40 ^ soc/_42874_/Q (DFFQ_X1_7T5P0) |
| 0.49 9.89 v soc/_24229_/ZN (CLKINV_X1_7T5P0) |
| 0.42 10.31 v soc/output266/Z (CLKBUF_X4_7T5P0) |
| 0.35 10.65 ^ mgmt_buffers/_026_/ZN (INV_X1_7T5P0) |
| 0.24 10.90 ^ mgmt_buffers/la_buf[51]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.90 ^ mprj/la_data_in[12] (user_project_wrapper) |
| 10.90 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45002_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[62] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.05 ^ soc/_45002_/CLK (DFFQ_X1_7T5P0) |
| 2.06 9.11 ^ soc/_45002_/Q (DFFQ_X1_7T5P0) |
| 0.35 9.45 v soc/_24279_/ZN (CLKINV_X1_7T5P0) |
| 0.37 9.83 v soc/output231/Z (CLKBUF_X4_7T5P0) |
| 0.77 10.60 ^ mgmt_buffers/_040_/ZN (INV_X1_7T5P0) |
| 0.24 10.84 v mgmt_buffers/la_buf[1]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.84 v mprj/la_data_in[62] (user_project_wrapper) |
| 10.84 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45008_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[56] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_45008_/CLK (DFFQ_X1_7T5P0) |
| 1.88 8.78 ^ soc/_45008_/Q (DFFQ_X1_7T5P0) |
| 0.37 9.15 v soc/_24273_/ZN (CLKINV_X1_7T5P0) |
| 0.37 9.52 v soc/output281/Z (CLKBUF_X4_7T5P0) |
| 1.09 10.61 ^ mgmt_buffers/_046_/ZN (INV_X1_7T5P0) |
| 0.22 10.83 v mgmt_buffers/la_buf[7]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.83 v mprj/la_data_in[56] (user_project_wrapper) |
| 10.83 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45005_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[59] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_45005_/CLK (DFFQ_X1_7T5P0) |
| 1.83 8.74 ^ soc/_45005_/Q (DFFQ_X1_7T5P0) |
| 0.52 9.26 v soc/_24276_/ZN (CLKINV_X1_7T5P0) |
| 0.40 9.65 v soc/output264/Z (CLKBUF_X4_7T5P0) |
| 0.85 10.50 ^ mgmt_buffers/_043_/ZN (INV_X1_7T5P0) |
| 0.24 10.74 v mgmt_buffers/la_buf[4]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.74 v mprj/la_data_in[59] (user_project_wrapper) |
| 10.74 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45003_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[61] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_45003_/CLK (DFFQ_X1_7T5P0) |
| 1.16 8.05 ^ soc/_45003_/Q (DFFQ_X1_7T5P0) |
| 0.98 9.02 v soc/_24278_/ZN (CLKINV_X1_7T5P0) |
| 0.49 9.51 v soc/output242/Z (CLKBUF_X4_7T5P0) |
| 0.88 10.39 ^ mgmt_buffers/_041_/ZN (INV_X1_7T5P0) |
| 0.24 10.62 v mgmt_buffers/la_buf[2]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.62 v mprj/la_data_in[61] (user_project_wrapper) |
| 10.62 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45023_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[41] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45023_/CLK (DFFQ_X1_7T5P0) |
| 1.68 8.63 ^ soc/_45023_/Q (DFFQ_X1_7T5P0) |
| 0.32 8.95 v soc/_24258_/ZN (CLKINV_X1_7T5P0) |
| 0.35 9.30 v soc/output234/Z (CLKBUF_X4_7T5P0) |
| 1.05 10.35 ^ mgmt_buffers/_061_/ZN (INV_X1_7T5P0) |
| 0.22 10.57 v mgmt_buffers/la_buf[22]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.57 v mprj/la_data_in[41] (user_project_wrapper) |
| 10.57 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45004_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[60] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_45004_/CLK (DFFQ_X1_7T5P0) |
| 1.90 8.79 ^ soc/_45004_/Q (DFFQ_X1_7T5P0) |
| 0.41 9.20 v soc/_24277_/ZN (CLKINV_X1_7T5P0) |
| 0.38 9.58 v soc/output253/Z (CLKBUF_X4_7T5P0) |
| 0.70 10.28 ^ mgmt_buffers/_042_/ZN (INV_X1_7T5P0) |
| 0.24 10.52 v mgmt_buffers/la_buf[3]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.52 v mprj/la_data_in[60] (user_project_wrapper) |
| 10.52 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42876_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[10] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42876_/CLK (DFFQ_X1_7T5P0) |
| 2.19 9.09 ^ soc/_42876_/Q (DFFQ_X1_7T5P0) |
| 0.42 9.51 v soc/_24227_/ZN (CLKINV_X1_7T5P0) |
| 0.39 9.90 v soc/output268/Z (CLKBUF_X4_7T5P0) |
| 0.35 10.25 ^ mgmt_buffers/_028_/ZN (INV_X1_7T5P0) |
| 0.24 10.50 ^ mgmt_buffers/la_buf[53]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.50 ^ mprj/la_data_in[10] (user_project_wrapper) |
| 10.50 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42873_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[13] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42873_/CLK (DFFQ_X1_7T5P0) |
| 2.03 8.93 ^ soc/_42873_/Q (DFFQ_X1_7T5P0) |
| 0.44 9.36 v soc/_24230_/ZN (CLKINV_X1_7T5P0) |
| 0.39 9.75 v soc/output265/Z (CLKBUF_X4_7T5P0) |
| 0.39 10.14 ^ mgmt_buffers/_025_/ZN (INV_X1_7T5P0) |
| 0.25 10.39 ^ mgmt_buffers/la_buf[50]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.39 ^ mprj/la_data_in[13] (user_project_wrapper) |
| 10.39 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44990_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[42] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.04 ^ soc/_44990_/CLK (DFFQ_X1_7T5P0) |
| 2.41 9.45 ^ soc/_44990_/Q (DFFQ_X1_7T5P0) |
| 0.60 10.05 ^ soc/output297/Z (CLKBUF_X4_7T5P0) |
| 0.25 10.30 ^ mgmt_buffers/la_buf[21]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.30 ^ mprj/la_data_in[42] (user_project_wrapper) |
| 10.30 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45024_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[40] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45024_/CLK (DFFQ_X1_7T5P0) |
| 1.64 8.59 ^ soc/_45024_/Q (DFFQ_X1_7T5P0) |
| 0.28 8.87 v soc/_24257_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.21 v soc/output235/Z (CLKBUF_X4_7T5P0) |
| 0.84 10.05 ^ mgmt_buffers/_062_/ZN (INV_X1_7T5P0) |
| 0.24 10.29 v mgmt_buffers/la_buf[23]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.29 v mprj/la_data_in[40] (user_project_wrapper) |
| 10.29 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45025_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[39] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_45025_/CLK (DFFQ_X1_7T5P0) |
| 1.57 8.47 ^ soc/_45025_/Q (DFFQ_X1_7T5P0) |
| 0.34 8.81 v soc/_24256_/ZN (CLKINV_X1_7T5P0) |
| 0.35 9.15 v soc/output236/Z (CLKBUF_X4_7T5P0) |
| 0.88 10.03 ^ mgmt_buffers/_063_/ZN (INV_X1_7T5P0) |
| 0.24 10.26 v mgmt_buffers/la_buf[24]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.26 v mprj/la_data_in[39] (user_project_wrapper) |
| 10.26 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45007_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[57] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_45007_/CLK (DFFQ_X1_7T5P0) |
| 1.04 7.93 ^ soc/_45007_/Q (DFFQ_X1_7T5P0) |
| 0.58 8.51 v soc/_24274_/ZN (CLKINV_X1_7T5P0) |
| 0.40 8.91 v soc/output280/Z (CLKBUF_X4_7T5P0) |
| 1.11 10.01 ^ mgmt_buffers/_045_/ZN (INV_X1_7T5P0) |
| 0.22 10.23 v mgmt_buffers/la_buf[6]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.23 v mprj/la_data_in[57] (user_project_wrapper) |
| 10.23 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45026_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[38] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45026_/CLK (DFFQ_X1_7T5P0) |
| 1.48 8.42 ^ soc/_45026_/Q (DFFQ_X1_7T5P0) |
| 0.35 8.77 v soc/_24255_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.11 v soc/output237/Z (CLKBUF_X4_7T5P0) |
| 0.84 9.94 ^ mgmt_buffers/_000_/ZN (INV_X1_7T5P0) |
| 0.24 10.18 v mgmt_buffers/la_buf[25]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.18 v mprj/la_data_in[38] (user_project_wrapper) |
| 10.18 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45021_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[43] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45021_/CLK (DFFQ_X1_7T5P0) |
| 1.80 8.75 ^ soc/_45021_/Q (DFFQ_X1_7T5P0) |
| 0.35 9.10 v soc/_24260_/ZN (CLKINV_X1_7T5P0) |
| 0.36 9.46 v soc/output232/Z (CLKBUF_X4_7T5P0) |
| 0.45 9.92 ^ mgmt_buffers/_059_/ZN (INV_X1_7T5P0) |
| 0.25 10.16 ^ mgmt_buffers/la_buf[20]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.16 ^ mprj/la_data_in[43] (user_project_wrapper) |
| 10.16 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45029_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[35] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45029_/CLK (DFFQ_X1_7T5P0) |
| 1.78 8.72 ^ soc/_45029_/Q (DFFQ_X1_7T5P0) |
| 0.27 8.99 v soc/_24252_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.32 v soc/output240/Z (CLKBUF_X4_7T5P0) |
| 0.58 9.90 ^ mgmt_buffers/_003_/ZN (INV_X1_7T5P0) |
| 0.25 10.15 v mgmt_buffers/la_buf[28]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.15 v mprj/la_data_in[35] (user_project_wrapper) |
| 10.15 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45006_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[58] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_45006_/CLK (DFFQ_X1_7T5P0) |
| 0.98 7.88 ^ soc/_45006_/Q (DFFQ_X1_7T5P0) |
| 0.63 8.50 v soc/_24275_/ZN (CLKINV_X1_7T5P0) |
| 0.42 8.92 v soc/output275/Z (CLKBUF_X4_7T5P0) |
| 0.99 9.91 ^ mgmt_buffers/_044_/ZN (INV_X1_7T5P0) |
| 0.23 10.14 v mgmt_buffers/la_buf[5]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.14 v mprj/la_data_in[58] (user_project_wrapper) |
| 10.14 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44995_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[37] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.04 ^ soc/_44995_/CLK (DFFQ_X1_7T5P0) |
| 2.25 9.29 ^ soc/_44995_/Q (DFFQ_X1_7T5P0) |
| 0.58 9.87 ^ soc/output302/Z (CLKBUF_X4_7T5P0) |
| 0.25 10.13 ^ mgmt_buffers/la_buf[26]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.13 ^ mprj/la_data_in[37] (user_project_wrapper) |
| 10.13 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44987_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[45] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.03 ^ soc/_44987_/CLK (DFFQ_X1_7T5P0) |
| 2.23 9.26 ^ soc/_44987_/Q (DFFQ_X1_7T5P0) |
| 0.58 9.83 ^ soc/output293/Z (CLKBUF_X4_7T5P0) |
| 0.25 10.09 ^ mgmt_buffers/la_buf[18]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.09 ^ mprj/la_data_in[45] (user_project_wrapper) |
| 10.09 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44988_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[44] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.03 ^ soc/_44988_/CLK (DFFQ_X1_7T5P0) |
| 2.17 9.20 ^ soc/_44988_/Q (DFFQ_X1_7T5P0) |
| 0.57 9.77 ^ soc/output294/Z (CLKBUF_X4_7T5P0) |
| 0.25 10.02 ^ mgmt_buffers/la_buf[19]/Z (BUFZ_X8_7T5P0) |
| 0.00 10.02 ^ mprj/la_data_in[44] (user_project_wrapper) |
| 10.02 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45000_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[32] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_45000_/CLK (DFFQ_X1_7T5P0) |
| 1.95 9.08 ^ soc/_45000_/Q (DFFQ_X1_7T5P0) |
| 0.54 9.62 ^ soc/output308/Z (CLKBUF_X4_7T5P0) |
| 0.25 9.88 ^ mgmt_buffers/la_buf[31]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.88 ^ mprj/la_data_in[32] (user_project_wrapper) |
| 9.88 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_44998_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[34] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_44998_/CLK (DFFQ_X1_7T5P0) |
| 1.95 9.08 ^ soc/_44998_/Q (DFFQ_X1_7T5P0) |
| 0.54 9.62 ^ soc/output305/Z (CLKBUF_X4_7T5P0) |
| 0.25 9.87 ^ mgmt_buffers/la_buf[29]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.87 ^ mprj/la_data_in[34] (user_project_wrapper) |
| 9.87 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45018_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[46] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_45018_/CLK (DFFQ_X1_7T5P0) |
| 1.63 8.52 ^ soc/_45018_/Q (DFFQ_X1_7T5P0) |
| 0.48 9.00 v soc/_24263_/ZN (CLKINV_X1_7T5P0) |
| 0.38 9.38 v soc/output228/Z (CLKBUF_X4_7T5P0) |
| 0.23 9.61 ^ mgmt_buffers/_056_/ZN (INV_X1_7T5P0) |
| 0.23 9.84 ^ mgmt_buffers/la_buf[17]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.84 ^ mprj/la_data_in[46] (user_project_wrapper) |
| 9.84 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45028_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[36] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45028_/CLK (DFFQ_X1_7T5P0) |
| 1.31 8.26 ^ soc/_45028_/Q (DFFQ_X1_7T5P0) |
| 0.28 8.53 v soc/_24253_/ZN (CLKINV_X1_7T5P0) |
| 0.32 8.85 v soc/output239/Z (CLKBUF_X4_7T5P0) |
| 0.68 9.53 ^ mgmt_buffers/_002_/ZN (INV_X1_7T5P0) |
| 0.25 9.78 v mgmt_buffers/la_buf[27]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.78 v mprj/la_data_in[36] (user_project_wrapper) |
| 9.78 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45031_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[33] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45031_/CLK (DFFQ_X1_7T5P0) |
| 1.25 8.19 ^ soc/_45031_/Q (DFFQ_X1_7T5P0) |
| 0.24 8.43 v soc/_24250_/ZN (CLKINV_X1_7T5P0) |
| 0.31 8.74 v soc/output243/Z (CLKBUF_X4_7T5P0) |
| 0.76 9.50 ^ mgmt_buffers/_005_/ZN (INV_X1_7T5P0) |
| 0.24 9.74 v mgmt_buffers/la_buf[30]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.74 v mprj/la_data_in[33] (user_project_wrapper) |
| 9.74 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45010_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[54] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45010_/CLK (DFFQ_X1_7T5P0) |
| 1.04 8.02 ^ soc/_45010_/Q (DFFQ_X1_7T5P0) |
| 0.20 8.21 v soc/_24271_/ZN (CLKINV_X1_7T5P0) |
| 0.28 8.50 v soc/output283/Z (CLKBUF_X4_7T5P0) |
| 0.98 9.48 ^ mgmt_buffers/_048_/ZN (INV_X1_7T5P0) |
| 0.23 9.70 v mgmt_buffers/la_buf[9]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.70 v mprj/la_data_in[54] (user_project_wrapper) |
| 9.70 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45009_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[55] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45009_/CLK (DFFQ_X1_7T5P0) |
| 1.04 8.01 ^ soc/_45009_/Q (DFFQ_X1_7T5P0) |
| 0.21 8.23 v soc/_24272_/ZN (CLKINV_X1_7T5P0) |
| 0.29 8.52 v soc/output282/Z (CLKBUF_X4_7T5P0) |
| 0.90 9.42 ^ mgmt_buffers/_047_/ZN (INV_X1_7T5P0) |
| 0.23 9.65 v mgmt_buffers/la_buf[8]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.65 v mprj/la_data_in[55] (user_project_wrapper) |
| 9.65 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45012_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[52] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45012_/CLK (DFFQ_X1_7T5P0) |
| 0.97 7.95 ^ soc/_45012_/Q (DFFQ_X1_7T5P0) |
| 0.29 8.24 v soc/_24269_/ZN (CLKINV_X1_7T5P0) |
| 0.31 8.55 v soc/output222/Z (CLKBUF_X4_7T5P0) |
| 0.77 9.32 ^ mgmt_buffers/_050_/ZN (INV_X1_7T5P0) |
| 0.24 9.56 v mgmt_buffers/la_buf[11]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.56 v mprj/la_data_in[52] (user_project_wrapper) |
| 9.56 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45017_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[47] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.95 ^ soc/_45017_/CLK (DFFQ_X1_7T5P0) |
| 1.53 8.48 ^ soc/_45017_/Q (DFFQ_X1_7T5P0) |
| 0.34 8.82 v soc/_24264_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.16 v soc/output227/Z (CLKBUF_X4_7T5P0) |
| 0.16 9.32 ^ mgmt_buffers/_055_/ZN (INV_X1_7T5P0) |
| 0.22 9.54 ^ mgmt_buffers/la_buf[16]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.54 ^ mprj/la_data_in[47] (user_project_wrapper) |
| 9.54 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45011_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[53] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45011_/CLK (DFFQ_X1_7T5P0) |
| 0.93 7.90 ^ soc/_45011_/Q (DFFQ_X1_7T5P0) |
| 0.28 8.18 v soc/_24270_/ZN (CLKINV_X1_7T5P0) |
| 0.31 8.48 v soc/output221/Z (CLKBUF_X4_7T5P0) |
| 0.75 9.24 ^ mgmt_buffers/_049_/ZN (INV_X1_7T5P0) |
| 0.24 9.48 v mgmt_buffers/la_buf[10]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.48 v mprj/la_data_in[53] (user_project_wrapper) |
| 9.48 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45013_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[51] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45013_/CLK (DFFQ_X1_7T5P0) |
| 0.98 7.95 ^ soc/_45013_/Q (DFFQ_X1_7T5P0) |
| 0.24 8.19 v soc/_24268_/ZN (CLKINV_X1_7T5P0) |
| 0.29 8.49 v soc/output223/Z (CLKBUF_X4_7T5P0) |
| 0.66 9.15 ^ mgmt_buffers/_051_/ZN (INV_X1_7T5P0) |
| 0.25 9.40 v mgmt_buffers/la_buf[12]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.40 v mprj/la_data_in[51] (user_project_wrapper) |
| 9.40 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45014_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[50] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45014_/CLK (DFFQ_X1_7T5P0) |
| 0.96 7.93 ^ soc/_45014_/Q (DFFQ_X1_7T5P0) |
| 0.19 8.12 v soc/_24267_/ZN (CLKINV_X1_7T5P0) |
| 0.28 8.40 v soc/output224/Z (CLKBUF_X4_7T5P0) |
| 0.66 9.06 ^ mgmt_buffers/_052_/ZN (INV_X1_7T5P0) |
| 0.25 9.30 v mgmt_buffers/la_buf[13]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.30 v mprj/la_data_in[50] (user_project_wrapper) |
| 9.30 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45015_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[49] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45015_/CLK (DFFQ_X1_7T5P0) |
| 0.95 7.92 ^ soc/_45015_/Q (DFFQ_X1_7T5P0) |
| 0.19 8.11 v soc/_24266_/ZN (CLKINV_X1_7T5P0) |
| 0.28 8.39 v soc/output225/Z (CLKBUF_X4_7T5P0) |
| 0.54 8.93 ^ mgmt_buffers/_053_/ZN (INV_X1_7T5P0) |
| 0.25 9.18 ^ mgmt_buffers/la_buf[14]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.18 ^ mprj/la_data_in[49] (user_project_wrapper) |
| 9.18 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45016_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_data_in[48] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45016_/CLK (DFFQ_X1_7T5P0) |
| 1.03 8.00 ^ soc/_45016_/Q (DFFQ_X1_7T5P0) |
| 0.21 8.21 v soc/_24265_/ZN (CLKINV_X1_7T5P0) |
| 0.29 8.49 v soc/output226/Z (CLKBUF_X4_7T5P0) |
| 0.36 8.85 ^ mgmt_buffers/_054_/ZN (INV_X1_7T5P0) |
| 0.24 9.10 ^ mgmt_buffers/la_buf[15]/Z (BUFZ_X8_7T5P0) |
| 0.00 9.10 ^ mprj/la_data_in[48] (user_project_wrapper) |
| 9.10 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42857_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[29] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.14 ^ soc/_42857_/CLK (DFFQ_X1_7T5P0) |
| 3.68 10.82 ^ soc/_42857_/Q (DFFQ_X1_7T5P0) |
| 0.63 11.45 v soc/_24246_/ZN (CLKINV_X1_7T5P0) |
| 0.47 11.92 v soc/output247/Z (CLKBUF_X4_7T5P0) |
| 0.22 12.14 v mgmt_buffers/_098_/Z (BUF_X1_7T5P0) |
| 0.00 12.14 v mprj/la_oenb[29] (user_project_wrapper) |
| 12.14 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42860_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[26] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.04 ^ soc/_42860_/CLK (DFFQ_X1_7T5P0) |
| 3.76 10.80 ^ soc/_42860_/Q (DFFQ_X1_7T5P0) |
| 0.45 11.25 v soc/_24243_/ZN (CLKINV_X1_7T5P0) |
| 0.45 11.70 v soc/output250/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.92 v mgmt_buffers/_101_/Z (BUF_X1_7T5P0) |
| 0.00 11.92 v mprj/la_oenb[26] (user_project_wrapper) |
| 11.92 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42861_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[25] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_42861_/CLK (DFFQ_X1_7T5P0) |
| 3.81 10.94 ^ soc/_42861_/Q (DFFQ_X1_7T5P0) |
| 0.30 11.24 v soc/_24242_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.66 v soc/output251/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.87 v mgmt_buffers/_102_/Z (BUF_X1_7T5P0) |
| 0.00 11.87 v mprj/la_oenb[25] (user_project_wrapper) |
| 11.87 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42855_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[31] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.04 ^ soc/_42855_/CLK (DFFQ_X1_7T5P0) |
| 3.43 10.47 ^ soc/_42855_/Q (DFFQ_X1_7T5P0) |
| 0.66 11.12 v soc/_24248_/ZN (CLKINV_X1_7T5P0) |
| 0.47 11.60 v soc/output245/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.81 v mgmt_buffers/_096_/Z (BUF_X1_7T5P0) |
| 0.00 11.81 v mprj/la_oenb[31] (user_project_wrapper) |
| 11.81 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42864_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[22] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42864_/CLK (DFFQ_X1_7T5P0) |
| 3.75 10.65 ^ soc/_42864_/Q (DFFQ_X1_7T5P0) |
| 0.41 11.05 v soc/_24239_/ZN (CLKINV_X1_7T5P0) |
| 0.44 11.50 v soc/output255/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.71 v mgmt_buffers/_105_/Z (BUF_X1_7T5P0) |
| 0.00 11.71 v mprj/la_oenb[22] (user_project_wrapper) |
| 11.71 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42885_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[1] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42885_/CLK (DFFQ_X1_7T5P0) |
| 3.46 10.34 ^ soc/_42885_/Q (DFFQ_X1_7T5P0) |
| 0.63 10.98 v soc/_24218_/ZN (CLKINV_X1_7T5P0) |
| 0.47 11.45 v soc/output278/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.66 v mgmt_buffers/_126_/Z (BUF_X1_7T5P0) |
| 0.00 11.66 v mprj/la_oenb[1] (user_project_wrapper) |
| 11.66 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42883_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[3] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42883_/CLK (DFFQ_X1_7T5P0) |
| 3.37 10.29 ^ soc/_42883_/Q (DFFQ_X1_7T5P0) |
| 0.65 10.94 v soc/_24220_/ZN (CLKINV_X1_7T5P0) |
| 0.47 11.41 v soc/output276/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.63 v mgmt_buffers/_124_/Z (BUF_X1_7T5P0) |
| 0.00 11.63 v mprj/la_oenb[3] (user_project_wrapper) |
| 11.63 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42856_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[30] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.07 ^ soc/_42856_/CLK (DFFQ_X1_7T5P0) |
| 3.34 10.41 ^ soc/_42856_/Q (DFFQ_X1_7T5P0) |
| 0.55 10.95 v soc/_24247_/ZN (CLKINV_X1_7T5P0) |
| 0.45 11.40 v soc/output246/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.62 v mgmt_buffers/_097_/Z (BUF_X1_7T5P0) |
| 0.00 11.62 v mprj/la_oenb[30] (user_project_wrapper) |
| 11.62 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42866_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[20] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42866_/CLK (DFFQ_X1_7T5P0) |
| 3.67 10.58 ^ soc/_42866_/Q (DFFQ_X1_7T5P0) |
| 0.32 10.90 v soc/_24237_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.32 v soc/output257/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.54 v mgmt_buffers/_107_/Z (BUF_X1_7T5P0) |
| 0.00 11.54 v mprj/la_oenb[20] (user_project_wrapper) |
| 11.54 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42862_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[24] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_42862_/CLK (DFFQ_X1_7T5P0) |
| 3.45 10.58 ^ soc/_42862_/Q (DFFQ_X1_7T5P0) |
| 0.33 10.91 v soc/_24241_/ZN (CLKINV_X1_7T5P0) |
| 0.41 11.32 v soc/output252/Z (CLKBUF_X4_7T5P0) |
| 0.21 11.54 v mgmt_buffers/_103_/Z (BUF_X1_7T5P0) |
| 0.00 11.54 v mprj/la_oenb[24] (user_project_wrapper) |
| 11.54 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42870_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[16] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42870_/CLK (DFFQ_X1_7T5P0) |
| 3.66 10.56 ^ soc/_42870_/Q (DFFQ_X1_7T5P0) |
| 0.34 10.89 v soc/_24233_/ZN (CLKINV_X1_7T5P0) |
| 0.43 11.32 v soc/output261/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.53 v mgmt_buffers/_111_/Z (BUF_X1_7T5P0) |
| 0.00 11.53 v mprj/la_oenb[16] (user_project_wrapper) |
| 11.53 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42871_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[15] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_42871_/CLK (DFFQ_X1_7T5P0) |
| 3.56 10.44 ^ soc/_42871_/Q (DFFQ_X1_7T5P0) |
| 0.41 10.85 v soc/_24232_/ZN (CLKINV_X1_7T5P0) |
| 0.44 11.29 v soc/output262/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.51 v mgmt_buffers/_112_/Z (BUF_X1_7T5P0) |
| 0.00 11.51 v mprj/la_oenb[15] (user_project_wrapper) |
| 11.51 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42863_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[23] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42863_/CLK (DFFQ_X1_7T5P0) |
| 3.61 10.51 ^ soc/_42863_/Q (DFFQ_X1_7T5P0) |
| 0.33 10.84 v soc/_24240_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.26 v soc/output254/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.48 v mgmt_buffers/_104_/Z (BUF_X1_7T5P0) |
| 0.00 11.48 v mprj/la_oenb[23] (user_project_wrapper) |
| 11.48 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42859_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[27] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_42859_/CLK (DFFQ_X1_7T5P0) |
| 3.32 10.45 ^ soc/_42859_/Q (DFFQ_X1_7T5P0) |
| 0.37 10.82 v soc/_24244_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.24 v soc/output249/Z (CLKBUF_X4_7T5P0) |
| 0.21 11.45 v mgmt_buffers/_100_/Z (BUF_X1_7T5P0) |
| 0.00 11.45 v mprj/la_oenb[27] (user_project_wrapper) |
| 11.45 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42858_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[28] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.13 ^ soc/_42858_/CLK (DFFQ_X1_7T5P0) |
| 3.24 10.36 ^ soc/_42858_/Q (DFFQ_X1_7T5P0) |
| 0.42 10.78 v soc/_24245_/ZN (CLKINV_X1_7T5P0) |
| 0.42 11.20 v soc/output248/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.42 v mgmt_buffers/_099_/Z (BUF_X1_7T5P0) |
| 0.00 11.42 v mprj/la_oenb[28] (user_project_wrapper) |
| 11.42 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42865_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[21] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42865_/CLK (DFFQ_X1_7T5P0) |
| 3.35 10.25 ^ soc/_42865_/Q (DFFQ_X1_7T5P0) |
| 0.43 10.69 v soc/_24238_/ZN (CLKINV_X1_7T5P0) |
| 0.43 11.12 v soc/output256/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.34 v mgmt_buffers/_106_/Z (BUF_X1_7T5P0) |
| 0.00 11.34 v mprj/la_oenb[21] (user_project_wrapper) |
| 11.34 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42872_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[14] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42872_/CLK (DFFQ_X1_7T5P0) |
| 3.19 10.10 ^ soc/_42872_/Q (DFFQ_X1_7T5P0) |
| 0.50 10.60 v soc/_24231_/ZN (CLKINV_X1_7T5P0) |
| 0.44 11.04 v soc/output263/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.26 v mgmt_buffers/_113_/Z (BUF_X1_7T5P0) |
| 0.00 11.26 v mprj/la_oenb[14] (user_project_wrapper) |
| 11.26 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42868_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[18] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42868_/CLK (DFFQ_X1_7T5P0) |
| 3.41 10.31 ^ soc/_42868_/Q (DFFQ_X1_7T5P0) |
| 0.31 10.62 v soc/_24235_/ZN (CLKINV_X1_7T5P0) |
| 0.41 11.03 v soc/output259/Z (CLKBUF_X4_7T5P0) |
| 0.21 11.25 v mgmt_buffers/_109_/Z (BUF_X1_7T5P0) |
| 0.00 11.25 v mprj/la_oenb[18] (user_project_wrapper) |
| 11.25 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42880_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[6] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42880_/CLK (DFFQ_X1_7T5P0) |
| 3.22 10.13 ^ soc/_42880_/Q (DFFQ_X1_7T5P0) |
| 0.45 10.59 v soc/_24223_/ZN (CLKINV_X1_7T5P0) |
| 0.43 11.02 v soc/output272/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.24 v mgmt_buffers/_121_/Z (BUF_X1_7T5P0) |
| 0.00 11.24 v mprj/la_oenb[6] (user_project_wrapper) |
| 11.24 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42886_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[0] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42886_/CLK (DFFQ_X1_7T5P0) |
| 3.26 10.14 ^ soc/_42886_/Q (DFFQ_X1_7T5P0) |
| 0.43 10.57 v soc/_24217_/ZN (CLKINV_X1_7T5P0) |
| 0.43 11.00 v soc/output279/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.22 v mgmt_buffers/_127_/Z (BUF_X1_7T5P0) |
| 0.00 11.22 v mprj/la_oenb[0] (user_project_wrapper) |
| 11.22 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42869_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[17] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42869_/CLK (DFFQ_X1_7T5P0) |
| 3.27 10.17 ^ soc/_42869_/Q (DFFQ_X1_7T5P0) |
| 0.35 10.52 v soc/_24234_/ZN (CLKINV_X1_7T5P0) |
| 0.42 10.93 v soc/output260/Z (CLKBUF_X4_7T5P0) |
| 0.21 11.15 v mgmt_buffers/_110_/Z (BUF_X1_7T5P0) |
| 0.00 11.15 v mprj/la_oenb[17] (user_project_wrapper) |
| 11.15 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42867_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[19] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42867_/CLK (DFFQ_X1_7T5P0) |
| 3.26 10.16 ^ soc/_42867_/Q (DFFQ_X1_7T5P0) |
| 0.31 10.47 v soc/_24236_/ZN (CLKINV_X1_7T5P0) |
| 0.41 10.88 v soc/output258/Z (CLKBUF_X4_7T5P0) |
| 0.21 11.10 v mgmt_buffers/_108_/Z (BUF_X1_7T5P0) |
| 0.00 11.10 v mprj/la_oenb[19] (user_project_wrapper) |
| 11.10 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42884_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[2] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42884_/CLK (DFFQ_X1_7T5P0) |
| 2.87 9.78 ^ soc/_42884_/Q (DFFQ_X1_7T5P0) |
| 0.64 10.42 v soc/_24219_/ZN (CLKINV_X1_7T5P0) |
| 0.45 10.88 v soc/output277/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.09 v mgmt_buffers/_125_/Z (BUF_X1_7T5P0) |
| 0.00 11.09 v mprj/la_oenb[2] (user_project_wrapper) |
| 11.09 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42879_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[7] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42879_/CLK (DFFQ_X1_7T5P0) |
| 2.94 9.85 ^ soc/_42879_/Q (DFFQ_X1_7T5P0) |
| 0.54 10.39 v soc/_24224_/ZN (CLKINV_X1_7T5P0) |
| 0.44 10.83 v soc/output271/Z (CLKBUF_X4_7T5P0) |
| 0.22 11.05 v mgmt_buffers/_120_/Z (BUF_X1_7T5P0) |
| 0.00 11.05 v mprj/la_oenb[7] (user_project_wrapper) |
| 11.05 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42875_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[11] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42875_/CLK (DFFQ_X1_7T5P0) |
| 2.80 9.70 ^ soc/_42875_/Q (DFFQ_X1_7T5P0) |
| 0.58 10.27 v soc/_24228_/ZN (CLKINV_X1_7T5P0) |
| 0.44 10.71 v soc/output267/Z (CLKBUF_X4_7T5P0) |
| 0.22 10.93 v mgmt_buffers/_116_/Z (BUF_X1_7T5P0) |
| 0.00 10.93 v mprj/la_oenb[11] (user_project_wrapper) |
| 10.93 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42881_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[5] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42881_/CLK (DFFQ_X1_7T5P0) |
| 2.90 9.79 ^ soc/_42881_/Q (DFFQ_X1_7T5P0) |
| 0.43 10.22 v soc/_24222_/ZN (CLKINV_X1_7T5P0) |
| 0.42 10.63 v soc/output273/Z (CLKBUF_X4_7T5P0) |
| 0.21 10.85 v mgmt_buffers/_122_/Z (BUF_X1_7T5P0) |
| 0.00 10.85 v mprj/la_oenb[5] (user_project_wrapper) |
| 10.85 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42882_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[4] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.91 ^ soc/_42882_/CLK (DFFQ_X1_7T5P0) |
| 2.83 9.74 ^ soc/_42882_/Q (DFFQ_X1_7T5P0) |
| 0.40 10.14 v soc/_24221_/ZN (CLKINV_X1_7T5P0) |
| 0.41 10.55 v soc/output274/Z (CLKBUF_X4_7T5P0) |
| 0.21 10.77 v mgmt_buffers/_123_/Z (BUF_X1_7T5P0) |
| 0.00 10.77 v mprj/la_oenb[4] (user_project_wrapper) |
| 10.77 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42877_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[9] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42877_/CLK (DFFQ_X1_7T5P0) |
| 2.90 9.80 ^ soc/_42877_/Q (DFFQ_X1_7T5P0) |
| 0.30 10.10 v soc/_24226_/ZN (CLKINV_X1_7T5P0) |
| 0.39 10.49 v soc/output269/Z (CLKBUF_X4_7T5P0) |
| 0.21 10.71 v mgmt_buffers/_118_/Z (BUF_X1_7T5P0) |
| 0.00 10.71 v mprj/la_oenb[9] (user_project_wrapper) |
| 10.71 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42878_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[8] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42878_/CLK (DFFQ_X1_7T5P0) |
| 2.88 9.78 ^ soc/_42878_/Q (DFFQ_X1_7T5P0) |
| 0.29 10.07 v soc/_24225_/ZN (CLKINV_X1_7T5P0) |
| 0.39 10.46 v soc/output270/Z (CLKBUF_X4_7T5P0) |
| 0.21 10.68 v mgmt_buffers/_119_/Z (BUF_X1_7T5P0) |
| 0.00 10.68 v mprj/la_oenb[8] (user_project_wrapper) |
| 10.68 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42874_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[12] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_42874_/CLK (DFFQ_X1_7T5P0) |
| 2.52 9.40 ^ soc/_42874_/Q (DFFQ_X1_7T5P0) |
| 0.49 9.89 v soc/_24229_/ZN (CLKINV_X1_7T5P0) |
| 0.42 10.31 v soc/output266/Z (CLKBUF_X4_7T5P0) |
| 0.21 10.52 v mgmt_buffers/_115_/Z (BUF_X1_7T5P0) |
| 0.00 10.52 v mprj/la_oenb[12] (user_project_wrapper) |
| 10.52 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42876_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[10] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_42876_/CLK (DFFQ_X1_7T5P0) |
| 2.19 9.09 ^ soc/_42876_/Q (DFFQ_X1_7T5P0) |
| 0.42 9.51 v soc/_24227_/ZN (CLKINV_X1_7T5P0) |
| 0.39 9.90 v soc/output268/Z (CLKBUF_X4_7T5P0) |
| 0.21 10.11 v mgmt_buffers/_117_/Z (BUF_X1_7T5P0) |
| 0.00 10.11 v mprj/la_oenb[10] (user_project_wrapper) |
| 10.11 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45002_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[62] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.05 ^ soc/_45002_/CLK (DFFQ_X1_7T5P0) |
| 2.06 9.11 ^ soc/_45002_/Q (DFFQ_X1_7T5P0) |
| 0.35 9.45 v soc/_24279_/ZN (CLKINV_X1_7T5P0) |
| 0.37 9.83 v soc/output231/Z (CLKBUF_X4_7T5P0) |
| 0.21 10.04 v mgmt_buffers/_065_/Z (BUF_X1_7T5P0) |
| 0.00 10.04 v mprj/la_oenb[62] (user_project_wrapper) |
| 10.04 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_42873_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[13] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_42873_/CLK (DFFQ_X1_7T5P0) |
| 2.03 8.93 ^ soc/_42873_/Q (DFFQ_X1_7T5P0) |
| 0.44 9.36 v soc/_24230_/ZN (CLKINV_X1_7T5P0) |
| 0.39 9.75 v soc/output265/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.96 v mgmt_buffers/_114_/Z (BUF_X1_7T5P0) |
| 0.00 9.96 v mprj/la_oenb[13] (user_project_wrapper) |
| 9.96 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45005_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[59] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_45005_/CLK (DFFQ_X1_7T5P0) |
| 1.83 8.74 ^ soc/_45005_/Q (DFFQ_X1_7T5P0) |
| 0.52 9.26 v soc/_24276_/ZN (CLKINV_X1_7T5P0) |
| 0.40 9.65 v soc/output264/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.87 v mgmt_buffers/_068_/Z (BUF_X1_7T5P0) |
| 0.00 9.87 v mprj/la_oenb[59] (user_project_wrapper) |
| 9.87 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45001_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[63] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 7.05 ^ soc/_45001_/CLK (DFFQ_X1_7T5P0) |
| 1.95 9.00 ^ soc/_45001_/Q (DFFQ_X1_7T5P0) |
| 0.26 9.26 v soc/_24280_/ZN (CLKINV_X1_7T5P0) |
| 0.35 9.61 v soc/output220/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.82 v mgmt_buffers/_064_/Z (BUF_X1_7T5P0) |
| 0.00 9.82 v mprj/la_oenb[63] (user_project_wrapper) |
| 9.82 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45004_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[60] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_45004_/CLK (DFFQ_X1_7T5P0) |
| 1.90 8.79 ^ soc/_45004_/Q (DFFQ_X1_7T5P0) |
| 0.41 9.20 v soc/_24277_/ZN (CLKINV_X1_7T5P0) |
| 0.38 9.58 v soc/output253/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.79 v mgmt_buffers/_067_/Z (BUF_X1_7T5P0) |
| 0.00 9.79 v mprj/la_oenb[60] (user_project_wrapper) |
| 9.79 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45008_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[56] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_45008_/CLK (DFFQ_X1_7T5P0) |
| 1.88 8.78 ^ soc/_45008_/Q (DFFQ_X1_7T5P0) |
| 0.37 9.15 v soc/_24273_/ZN (CLKINV_X1_7T5P0) |
| 0.37 9.52 v soc/output281/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.73 v mgmt_buffers/_071_/Z (BUF_X1_7T5P0) |
| 0.00 9.73 v mprj/la_oenb[56] (user_project_wrapper) |
| 9.73 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45003_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[61] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_45003_/CLK (DFFQ_X1_7T5P0) |
| 1.16 8.05 ^ soc/_45003_/Q (DFFQ_X1_7T5P0) |
| 0.98 9.02 v soc/_24278_/ZN (CLKINV_X1_7T5P0) |
| 0.49 9.51 v soc/output242/Z (CLKBUF_X4_7T5P0) |
| 0.22 9.73 v mgmt_buffers/_066_/Z (BUF_X1_7T5P0) |
| 0.00 9.73 v mprj/la_oenb[61] (user_project_wrapper) |
| 9.73 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45021_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[43] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45021_/CLK (DFFQ_X1_7T5P0) |
| 1.80 8.75 ^ soc/_45021_/Q (DFFQ_X1_7T5P0) |
| 0.35 9.10 v soc/_24260_/ZN (CLKINV_X1_7T5P0) |
| 0.36 9.46 v soc/output232/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.67 v mgmt_buffers/_084_/Z (BUF_X1_7T5P0) |
| 0.00 9.67 v mprj/la_oenb[43] (user_project_wrapper) |
| 9.67 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45018_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[46] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_45018_/CLK (DFFQ_X1_7T5P0) |
| 1.63 8.52 ^ soc/_45018_/Q (DFFQ_X1_7T5P0) |
| 0.48 9.00 v soc/_24263_/ZN (CLKINV_X1_7T5P0) |
| 0.38 9.38 v soc/output228/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.59 v mgmt_buffers/_081_/Z (BUF_X1_7T5P0) |
| 0.00 9.59 v mprj/la_oenb[46] (user_project_wrapper) |
| 9.59 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45029_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[35] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45029_/CLK (DFFQ_X1_7T5P0) |
| 1.78 8.72 ^ soc/_45029_/Q (DFFQ_X1_7T5P0) |
| 0.27 8.99 v soc/_24252_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.32 v soc/output240/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.54 v mgmt_buffers/_092_/Z (BUF_X1_7T5P0) |
| 0.00 9.54 v mprj/la_oenb[35] (user_project_wrapper) |
| 9.54 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45023_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[41] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45023_/CLK (DFFQ_X1_7T5P0) |
| 1.68 8.63 ^ soc/_45023_/Q (DFFQ_X1_7T5P0) |
| 0.32 8.95 v soc/_24258_/ZN (CLKINV_X1_7T5P0) |
| 0.35 9.30 v soc/output234/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.51 v mgmt_buffers/_086_/Z (BUF_X1_7T5P0) |
| 0.00 9.51 v mprj/la_oenb[41] (user_project_wrapper) |
| 9.51 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45020_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[44] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45020_/CLK (DFFQ_X1_7T5P0) |
| 1.61 8.56 ^ soc/_45020_/Q (DFFQ_X1_7T5P0) |
| 0.35 8.90 v soc/_24261_/ZN (CLKINV_X1_7T5P0) |
| 0.35 9.25 v soc/output230/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.46 v mgmt_buffers/_083_/Z (BUF_X1_7T5P0) |
| 0.00 9.46 v mprj/la_oenb[44] (user_project_wrapper) |
| 9.46 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45024_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[40] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45024_/CLK (DFFQ_X1_7T5P0) |
| 1.64 8.59 ^ soc/_45024_/Q (DFFQ_X1_7T5P0) |
| 0.28 8.87 v soc/_24257_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.21 v soc/output235/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.42 v mgmt_buffers/_087_/Z (BUF_X1_7T5P0) |
| 0.00 9.42 v mprj/la_oenb[40] (user_project_wrapper) |
| 9.42 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45019_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[45] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.95 ^ soc/_45019_/CLK (DFFQ_X1_7T5P0) |
| 1.58 8.53 ^ soc/_45019_/Q (DFFQ_X1_7T5P0) |
| 0.31 8.84 v soc/_24262_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.18 v soc/output229/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.40 v mgmt_buffers/_082_/Z (BUF_X1_7T5P0) |
| 0.00 9.40 v mprj/la_oenb[45] (user_project_wrapper) |
| 9.40 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45017_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[47] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.95 ^ soc/_45017_/CLK (DFFQ_X1_7T5P0) |
| 1.53 8.48 ^ soc/_45017_/Q (DFFQ_X1_7T5P0) |
| 0.34 8.82 v soc/_24264_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.16 v soc/output227/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.37 v mgmt_buffers/_080_/Z (BUF_X1_7T5P0) |
| 0.00 9.37 v mprj/la_oenb[47] (user_project_wrapper) |
| 9.37 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45025_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[39] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_45025_/CLK (DFFQ_X1_7T5P0) |
| 1.57 8.47 ^ soc/_45025_/Q (DFFQ_X1_7T5P0) |
| 0.34 8.81 v soc/_24256_/ZN (CLKINV_X1_7T5P0) |
| 0.35 9.15 v soc/output236/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.36 v mgmt_buffers/_088_/Z (BUF_X1_7T5P0) |
| 0.00 9.36 v mprj/la_oenb[39] (user_project_wrapper) |
| 9.36 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45026_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[38] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45026_/CLK (DFFQ_X1_7T5P0) |
| 1.48 8.42 ^ soc/_45026_/Q (DFFQ_X1_7T5P0) |
| 0.35 8.77 v soc/_24255_/ZN (CLKINV_X1_7T5P0) |
| 0.34 9.11 v soc/output237/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.32 v mgmt_buffers/_089_/Z (BUF_X1_7T5P0) |
| 0.00 9.32 v mprj/la_oenb[38] (user_project_wrapper) |
| 9.32 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45022_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[42] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45022_/CLK (DFFQ_X1_7T5P0) |
| 1.48 8.43 ^ soc/_45022_/Q (DFFQ_X1_7T5P0) |
| 0.30 8.72 v soc/_24259_/ZN (CLKINV_X1_7T5P0) |
| 0.33 9.06 v soc/output233/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.27 v mgmt_buffers/_085_/Z (BUF_X1_7T5P0) |
| 0.00 9.27 v mprj/la_oenb[42] (user_project_wrapper) |
| 9.27 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45006_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[58] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.90 ^ soc/_45006_/CLK (DFFQ_X1_7T5P0) |
| 0.98 7.88 ^ soc/_45006_/Q (DFFQ_X1_7T5P0) |
| 0.63 8.50 v soc/_24275_/ZN (CLKINV_X1_7T5P0) |
| 0.42 8.92 v soc/output275/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.14 v mgmt_buffers/_069_/Z (BUF_X1_7T5P0) |
| 0.00 9.14 v mprj/la_oenb[58] (user_project_wrapper) |
| 9.14 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45007_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[57] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.89 ^ soc/_45007_/CLK (DFFQ_X1_7T5P0) |
| 1.04 7.93 ^ soc/_45007_/Q (DFFQ_X1_7T5P0) |
| 0.58 8.51 v soc/_24274_/ZN (CLKINV_X1_7T5P0) |
| 0.40 8.91 v soc/output280/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.12 v mgmt_buffers/_070_/Z (BUF_X1_7T5P0) |
| 0.00 9.12 v mprj/la_oenb[57] (user_project_wrapper) |
| 9.12 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45028_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[36] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45028_/CLK (DFFQ_X1_7T5P0) |
| 1.31 8.26 ^ soc/_45028_/Q (DFFQ_X1_7T5P0) |
| 0.28 8.53 v soc/_24253_/ZN (CLKINV_X1_7T5P0) |
| 0.32 8.85 v soc/output239/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.06 v mgmt_buffers/_091_/Z (BUF_X1_7T5P0) |
| 0.00 9.06 v mprj/la_oenb[36] (user_project_wrapper) |
| 9.06 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45027_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[37] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.88 ^ soc/_45027_/CLK (DFFQ_X1_7T5P0) |
| 1.34 8.22 ^ soc/_45027_/Q (DFFQ_X1_7T5P0) |
| 0.28 8.50 v soc/_24254_/ZN (CLKINV_X1_7T5P0) |
| 0.32 8.82 v soc/output238/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.03 v mgmt_buffers/_090_/Z (BUF_X1_7T5P0) |
| 0.00 9.03 v mprj/la_oenb[37] (user_project_wrapper) |
| 9.03 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45032_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[32] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45032_/CLK (DFFQ_X1_7T5P0) |
| 1.33 8.27 ^ soc/_45032_/Q (DFFQ_X1_7T5P0) |
| 0.23 8.50 v soc/_24249_/ZN (CLKINV_X1_7T5P0) |
| 0.31 8.81 v soc/output244/Z (CLKBUF_X4_7T5P0) |
| 0.21 9.02 v mgmt_buffers/_095_/Z (BUF_X1_7T5P0) |
| 0.00 9.02 v mprj/la_oenb[32] (user_project_wrapper) |
| 9.02 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45030_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[34] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45030_/CLK (DFFQ_X1_7T5P0) |
| 1.24 8.18 ^ soc/_45030_/Q (DFFQ_X1_7T5P0) |
| 0.28 8.46 v soc/_24251_/ZN (CLKINV_X1_7T5P0) |
| 0.32 8.78 v soc/output241/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.99 v mgmt_buffers/_093_/Z (BUF_X1_7T5P0) |
| 0.00 8.99 v mprj/la_oenb[34] (user_project_wrapper) |
| 8.99 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45031_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[33] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.94 ^ soc/_45031_/CLK (DFFQ_X1_7T5P0) |
| 1.25 8.19 ^ soc/_45031_/Q (DFFQ_X1_7T5P0) |
| 0.24 8.43 v soc/_24250_/ZN (CLKINV_X1_7T5P0) |
| 0.31 8.74 v soc/output243/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.95 v mgmt_buffers/_094_/Z (BUF_X1_7T5P0) |
| 0.00 8.95 v mprj/la_oenb[33] (user_project_wrapper) |
| 8.95 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45012_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[52] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45012_/CLK (DFFQ_X1_7T5P0) |
| 0.97 7.95 ^ soc/_45012_/Q (DFFQ_X1_7T5P0) |
| 0.29 8.24 v soc/_24269_/ZN (CLKINV_X1_7T5P0) |
| 0.31 8.55 v soc/output222/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.76 v mgmt_buffers/_075_/Z (BUF_X1_7T5P0) |
| 0.00 8.76 v mprj/la_oenb[52] (user_project_wrapper) |
| 8.76 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45009_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[55] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45009_/CLK (DFFQ_X1_7T5P0) |
| 1.04 8.01 ^ soc/_45009_/Q (DFFQ_X1_7T5P0) |
| 0.21 8.23 v soc/_24272_/ZN (CLKINV_X1_7T5P0) |
| 0.29 8.52 v soc/output282/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.73 v mgmt_buffers/_072_/Z (BUF_X1_7T5P0) |
| 0.00 8.73 v mprj/la_oenb[55] (user_project_wrapper) |
| 8.73 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45010_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[54] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45010_/CLK (DFFQ_X1_7T5P0) |
| 1.04 8.02 ^ soc/_45010_/Q (DFFQ_X1_7T5P0) |
| 0.20 8.21 v soc/_24271_/ZN (CLKINV_X1_7T5P0) |
| 0.28 8.50 v soc/output283/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.71 v mgmt_buffers/_073_/Z (BUF_X1_7T5P0) |
| 0.00 8.71 v mprj/la_oenb[54] (user_project_wrapper) |
| 8.71 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45016_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[48] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45016_/CLK (DFFQ_X1_7T5P0) |
| 1.03 8.00 ^ soc/_45016_/Q (DFFQ_X1_7T5P0) |
| 0.21 8.21 v soc/_24265_/ZN (CLKINV_X1_7T5P0) |
| 0.29 8.49 v soc/output226/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.70 v mgmt_buffers/_079_/Z (BUF_X1_7T5P0) |
| 0.00 8.70 v mprj/la_oenb[48] (user_project_wrapper) |
| 8.70 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45013_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[51] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45013_/CLK (DFFQ_X1_7T5P0) |
| 0.98 7.95 ^ soc/_45013_/Q (DFFQ_X1_7T5P0) |
| 0.24 8.19 v soc/_24268_/ZN (CLKINV_X1_7T5P0) |
| 0.29 8.49 v soc/output223/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.70 v mgmt_buffers/_076_/Z (BUF_X1_7T5P0) |
| 0.00 8.70 v mprj/la_oenb[51] (user_project_wrapper) |
| 8.70 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45011_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[53] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45011_/CLK (DFFQ_X1_7T5P0) |
| 0.93 7.90 ^ soc/_45011_/Q (DFFQ_X1_7T5P0) |
| 0.28 8.18 v soc/_24270_/ZN (CLKINV_X1_7T5P0) |
| 0.31 8.48 v soc/output221/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.69 v mgmt_buffers/_074_/Z (BUF_X1_7T5P0) |
| 0.00 8.69 v mprj/la_oenb[53] (user_project_wrapper) |
| 8.69 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45014_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[50] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45014_/CLK (DFFQ_X1_7T5P0) |
| 0.96 7.93 ^ soc/_45014_/Q (DFFQ_X1_7T5P0) |
| 0.19 8.12 v soc/_24267_/ZN (CLKINV_X1_7T5P0) |
| 0.28 8.40 v soc/output224/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.61 v mgmt_buffers/_077_/Z (BUF_X1_7T5P0) |
| 0.00 8.61 v mprj/la_oenb[50] (user_project_wrapper) |
| 8.61 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Startpoint: soc/_45015_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: mprj/la_oenb[49] (internal pin) |
| Path Group: (none) |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 6.97 ^ soc/_45015_/CLK (DFFQ_X1_7T5P0) |
| 0.95 7.92 ^ soc/_45015_/Q (DFFQ_X1_7T5P0) |
| 0.19 8.11 v soc/_24266_/ZN (CLKINV_X1_7T5P0) |
| 0.28 8.39 v soc/output225/Z (CLKBUF_X4_7T5P0) |
| 0.21 8.59 v mgmt_buffers/_078_/Z (BUF_X1_7T5P0) |
| 0.00 8.59 v mprj/la_oenb[49] (user_project_wrapper) |
| 8.59 data arrival time |
| --------------------------------------------------------- |
| (Path is unconstrained) |
| |
| |
| Flash output Interface |
| Startpoint: soc/_46499_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: flash_clk (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 6.71 6.71 clock network delay (propagated) |
| 0.00 6.71 ^ soc/_46499_/CLK (DFFQ_X1_7T5P0) |
| 5.06 11.77 ^ soc/_46499_/Q (DFFQ_X1_7T5P0) |
| 0.92 12.70 ^ soc/output145/Z (CLKBUF_X4_7T5P0) |
| 1.40 14.10 ^ housekeeping/input84/Z (CLKBUF_X1_7T5P0) |
| 0.12 14.22 v housekeeping/_06711_/ZN (NAND2_X1_7T5P0) |
| 0.81 15.02 ^ housekeeping/_06713_/ZN (NAND2_X1_7T5P0) |
| 0.51 15.53 ^ housekeeping/output249/Z (CLKBUF_X4_7T5P0) |
| 2.76 18.29 ^ padframe/flash_clk_pad/PAD (GF_NI_BI_T) |
| 0.00 18.29 ^ flash_clk (inout) |
| 18.29 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock network delay (propagated) |
| -0.25 24.75 clock uncertainty |
| 0.00 24.75 clock reconvergence pessimism |
| -5.00 19.75 output external delay |
| 19.75 data required time |
| --------------------------------------------------------- |
| 19.75 data required time |
| -18.29 data arrival time |
| --------------------------------------------------------- |
| 1.46 slack (MET) |
| |
| |
| Startpoint: soc/_45619_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: flash_csb (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 6.87 6.87 clock network delay (propagated) |
| 0.00 6.87 ^ soc/_45619_/CLK (DFFQ_X1_7T5P0) |
| 0.91 7.77 v soc/_45619_/Q (DFFQ_X1_7T5P0) |
| 0.71 8.48 ^ soc/_20972_/ZN (NOR3_X1_7T5P0) |
| 0.63 9.12 ^ soc/_20973_/Z (AND2_X1_7T5P0) |
| 6.18 15.30 v soc/_20974_/ZN (CLKINV_X1_7T5P0) |
| 1.51 16.80 v soc/output146/Z (CLKBUF_X4_7T5P0) |
| 1.40 18.21 v housekeeping/input85/Z (CLKBUF_X1_7T5P0) |
| 0.65 18.85 ^ housekeeping/_06708_/ZN (NAND2_X1_7T5P0) |
| 0.59 19.45 v housekeeping/_06710_/ZN (NAND2_X1_7T5P0) |
| 0.50 19.94 v housekeeping/output251/Z (CLKBUF_X4_7T5P0) |
| 2.55 22.50 v padframe/flash_csb_pad/PAD (GF_NI_BI_T) |
| 0.00 22.50 v flash_csb (inout) |
| 22.50 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock network delay (propagated) |
| -0.25 24.75 clock uncertainty |
| 0.00 24.75 clock reconvergence pessimism |
| -4.50 20.25 output external delay |
| 20.25 data required time |
| --------------------------------------------------------- |
| 20.25 data required time |
| -22.50 data arrival time |
| --------------------------------------------------------- |
| -2.25 slack (VIOLATED) |
| |
| |
| Startpoint: soc/_46501_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: flash_io0 (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock clock (rise edge) |
| 7.36 7.36 clock network delay (propagated) |
| 0.00 7.36 ^ soc/_46501_/CLK (DFFQ_X1_7T5P0) |
| 0.72 8.08 v soc/_46501_/Q (DFFQ_X1_7T5P0) |
| 0.24 8.31 v soc/output147/Z (CLKBUF_X4_7T5P0) |
| 1.39 9.70 v housekeeping/input86/Z (CLKBUF_X1_7T5P0) |
| 0.64 10.34 ^ housekeeping/_06719_/ZN (NAND2_X1_7T5P0) |
| 0.53 10.88 v housekeeping/_06720_/ZN (OAI21_X1_7T5P0) |
| 0.42 11.30 v housekeeping/_06721_/Z (CLKBUF_X1_7T5P0) |
| 0.36 11.66 v housekeeping/output253/Z (CLKBUF_X4_7T5P0) |
| 2.55 14.20 v padframe/flash_io0_pad/PAD (GF_NI_BI_T) |
| 0.00 14.20 v flash_io0 (inout) |
| 14.20 data arrival time |
| |
| 25.00 25.00 clock clock (rise edge) |
| 0.00 25.00 clock network delay (propagated) |
| -0.25 24.75 clock uncertainty |
| 0.00 24.75 clock reconvergence pessimism |
| -5.00 19.75 output external delay |
| 19.75 data required time |
| --------------------------------------------------------- |
| 19.75 data required time |
| -14.20 data arrival time |
| --------------------------------------------------------- |
| 5.55 slack (MET) |
| |
| |
| report_worst_slack -max (SETUP) |
| worst slack -34.47 |
| report_worst_slack -min (HOLD) |
| worst slack -0.85 |
